GB2156553B - Semiconductor memory redundancy circuit - Google Patents

Semiconductor memory redundancy circuit

Info

Publication number
GB2156553B
GB2156553B GB8505764A GB8505764A GB2156553B GB 2156553 B GB2156553 B GB 2156553B GB 8505764 A GB8505764 A GB 8505764A GB 8505764 A GB8505764 A GB 8505764A GB 2156553 B GB2156553 B GB 2156553B
Authority
GB
United Kingdom
Prior art keywords
ordinary
memory
word line
memory section
redundancy circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB8505764A
Other versions
GB8505764D0 (en
GB2156553A (en
Inventor
Munehiro Uratani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Publication of GB8505764D0 publication Critical patent/GB8505764D0/en
Publication of GB2156553A publication Critical patent/GB2156553A/en
Application granted granted Critical
Publication of GB2156553B publication Critical patent/GB2156553B/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/84—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/83—Masking faults in memories by using spares or by reconfiguring using programmable devices with reduced power consumption
    • G11C29/832—Masking faults in memories by using spares or by reconfiguring using programmable devices with reduced power consumption with disconnection of faulty elements

Landscapes

  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Semiconductor Memories (AREA)

Abstract

A redundancy circuit for a semiconductor memory includes an ordinary decoder which selects a desired memory section in an ordinary memory, and a spare decoder which selects a desired memory section in a spare memory. The ordinary decoder includes a plurality of output inverters, each of which is connected to the corresponding ordinary memory section via an ordinary memory word line. A fuse is disposed in the ordinary memory word line so that the output inverter is disconnected from the ordinary memory section when some defects are included in the corresponding ordinary memory section. A pull-down transistor is connected to the ordinary memory word line in order to permanently maintain the ordinary memory word line at the logic low when the corresponding fuse is burned out. <IMAGE>
GB8505764A 1984-03-08 1985-03-06 Semiconductor memory redundancy circuit Expired GB2156553B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59045102A JPS60191500A (en) 1984-03-08 1984-03-08 Redundancy circuit

Publications (3)

Publication Number Publication Date
GB8505764D0 GB8505764D0 (en) 1985-04-11
GB2156553A GB2156553A (en) 1985-10-09
GB2156553B true GB2156553B (en) 1988-04-20

Family

ID=12709923

Family Applications (1)

Application Number Title Priority Date Filing Date
GB8505764A Expired GB2156553B (en) 1984-03-08 1985-03-06 Semiconductor memory redundancy circuit

Country Status (3)

Country Link
JP (1) JPS60191500A (en)
DE (1) DE3508157A1 (en)
GB (1) GB2156553B (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0213044A3 (en) * 1985-08-20 1989-03-22 STMicroelectronics, Inc. Defective element disabling circuit having a laser-blown fuse
JPS63168900A (en) * 1987-01-06 1988-07-12 Toshiba Corp Semiconductor memory

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57150197A (en) * 1981-03-11 1982-09-16 Nippon Telegr & Teleph Corp <Ntt> Storage circuit
JPS58164099A (en) * 1982-03-25 1983-09-28 Toshiba Corp Semiconductor memory
JPS58208998A (en) * 1982-05-28 1983-12-05 Toshiba Corp Semiconductor memory device
US4494220A (en) * 1982-11-24 1985-01-15 At&T Bell Laboratories Folded bit line memory with one decoder per pair of spare rows
US4538247A (en) * 1983-01-14 1985-08-27 Fairchild Research Center Redundant rows in integrated circuit memories
JPS59151398A (en) * 1983-02-17 1984-08-29 Mitsubishi Electric Corp Semiconductor storage device

Also Published As

Publication number Publication date
GB8505764D0 (en) 1985-04-11
DE3508157A1 (en) 1985-09-19
DE3508157C2 (en) 1988-04-28
GB2156553A (en) 1985-10-09
JPS60191500A (en) 1985-09-28

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Legal Events

Date Code Title Description
PE20 Patent expired after termination of 20 years

Effective date: 20050305