GB2256070A

GB2256070A - Semiconductor memory device with redundancy

Info

Publication number: GB2256070A
Application number: GB9116165A
Authority: GB
Inventors: Hyun-Soon Jang; Kyu-Chan Lee
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 1991-05-24
Filing date: 1991-07-26
Publication date: 1992-11-25
Also published as: KR920022148A; ITMI912229A0; JPH04346000A; GB9116165D0; DE4124572A1; FR2676844A1; ITMI912229A1; TW217455B; KR940002272B1; IT1251003B; DE4124572C2

Abstract

A semiconductor memory device, with redundancy device, prevents access time of a row address from being delayed in a normal operation mode. By using a mode detect signal generated by detecting whether or not the memory device will be repaired, the row address is directly accessed without passing through a delay circuit in the normal operation mode, while the access of the row address is delayed in the redundant operation mode. To this end, the device comprises a detecting circuit for generating the mode detect signal MD in dependence upon turning on/off of a fuse 116, a first transfer path 201 transferring a buffered row address without delay, a second transfer path 202 delaying the buffered row address through a delay circuit 130, and a path select circuit 120 selecting either the first transfer path 201 or the second transfer path 202 in dependence upon the mode detect signal MD, to transfer a signal of a selected path to a boost clock generator. <IMAGE>

Description

2 25) 6 u. t11) SENUCONDUCTOR MEMORY DEVICE WITH REDUNDANCY The present

invention relates to a semiconductor memory device having a redundancy scheme.

Generally, a semiconductor memory device is provided with a spare cell array in addition to a normal cell array. The spare cells of the spare cell array serve to replace the normal cells when any defect in the normal cells is detected. For the purpose of this, the memory device usually includes a detecting means, such as a fuse circuit, capable of recognizing a defective address, and a redundant decoder for selecting a redundant word line of the spare cell array from the detected defective address. Furthermore, the memory device must be internally chosen to perform either normal operation mode or redundant operation mode. Such a selection is performed through a row address. As is well known in the art, a row address is used to decode a word line of the memory cell array, and to determine a holding time of a boost clock pulse used for raising a voltage level of the word lines. If a defective cell needs to be repaired that is, redundancy operation is required, the fuse is cut off from a power source terminal electrically or by using a laser beam, thereby selecting the redundant operation mode from the corresponding row address.

Referring to Figure 1 of the accompanying diagrammatic drawings, which illustrates a conventional circuit for performing redundant or normal row decoding by receiving an external input address in a memory device, the external input address XA is converted to row address RA by the operation of a row address buffer 10. The row address RA is transferred, through first and second delay circuits 20 and 30, to a boost clock pulse generator 40 and redundant enable circuit 60, while it is directly transferred to a row fuse circuit 50, to detect a row address indicating a defective cell, and to send a fuse signal Fo corresponding thereto to the redundant enable circuit 60. The 1 reason that the same row address RA is accessed through two different paths, i.e., one path by way of the first and second delay circuits 20 and 30, and the other path by way of the row fuse circuit 50, is to cause the first and second delay circuits 20 and 30 to delay the row address signal whilst the row fuse circuit 50 detects the row address corresponding to a defective cell. Thus, if there exists a row address corresponding to a defective cell, the redundant enable circuit 60 generates a redundant enable signal RRE to perform repairing of the defective cell (redundant operation mode). The redundant enable signal RRE disables a boost clock pulse decoder 70 decoding boost clock pulses BST generated by the boost clock pulse generator 40, thereby stopping the operation of a normal row decoder 100. Hence, a redundant row decoder 90 receives the redundant enable signal RRE and boost clock pulses BST so as to select the corresponding redundant word line in the redundant cell array. On the other hand, if there does not exist a row address corresponding to a defective cell, the redundant row decoder 90 is not operated. Even in this case, the first and second delay circuits 20 and 30 together with the row fuse circuit 50 are operated either to select the redundant operation mode or to select the normal operation mode.

Consequently, regardless of performance of either redundant operation mode or normal mode, the row address selecting a word line is delayed through the first and second delay circuits 20 and 30. That is, the address access time is unnecessarily delayed, even though the repairing of the memory is not required. Thus, the normal operation mode requires a long access time, to reduce the whole operational speed of the memory.

1 Preferred embodiments of the present invention aim to provide a device with redundancy capable of improving its operation speed by preventing the occurrence of undesirable delay.time while determining an operation mode of the memory device for redundancy.

According to a first aspect of the present invention there is provided a semiconductor memory device with redundancy means for replacing a defective memory cell by a spare memory cell, comprising:

a first transfer path means for transferring a signal adapted to complementary metal-oxide-semiconductor(CMOS) voltage level, a second transfer path means for transferring said signal through delay means; and path selection means, connectable to said first and second transfer path means, for selecting either one of said first and said second transfer path means in response to a mode detect signal generated by turning on/off a fuse.

Preferably, said path selection means comprises:

a first transmission gate having a channel connected in between said first transfer path and a redundant enable circuit or a boost generator, and a control gate thereof receiving said mode detect signal; and a second transmission gate having a channel connected in between said second transfer path means and said redundant enable circuit or said boost generator, and a control gate thereof receiving said mode detect signal.

Preferably, said first transfer path means is selected when said fuse is connected to a power source terminal, while said second transfer path means is selected when said fuse is cut off from said power source terminal.

Preferably, said mode detect signal has a first or second phase respectively according to the turning on/off of said fuse, said second phase being opposite to said first phase.

According to a second aspect of the present invention there is provided a semiconductor memory device with redundancy means for replacing a defective memory cell by a spare cell, comprising:

means for generating a mode detect signal having two different phases in dependence upon turning on/off of a fuse; a first transfer path means for transferring a signal adapted to complementary metal-oxide-semiconductor(CMOS) voltage level; a second transfer path means for transferring said signal through delay means; path selection means for selecting one of said two paths in response to a mode detect signal generated by turning on/off said fuse, thus to connect a selected path means to an output terminal, said path selection means being connectable to- said first and second transfer path means; means for boosting a voltage of a word line selected by a row address to a given level, by receiving an output of said path selection means; and means for activating or non-activating a redundant decoding operation in response to the output of said path selection means.

Preferably, said first transfer path means is selected when said mode detect signal has a first phase.

Preferably, said activating/non-activating means generates a signal nonactivating said redundant decoding operation when said first transfer path means is selected.

Preferably, said second transfer path means is selected when said mode detect signal has a second phase.

Preferably, said activating/non-activating means generates a signal activating said redundant decoding operation when said second transfer path means is selected.

Preferably, said path selection means comprises:

a first complementary metal-oxide-semiconductor transmission gate having a channel connected in between said first transfer path means and said output terminal, and a control gate thereof receiving said mode detect signal; and a second complementary metal-oxide-semiconductor transmission gate having a channel connected in between said second transfer path means and said output terminal, and a control gate thereof receiving said mode detect signal.

According to a third aspect of the present invention there is provided a semiconductor memory device with redundancy means for replacing a defective memory cell by a spare cell, the device comprising:

means for receiving an address signal; means for detecting whether said address signal corresponds to a defective cell being addressed; and means for transferring said address signal selectively through a delay means or by-passing said delay means, in dependence upon a detection result of said detection means.

Such a device may further comprise any one or more of the features disclosed in the accompanying specification, claims, abstract and/or drawings, in any combination.

For a better understanding of the invention, and to show how the same may be carried into effect, reference will now be made, by way of example, to Figures 2 and 3 of the accompanying diagrammatic drawings, in which:

Figure 2 is a block diagram illustrating one example of a preferred embodiment of a memory device according to the present invention; and 1 Figure 3 is a detailed circuit diagram of a selected portion of Figure 2.

In Figure 2, there is illustrated a memory having redundant and normal row decoding. All of the parts except the part 200, indicated by dotted line, are the same as those of Figure I and have the same reference numerals as in Figure 1. The part 200 includes a second delay circuit 130, a mode detect circuit 110, and a path select circuit 120. The second delay circuit 130 receives an output of the first delay circuit 20 through a second transfer path 202. The path select circuit 120 receives an output of the first delay circuit 20 transmitted through a first transfer path 201 and an output of the second delay circuit 130 connectable to the second transfer path 202. The first transfer path 201 is used in directly transferring the output of the first delay circuit 20 to a respective input terminal of the path select circuit 120 without passing through the second delay circuit 130, while the second transfer path 202 is used in transferring the output of the first delay circuit 20 to a respective input terminal of the path select circuit 120, through the second delay circuit 130.

The path select circuit 120 selects either the first transfer path 201 or the second transfer path 202 according to a mode detect signal MD generated in the mode detect circuit 110, to transfer a selected signal by the path selection to the boost clock pulse generator 40 and redundant enable circuit 60. The mode detect circuit 110 is controlled by clock pulses OR generated in dependence upon the activation of a row address strobe signal RAS.

1 Referring to Figure 3 illustrating the gate circuit of the part 200, the mode detect circuit 110 comprises three series-connected inverters 111, 112, 113 and a NAND gate 114 in order to delay the clock pulses OR and adjust the pulse width thereof. The clock pulsesORare enabled (logic "high" state) by the activation of the row address strobe signal RAS, and delayed by one pulse due to the inverters and NAND gate, thus to appear as "high" state on the output terminal of the NAND gate 114. The output pulses of the NAND gate 114 are applied, through an inverter 115, to one control electrode of a transmission gate 117 comprising two N-channel MOS transistors.

A fuse 116 connected to power source terminal Vcc may be cut off by a laser beam. The channel of the transmission gate 117, between the fuse 116 and ground voltage Vss, is turned on during the period that the pulses OR are in logic "high" state. Also, an inverter 118 is disposed between the other electrode of the transmission gate 117 and the fuse 116. An output MD of an inverter 119 for inverting an output of the inverter 118 is a signal informing the path select circuit 120 that the present state of the device is repaired redundant mode or normal mode.

The path select circuit 120 comprises first and second CMOS transmission gates 121 and 123 controlled by the mode detect signal MD. The mode detect signal MD is applied to the n-type gate of the first transmission gate 121 and the p-type gate of the second transmission gate 123, while their other gates receive the mode detect signal MD inverted through an inverter 122. Thus the channel of the first transmission gate 121 is connected in between the first transfer path 201 and the input terminal of the boost clock pulse generator 40, while the channel of the second transmission gate 123 is connected in between the second transfer path 202 and the boost clock pulse generator 40. Thus, the path select circuit 120 selects either the first transfer path 201 or the second -transfer path 202 according to the logic state of the mode detect signal MD.

The first delay circuit 20 consists of a NOR gate for receiving buffered row address signals RAO, RAO. The second delay circuit 130 comprises a plurality of inverters 31, 32, 33 and 34 delaying an output of the NOR gate by a given time. The number of the inverters in the second delay circuit 30 may be determined as required.

Hereinafter will be described the inventive mode of operation, with reference to Figure 3.

If the memory device requires repairing, the fuse 116 is cut off from the power source terminal Vcc by a laser beam. Then, since one electrode of the N-channel transmission gate 117 receives a signal of " high " state when the clock pulse OR is in the "high" state, the voltage of the node 102 connected to the fuse 116 is dropped to "low" state, and the other electrode of the transmission gate 117 receives a signal of "high" state inverted through the inverter 118. Consequently, the mode detect signal MD become "low" state, representing the redundant operation mode. Hence, in the path select circuit 120, only the second transmission gate 123 is turned on, and the first transmission gate 121 is blocked, so that the row address signals RAO, RAO, through the first delay circuit 20, the second delay circuit 30 and the second transmission gate 123, are applied to the boost clock generator 40 and redundant enable circuit 60. Accordingly the memory repairing, i.e., the redundant operation mode, is performed.

Alternatively, if repaiiing is not required i.e., no defective cell exist in the normal cell array, the fuse 116 is not cut off from the power source terminal, and the voltage of the node 102 maintains "high" state. Hence, the mode detect signal MD becomes "high" state, so that the path select circuit selects the first transfer path 201 connecting the first delay circuit 20 to the first transmission gate 121, by the turn-on of the first transmission gate 121. Because the normal operation mode does not require the delay of the access time as in the redundant operation mode, the second delay circuit 30 need not be used.

In the illustrated embodiment, the RAS access time (TRAc: the time during which the RAS is activated and data DOUTcomes out) may be reduced by 2ns compared to a conventional circuit.

As stated above, the illustrated circuit selects either redundant or normal operation mode before decoding the row address, to prevent the address access time from being unnecessarily delayed in normal operation. Thus a reduction of the row address access time is realized.

While a preferred embodiment of the invention has been particularly shown and described, it will be easily understood by those skilled in the art that changes in form and details may be made without departing from the spirit and scope of the invention.

The reader's attention is directed to all papers and documents which are filed concurrently with or previous to this specification in connection with this application and which are open to public inspection with this specification, and the contents of all such papers and documents are incorporated herein by reference.

All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and/or all of the steps of any method or process so disclosed, may be combined in any combination, except combinations where at least some of such features and/or steps are mutually 25 exclusive.

Each feature disclosed in this specification (including any accompanying claims, abstract and drawings), may be replaced by alternative features serving the same, equivalent or similar purpose. unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic series of equivalent or similar features.

The invention is not restricted to the details of the foregoing embodiment(s). The invention extends to any novel one, or any novel combination, of the features disclosed in this specification (including any accompanying claims, abstract and drawings), or to any novel one, or any novel combination, of the steps of any method or process so disclosed.

Claims

1. A semiconductor memory device with redundancy means for replacing a defective memory cell by a spare memory cell, comprising:

a first transfer path means for transferring a signal adapted to complementary metal-oxide-semiconductor(CMOS) voltage level; a second transfer path means for transferring said signal through delay means; and path selection means, connectable to said first and second transfer path means, for selecting either one of said first and said second transfer path means in response to a mode detect signal generated by turning on/off a fuse.

2. A semiconductor memory device according to Claim 1, wherein said path selection means comprises:

3. A semiconductor memory device according to Claim 1 or 2, wherein said first transfer path means is selected when. said fuse is connected to a power source terminal, while said second transfer path means is selected when said fuse is cut off from said power source terminal.

4. A semiconductor memory device according to Claim 1,2 or 3, wherein said mode detect signal has a first or second phase respectively according to the turning on/off of said fuse, said second phase being opposite to said first phase.

5. A semiconductor memory device with redundancy means for replacing a defective memory cell by a spare cell, comprising:

means for generating a mode detect signal having two different phases in dependence upon turning on/off of a fuse; is a first transfer path means for transferring a signal adapted to complementary metal-oxide-semiconductor(CMOS) voltage level; a second transfer path means for transferring said signal through delay means; path selection means for selecting one of said two paths in response to a mode detect signal generated by turning on/off said fuse, thus to connect a selected path means to an output terminal, said path selection means being connectable to said first and second transfer path means; means for boosting a voltage of a word line selected by a row address to a given level, by receiving an output of said path selection means; and means for activating or non-activating in response to the output of said path selection means.

a redundant decoding operation

6. A semiconductor memory device according to Claim 5, wherein said first transfer path means is selected when said mode detect signal has a first phase.

7. A semiconductor memory device according to Claim 5 or 6, wherein said activating/non-activating means generates a signal non-activating said redundant decoding operation when said first transfer path means is selected.

8. A semiconductor memory device according to Claim 5, 6 or 7, wherein said second transfer path means is selected when said mode detect signal has a second phase.

9. A semiconductor memory device according to Claim 5, 6, 7 or 8, wherein said activating/non-activating means generates a signal activating said redundant decoding operation when said second transfer path means is selected.

10. A semiconductor memory device according to any of Claims 5 to 9, wherein said path selection means comprises:

a first complementary metal-oxide-semiconductor transmission gate having a channel connected in between said first transfer path means and said output terminal, and a control gate thereof receiving said mode detect signal; and tl a second complementary metal-oxide-semiconductor transmission gate having a channel connected in between said second transfer path means and said output terminal, and a control gate thereof receiving said mode detect signal.

11. A semiconductor memory device with redundancy means for replacing a defective memory cell by a spare cell, the device comprising:

12. A semiconductor memory device according to claim 11, further comprising any one or more of the features disclosed in the accompanying specification, claims, abstract and/or drawings, in any combination.

13. A semiconductor memory device substantially as hereinbefore described with reference to Figure 2 or Figures 2 and 3 of the accompanying drawings.