DE3508157C2 - - Google Patents

Abstract

A redundancy circuit for a semiconductor memory includes an ordinary decoder which selects a desired memory section in an ordinary memory, and a spare decoder which selects a desired memory section in a spare memory. The ordinary decoder includes a plurality of output inverters, each of which is connected to the corresponding ordinary memory section via an ordinary memory word line. A fuse is disposed in the ordinary memory word line so that the output inverter is disconnected from the ordinary memory section when some defects are included in the corresponding ordinary memory section. A pull-down transistor is connected to the ordinary memory word line in order to permanently maintain the ordinary memory word line at the logic low when the corresponding fuse is burned out. <IMAGE>

Description

The invention relates to a redundancy circuit for a Semiconductor memory according to the preamble of the patent saying 1.

Such a conventional redundancy circuit for one Contains semiconductor memory

• Normal memory word lines (W ₀ , W ₁ ,..., W _N ) which are connected to a normal memory,
• Spare memory word lines (SW ₀ , SW ₁ ) which are connected to a spare memory,
• a normal memory decoding circuit with NAND gates (NAND ₀ - NAND _N ), with one NAND gate on the output side being connected to a normal memory word line via inverters (CINV ₀ - CINV _N ),
• - A spare memory decoding circuit with decoding elements (SD ₀ , SD ₁ ), one of which is connected on the output side via inverter (CINVS ₀ , CINVS ₁ ) to a spare memory word line (SW ₀ , SW ₁ ), and
• - Input signal lines for supplying row address input signals (A ₀ ,..., A _i ) to the inputs of the NAND gates and to the decoding elements.

In Figs. 1 to 3, a conventional redundancy scarf is shown for processing a semiconductor memory. The reference characters A ₀ to A _i represent row address input signals. The conventional redundancy circuit has a normal memory decoding circuit with NAND gates NAND ₀ to NAND _N. It also has an equivalent memory decoding circuit with decoding elements SD ₀ and SD ₁ . In addition, the redundancy circuit has normal memory word lines W ₀ to W _N and spare memory word lines SW ₀ to SW ₁ .

In FIG. 2, the structure of the decoding section SD is shown _0th Signal lines Pk ₀ to Pk _n are programmed or controlled with the aid of fuses such that one of the signals / A _i (i = 0 to n) can be transmitted through them. A transmission gate coupling circuit G ₁ with P-channel and N-channel MOS transistors is in the so-called ON state before a change in the address input signals takes place. For this reason, the address input signals are slightly delayed by the MOS transistors.

Fig. 3 shows various signals that are generated within the redundancy circuit of Fig. 1 when the normal memory word line W ₁ shows a defect and the fuse of the decoding element SD ₁ is programmed so that the spare memory word line SW ₁ instead of Word line W ₁ takes over the operation. During the time period T ₀ , the normal memory word line W _{0 is} selected, while the remaining word lines remain unselected. At this time, the signal that is the output of the AND gate AND has the logic H level (high level). If the address signal changes to select the spare memory word line SW ₁ , the signals appear very quickly while the signal is considerably delayed because the gate capacity of the (N + 1) NAND gates NAND ₀ to NAND _{N is} connected to the line where the signal appears. Accordingly, the signals,,, and have the logic L level (low level) during the time period T ₁ . At this time, the clock signal Φ _w assumes the logical H level, the output signals of both inverters CINVS ₁ and CINV ₁ also have the logical H level, so that both word lines SW ₁ and W _{1 are} selected. If the normal memory word line W _{0 is} selected after the replacement memory word line SW ₁ (time period T ₃ ), the selection or control of the normal memory word line W _{0 is} delayed because the leading edge of the signal is also delayed. This means that the time periods T ₁ and T ₃ prevent exact operation (T ₁ ) and the access is slowed down (T ₃ ). The access time is thus increased or extended.

EP-O 1 10 636 A2 describes a redundancy circuit for a semiconductor memory which has a normal memory and a spare memory. However, it cannot be seen that the normal memory word lines can be controlled via NAND gates with inverters which are fed back. Although 2 fuses in the Nor malspeicher word lines are also shown in FIG. Exist, however, do not lie down ter an inverter. The transistor T 15 in FIG. 2 is not to be referred to as such. Namely, if the input signal at node 28 is at a high level, then a high drive voltage is also supplied to output node 30 , and vice versa. In this context, please refer to page 5, lines 30 to 34. In addition, it is not recognizable that between a fuse and the normal memory, the corresponding normal memory word line should be connected to a discharge transistor.

In the case of the redundancy circuit for a semiconductor memory known from EP-O 1 14 763 A2, it cannot be seen either that normal memory word lines should be controllable via NAND gates and inverters which are fed back. The fuses F ₁ to F _{n shown there} are at a completely different location. You are also in the area of spare memory word lines and not in the area of normal memory word lines. Through the respective at the right end of the lines 10 and 31 shown in FIGS. 1 and 2, the transistor corresponding line is not pulled to an L level or low level, for example to ground potential, but to the voltage V _pp . In addition, it can not be seen that all Gatean connections of all bleeder transistors should be connected to a common voltage source. Rather, the gate connections are connected to the normal memory or spare memory word lines themselves.

The invention has for its object the ge called redundancy circuit so that in case of defective ter normal memory word line and control of an ent speaking spare memory word line the control of Normal memory word line is reliably avoided, and that at the same time with a subsequent control egg ner another normal memory word line no drive ver hesitation occurs.

This object is achieved according to the invention in that

• - between each output of one connected to a NAND gate inverter (CINV _0, CINV _1, CINV _N...) And a normal memory word line (W _0, W (NAND _0, NAND _1, NAND _{N...) 1} ,..., W _N ) there is a fuse (F ₀ , F ₁ ,..., F _N ) which is blown through in the event of a defective normal memory word line,
• - With each normal memory word line (W ₀ , W ₁ ,..., W _N ) in the area between the fuse and the normal memory, a connection of a respective drain transistor (Q ₀ , Q ₁ ,..., Q _N ) is connected, the other terminal of which is at a low logic level (L) , and
• - All gate electrodes of the discharge transistors (Q ₀ , Q ₁ ,..., Q _N ) are connected to a common voltage source (Vcc) .

All inverters can advantageously be controlled by a clock signal ( Φ _w ).

In addition to the state of the art, the drawing represents an out example of management according to the invention. It shows

Fig. 1 is a circuit diagram of a conventional danzschaltung Redun,

Fig. 2 is a circuit diagram of a decoder circuit inner half of the redundancy circuit of Fig. 1,

Fig. 3 shows the profile of various signals within the redundancy circuit of Fig. 1, and

Fig. 4 is a circuit diagram of a redundancy circuit according to the invention.

A redundancy circuit according to the invention is shown in FIG. 4. The same elements as in FIGS. 1 and 2 are provided with the same reference numerals.

With each normal memory word line W ₀ to W _n , a drain transistor (pull-down transistor) Q ₀ to Q _{N is} connected. The gate electrodes of the discharge transistors Q ₀ to Q _N are connected to a common voltage source V _cc . The normal memory word lines W ₀ to W _N are also connected to assigned inverters CINV ₀ to CINV _N via fuses F ₀ to F _N. If a certain fuse that is connected to a defective word line has blown, the defective word line is separated from the output of the corresponding inverter.

The on-resistance of the corresponding leakage transistor Q ₀ to Q _N is chosen so that it assumes a relatively high value, so that the associated word line is kept at the logical H level when the output signal of the associated inverter assumes the logical H level and the associated fuse is in the normal state (uninterrupted state). In contrast, the word line is pulled to the logic L level with the aid of the leakage transistor when the associated fuse is blown or interrupted. In the exemplary embodiment according to the invention, the AND gate AND is not present in FIG. 1. In addition, the output terminals SW _{0 '} and SW _{1' of} the decoding elements SD ₀ and SD _{1 are} not connected to the NAND gates NAND ₀ to NAND _N.

If a defect occurs in the memory area which is associated with the normal memory word line W ₁ , the fuse F ₁ burns out, for example under the action of a laser-powered cutting device, so that the normal memory word line W _{1 is} separated from the inverter CINV ₁ . The decoding element SD ₁ is programmed per or is controlled so that the replacement memory word line SW ₁ then takes over the operation instead of the normal memory word line W ₁ . The normal memory word line W ₁ is then kept permanently at the logic L level (low level) with the aid of the drain transistor Q ₁ . If the decoding element SD ₁ generates an output signal, the inverter CINVS ₁ also supplies an output signal with a logic H level, so that the word line SW _{1 is} selected for the spare memory.

The redundancy circuit according to the invention is not controlled with the aid of the signal already mentioned in FIG. 1. Therefore, the signals have and behave until substantially the same response or the same response speed compared to the address signals. This means that the delay times T ₁ and T ₃ , which are shown in Fig. 3, are minimized. Since the fuses F ₀ to F _{N have} only a low electrical resistance, the control or selection signals on the normal memory word lines W ₀ to W _{N are} only slightly delayed.

Of course, the invention can also be used in the context of a non-synchronized circuit in which no clock signal Φ _{w is} generated.

Claims (3)

1. Redundancy circuit for a semiconductor memory, with

• a) normal memory word lines (W ₀ , W ₁ ,..., W _N ) which are connected to a normal memory,
• b) spare memory word lines (SW ₀ , SW ₁ ) which are connected to a spare memory,
• c) a normal memory decoding circuit with NAND gates (NAND ₀ - NAND _N ), each NAND gate being connected on the output side to a normal memory word line via inverters (CINV ₀ - CINV _N ),
• d) a spare memory decoding circuit with decoding elements (SD ₀ , SD ₁ ), one of which is connected on the output side via inverter (CINVS ₀ , CINVS ₁ ) to a spare memory word line (SW ₀ , SW ₁ ) and
• e) input lines for supplying row address input signals (A ₀ ,..., A _i ) to the inputs of the NAND-To re and to the decoding elements,

characterized in that

• f) between each output of one connected to a NAND gate. (NAND _0, NAND _1,.., NAND _N) inverter (CINV _0, CINV _1,..., CINV _N) and a normal memory word line (W _0, W ₁ , ... , W _N ) there is a fuse (F ₀ , F ₁ ,..., F _N ) which is blown in the event of a defective normal memory word line,
• g) with each normal memory word line (W ₀ , W ₁ ,..., W _N ) in the area between the fuse and the normal memory, a connection of a respective drain transistor (Q ₀ , Q ₁ ,..., Q _N ) is connected , the other terminal of which is at a low logic level (L) , and
• h) all gate electrodes of the discharge transistors (Q ₀ , Q ₁ ,..., Q _N ) lie on a common voltage source (Vcc) .

2. Redundancy circuit according to claim 1, characterized in that all inverters are controllable by a clock signal ( Φ _w ).