GB2156553A

GB2156553A - Semiconductor memory redundancy circuit

Info

Publication number: GB2156553A
Application number: GB8505764A
Authority: GB
Inventors: Munehiro Uratani
Original assignee: Sharp Corp
Current assignee: Sharp Corp
Priority date: 1984-03-08
Filing date: 1985-03-06
Publication date: 1985-10-09
Also published as: DE3508157A1; GB8505764D0; GB2156553B; DE3508157C2; JPS60191500A

Abstract

A redundancy circuit for a semiconductor memory includes an ordinary decoder which selects a desired memory section in an ordinary memory, and a spare decoder which selects a desired memory section in a spare memory. The ordinary decoder includes a plurality of output inverters, each of which is connected to the corresponding ordinary memory section via an ordinary memory word line. A fuse is disposed in the ordinary memory word line so that the output inverter is disconnected from the ordinary memory section when some defects are included in the corresponding ordinary memory section. A pull-down transistor is connected to the ordinary memory word line in order to permanently maintain the ordinary memory word line at the logic low when the corresponding fuse is burned out. <IMAGE>

Description

SPECIFICATION Semiconductor memory redundancy circuit BACKGROUND OF THE INVENTION FIELD OF THE INVENTION The present invention relates to a redundancy circuit employed in a semiconductor memory.

DESCRIPTION OF THE PRIOR ART A redundancy circuit is widely employed in a semiconductor memory so as to enhance the reliability. The redundancy circuit is effective when a portion of an ordinary memory has defects. However, in the convention semiconductor memory, the redundancy circuit produces a remarkable delay in an access time. The thus produced delay will preclude an accurate operation, and precludes a high speed operation.

OBJECTS AND SUMMARY OF THE INVEN TION OBJECTS OF THE INVENTION Accordingly, an object of the present invention is to provide a novel redundancy circuit, which minimizes the delay in an access time.

Another object of the present invention is to provide a redundancy circuit for a semiconductor memory, which ensures a high speed, accurate operation of the semiconductor memory.

Other objects and further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. It should be understood, however, that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.

SUMMARY OF THE INVENTION To achieve the above objects, pursuant to an embodiment of the present invention, a fuse and a pull-down transistor is connected to each selection line associated with an ordinary semiconductor memory. When a specific portion has defects, the specific portion is disconnected through the use of the fuse. By disconnecting the defective portion from the normal portion, the access time is not delayed, and an accurate operation is ensured.

BRIEF DESCRIPTION OF THE DRAWINGS The present invention will be better understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus are not limitative of the present invention and wherein: Figure 1 is a circuit diagram of an example of the conventional redundancy circuit; Figure 2 is a circuit diagram of a decoder circuit included in the redundancy circuit of Fig. 1; Figure 3 is a waveform chart showing various signals occurring within the redundancy circuit of Fig. 1; and Figure 4 is a circuit diagram of an embodiment of a redundancy circuit of the present invention.

DESCRIPTION OF THE PREFERRED EMBODI MENTS An example of the conventional redundancy circuit will be first described with reference to Figs. 1 through 3.

Ao through A represent the row address input signals. The conventional redundancy circuit includes an ordinary memory decoder circuit having NAND gates NAND, through NANDN, and a spare memory decoder circuit having decoder elements SD, and SD,. The redundancy circuit further includes ordinary memory word lines WO through WN, and spare memory word lines SWO and SW1.

Fig. 2 shows the structure of the decoder element SDo. Signal lines Pk, through Pk, are programmed by fuses so that either one of signals JA, (i = 0 through n) are passed therethrough. A transfer gate couple G, including P-ch and N-ch MOS transistors has been placed in the ON state before the address input signals change and, therefore, the address input signals are little delayed by these MOS transistors.

Fig. 3 shows various signals occurring within the redundancy circuit of Fig. 1 when the ordinary memory word line W, has defects, and the fuse of the decoder element SD, is programmed so that the spare memory word line SW, performs the operation for the word line W,. During a time period of Tot the ordinary memory word line WO is selected, and the remaining word lines are not selected.

At this moment, a signal DSEL, which is an output signal of an AND gate AND, bears the logic high. When the address signal changes to select the spare memory word line SW1, signals SW,', W01 and W,' respond rapidly, but the signal DSEL is considerably delayed because the gate capacitance of the (N + 1) NAND gates NAND, through NANDN is connected to the line of the signal DSEL. Accordingly, the signals SW,' and W,' bear the logic low during a time period T,. If a clock ~w is changed to the ligic high at this moment, the output signals of both inverters CINVS, and CINV, bear the logic high and, therefore, the both two word lines SW, and W, are selected.

Further, when the word line selection is changed from the spare memory word line SW, to the ordinary memory word line WO (time period T3), the selection of the ordinary memory word line WO is delayed because the leading edge of the signal DSEL is delayed.

That is, the time periods T1 and T3 preclude an accurate operation, or slow down the access time.

Fig. 4 shows an embodiment of a redundancy circuit of the present invention. Like elements corresponding to those of Figs. 1 and 2 are indicated by like numerals.

Pull-down transistors Qo through QN are connected to each of the ordinary memory word lines WO through WN. The gate electrodes of the pull-down transistors Qo through QN are commonly connected to a power source Vcc. Further, the ordinary memory word lines WO through WN are connected to the corresponding inverters CINV, through CINVN via fuses Fo through FN. When a specific fuse connected to the defective word line is burned out, the defective word line is disconnected from the output line of the corresponding inverter.

The on-resistance of the respective pulldown transistors QO through QN is selected at a considerably high value so that the word line is maintained at the logic high when the output signal of the corresponding inverter bears the logic high under the condition where the corresponding fuse is held in the normal state. And, the word line is placed in the logic low by means of the pull-down transistor when the corresponding fuse is burned out. In the embodiment of the present invention, the AND gate AND shown in Fig. 1 is removed and, therefore, output terminals SWO' and SW1' of the decoder elements SD, and SD1 are not connected to the NAND gates NAND, through NANDN.

When the memory region associated with the ordinary memory word line W1 has some defects, the fuse F1 is burned out through the use of, for example, a laser cutter, so as to disconnect the ordinary memory word line W1 from the inverter CI NV1. The decoder element SD1 is programmed so that the spare memory word line SW, performs the operation for the ordinary memory word line W1. The ordinary memory word line W1 is permanently held at the logic low by the pull-down transistor Q,.

When the decoder element SD1 develops an output signal, the inverter CINVS, develops an output signal of the logic high so that the word line SW1 of the spare memory is selected.

The embodiment of the present invention is not controlled by the signal DSEL. Therefore, the signals SWO', So11, and W01 through WN' show the substantially same respond speed against the address signals. That is, the delay periods T1 and T3 shown in Fig. 3 are minimized. Since the fuses Fo through Fn have a considerably low resistance value, the selection signals on the ordinary memory word lines WO through WN are little delayed.

The present invention is applicable to the non-synchronized system which does not in dude the clock ~w The invention being thus described, it will be obvious that the same may be varied in many ways without departure from the spirit and scope of the invention, which is limited only by the following claims.

Claims

1. A redundancy circuit for a semiconductor memory comprising: decoder means for developing memory section selection signals; and selection signal transfer means disposed between said decoder means and ordinary memory sections; said selection signal transfer means including: a plurality of word lines disposed between said decoder means and said ordinary memory sections; a plurality of fuses disposed in each of said word lines; and a plurality of pull-down transistors connected to each of said word lines.

2. The redundancy circuit of claim 1, wherein said decoder means includes a plurality of output inverters, each inverter being connected to one of said plurality of word lines.

3. The redundancy circuit of claim 2, wherein one of said output inverters is connected to one of said word lines via one of said fuses, and one of said pull-down transistors is connected to said one of said word lines at a position between said one of said fuses and one of said ordinary memory sections.

4. A semiconductor memory having a main memory section and a spare memory section, the main memory section having a plurality of main memory lines which may be selectively activated by memory address selection circuitry in the addressing of memory locations and the spare memory section having one or more spare memory lines which may be selectively activated in place of a said main memory line so as to enable substitution for a said ordinary memory line if a part of the memory addressed by activating the said main memory line is defective, the said main memory lines having fusible portions so that they may be disconnected when substituted for by the or a said spare memory line.

5. A semiconductor memory according to claim 4 in which the said main memory lines adopt a first logic value when activated and a second logic value when not activated by the memory address solution circuitry, the said main memory lines having default logic value means which cause a said main address line which has been disconnected at its said fusible portion to adopt the said second logic value.

6. A semiconductor memory according to claim 5 in which the said default logic value means comprises a transistor connected between each said main memory line and a predetermined voltage.

7. A semiconductor memory substantially as herein described with reference to Fig. 4 of the accompanying drawings.