GB2146861A - Digital frequency discriminator - Google Patents
Digital frequency discriminator Download PDFInfo
- Publication number
- GB2146861A GB2146861A GB08324665A GB8324665A GB2146861A GB 2146861 A GB2146861 A GB 2146861A GB 08324665 A GB08324665 A GB 08324665A GB 8324665 A GB8324665 A GB 8324665A GB 2146861 A GB2146861 A GB 2146861A
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- Prior art keywords
- pulses
- signal
- pulsed
- monostable
- pulse
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
- H03L7/187—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number using means for coarse tuning the voltage controlled oscillator of the loop
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R23/00—Arrangements for measuring frequencies; Arrangements for analysing frequency spectra
- G01R23/005—Circuits for comparing several input signals and for indicating the result of this comparison, e.g. equal, different, greater, smaller (comparing phase or frequency of 2 mutually independent oscillations in demodulators)
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/091—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
Abstract
A digital frequency discriminator operative to provide a discriminator output signal in dependence upon the frequency difference between a pulsed input signal and a pulsed reference signal comprising a voltage controlled monostable device (20) connected in a feedback loop so that the duration of its monostable pulses is controlled by a control voltage (39) to correspond with the pulse period of the pulsed reference (32) signal and which is triggered by each pulse of the pulsed input signal (19) to produce the monostable pulses and comparator means (22,28,29) responsive contemporaneously to pulses of the pulsed input signal and to the monostable pulses for producing the discriminator output signal. The digital state of the digital output signal, (0 or 1), is determined in dependence upon the pulse length of pulses of the pulsed input signal as compared with the pulse length of corresponding pulses of the pulsed reference signal. Known digital frequency discriminators have the disadvantage that they require several cycles of input signal in order to produce an output signal; the present digital frequency discriminator affords a digital frequency output signal which obviates the aforesaid disadvantage. <IMAGE>
Description
SPECIFICATION
Digital Frequency Discriminator
This invention relates to digital frequency discriminators and more especially but not exclusively it relates to digital frequency synthesisers embodying such discriminators.
Frequency discriminators operate to compare the frequency of two input signals and to provide an output signal in dependence upon the frequency difference therebetween. In digital frequency synthesisers a frequency discriminator is used to compare the frequency of a voltage controlled oscillator (V.C.O.) with the frequency of a reference signal and to provide an output signal in dependence upon which the frequency of the voltage controlled oscillator is controlled.
Known digital frequency discriminators have the disadvantage that they tend to be slow in operation and require several cycles of input signal in order to produce an output signal. It is an object of the present invention to provide a digital frequency discriminator which obviates the aforesaid disadvantage.
According to the present invention a digital frequency discriminator operative to provide a discriminator output signal in dependence upon the frequency difference between a pulsed input signal and a pulsed reference signal comprises a voltage controlled monostable device connected in a feedback loop so that the duration of its monostable pulses is controlled by a control voltage to correspond with the pulse period of the pulsed reference signal and which is triggered by each pulse of the pulsed input signal to produce the monostable pulses and comparator means responsive comtemporaneously to pulses of the pulsed input signal and to the monostable pulses for producing the discriminator output signal, the state of which output signal, (0 or 1), is determined in dependence upon the pulse length of pulses of the pulsed input signal as compared with the pulse length of corresponding pulses of the pulsed reference signal.
The feed back control loop may be operatively associated with a reference oscillator, and a counter responsive to the leading edge of the monostable pulses to begin counting pulses from the reference oscillator so as to produce the pulsed reference signal at a frequency which is a submultiple of the reference oscillator frequency, and the said loop may comprise a signal sampler responsive to the trailing edge of the monostable pulses for sampling the state of the pulsed reference signal and for holding the sampled state, integrator means and gating means which is triggered synchronously with the trailing edge of the monostable pulses for applying the sampled state (0 or 1 ) of the pulsed reference signal to the integrator means, for a predetermined period, thereby to produce the control voltage in dependence upon which the pulse length of the monostable pulses is determined.
The comparator means may comprise a pulse sampler responsive to the trailing edge of the monostable pulses for sampling the state (0 or 1) of the pulsed input signal and for holding that sampled state, a further monostable device responsive to the trailing edge of the monostable pulses for producing gating pulses, an output gate responsive to each gating pulse for applying to an output line for the period of each gating pulse the sampled state (O or 1) held by the pulse sampler thereby to produce on the output line the discriminator output signal.
The gating means may comprise a control gate responsive to the gating pulses for applying the sampled state (0 or 1) of the pulsed reference signal to the integrator means thereby to produce the control voltage in dependence upon which the pulse length of the monostable pulses is determined.
According to one embodiment of the invention a digital frequency discriminator adapted to be responsive to a pulsed input signal and a pulsed reference signal and to produce a discriminator output signal in dependence upon the frequency difference between the pulsed input signal and the pulsed reference signal may comprise a voltage controlled monostable device arranged to produce a monostable pulse responsively to each pulse of the pulsed input signal, the monostable pulse having a pulse length derived in dependence upon the pulsed reference signal, a pulse sampler responsive to the trailing edge of the monostable pulses for sampling the state (0 or 1 ) of the pulsed input signal and for holding that sampled state, a further monostable device responsive to the trailing edge of the monostable pulses for producing gating pulses, an output gate responsive to each gating pulse for applying to an output line for the period of each gating pulse the sampled state 0 or 1 held by the pulse sampler thereby to produce on the output line the discriminator output signal, a reference oscillator, a counter responsive to the leading edge of the monostable pulses to begin counting pulses from the reference oscillator so as to produce the pulsed reference signal at a frequency which is a submultiple of the reference oscillator frequency, a signal sampler responsive to the trailing edge of the monostable pulses for sampling the state of the pulsed reference signal and for holding the sampled state, integrator means, a control gate responsive to the gating pulses for applying the sampled state (0 or 1 ) of the pulsed reference signal to the integrator means, thereby to produce a control voltage in dependence upon which the pulse length of the monostable pulses is determined.
The pulse sampler and the signal sampler may be
D-type flip-flops.
The integrator means may comprise a series resistor and a shunt capacitor.
A digital frequency discriminator according to the present invention may be embodied in a digital frequency synthesiser.
The digital frequency synthesiser may comprise a voltage controlled oscillator (VCO) providing an a.c.
output signal, the VCO frequency being controlled in dependence upon the discriminator output signal of the digital frequency discriminator in the presence of a frequency difference between the pulsed reference signal and a pulsed input signal derived from the VCO via a variable divider in accordance with the setting of which the frequency of the a.c.
output signal is determined, wherein the frequency discriminator is coupled consequent upon operation of switch analogue stores to the (VCO) so that the discriminator output signal updates the voltage stored in the selected sample and hold store, the stored voltage being used to control the frequency
of the (VCO), the switch being operated for selection
purposes in accordance with the setting of the variable divider as determined by a program stored
in a read only memory (ROM) so that for a given
setting of the variable divider, a predetermined
sample and hold analogue store is selected
contemporaneously with the setting of the variable
divider, the (ROM) being responsive to a clock signal
derived from the variable divider for changing
repeatedly in steps the setting of the variable divider
and thus the frequency of the a.c. output signal.
One embodiment of the invention will now be described by way of example with reference to the accompanying drawings in which:
Figure 1 isa somewhat schematic block circuit diagram of a synthesiser embodying a frequency discriminator,
Figure 2 is a circuit diagram of a part of the synthesisershown in Figure 1,
Figure 3 is a block circuit diagram of the frequency discriminator embodied in the synthesiser shown in
Figure 1, and
Figures 4 and 5 are wave form diagrams appertaining to operation of the frequency discriminator shown in Figure 3.
Referring nowto Figure 1,thesynthesiser comprises a voltage controlled oscillator (VCO) 1, which provides on a line 2 an a.c. output signal and which feeds a signal via a line 3, at the same frequency as the output signal, to a variable divider 4. The variable divider 4 feeds a frequency discriminator 5 with a pulsed input signal. The frequency discriminator 5 also receives a signal from a reference frequency source 6. The frequency discriminoator 5 compares the signal from the variable divider 4 with a pulsed reference signal derived from the reference frequency and produces on a line 7 a control signal, as will hereinafter be described, in dependence upon which control signal the frequency of the VCO 1 is set.The control signal on the line 7 in practice tends either toward a high logic level (1) or towards low logic level (0) the logic level provided being dependent upon whether the frequency from the variable divider 4 is higher than the pulsed reference signal derived from the reference source 6 or lowerthan the pulsed reference signal. The control signal on the line 7 is fed to a selected one of a plurality of sample and hold analogue stores 8. The sample and hold
analogue stores 8 are connected in parallel between
input logic gates 9 and output logic gates 10, the
arrangement being such that each sample and hold
analogue store 8 is connected between one pair of
gates 9 and 10 (not shown in detail) so that any one
of the sample and hold analogue stores 8 can be
selected by appropriate operation of the gates 9 and 10.The logic gates 9 and 10 are controlled in dependence upon signals from a read only memory 11 which provides control signals for the gates via lines 12 and 13. The read only memory 11 also controls the variable divider 4 via control lines 14 and in use of the synthesiser it is arranged that a predetermined sequence of division factors are selected corresponding to a predetermined sequence of a.c. output signal frequencies, which are provided an the line 2 in accordance with the contents of a programme stored in the read only memory 11. An address section of the read only memory (not shown in detail) is fed via a line 15 with clock pulses from a fixed divider 16 fed from the variable divider 4.Thus in operation of the synthesiser the ROM 11 is clocked at a subharmonic of the output frequency from the variable divider 4 corresponding to the clock pulse frequency on the line 15 in response to which the output frequency is changed. As the division factor of the variable divider 4 is changed in steps by the ROM 11 it is arranged that the ROM 11 contemporaneously controls the gates 9 and 10 so that an appropriate sample and hold analogue store is selected. The selected sample and hold analogue store holds a stored voltage level which is applied to control the
VCO 1 so as to produce the required frequency on the line 3.
In operation of the synthesiser, immediately after switch on, the sequence of frequencies to be selected in accordance with the stored programme in the ROM 11 will be continuously repeated until the voltage levels stored in the sample and hold analogue stores 8 are appropriate to corresponding settings of the frequency divider 4. Thereafter, when a particular frequency is selected, a corresponding sample and hold analogue store will also be selected which is already primed with an appropriate control voltage to be applied to the voltage controlled oscillator 1.In practice the voltage stored in the sample and hold analogue stores 8 may deviate slightly from an ideal value but it will be appreciated that the feedback loop which includes the VCO, the variable divider 4 and the frequency comparator 5 will operate so as to provide appropriate logic level signals on the control line 7 so as to correct the stored voltage appropriately.
In the present case if a 100 mHz output signal is required on the line 2 and the pulsed reference signal is arranged to be 10 kHz as would be appropriate for a 10 kHz channel spacing, the variable divider is in this case set to divider by a divisor of 10,000. In orderto produce 100 hops or frequency changes per second, the output frequency from the variable divider 4 is arranged to be divided by 100 by the fixed divider 16 so as to provide clock pulses at 100 Hz.
The various parts of the synthesiser such as the read only memory, the variable divider 4, the VCO, the reference frequency source and the logic gates are well known to those skilled in the art and will not be described in great detail herein. The sample and hold analogue stores may comprise any suitable sample and hold analogue storage device and for example may simply comprise a series resistor 17 and a shunt capacitor 18, which as shown in Figure 2, is connected to an appropriate one of the gates 10 on the VCO side of the resistor 17.
The frequency discriminator 5 however is central to the present invention and will now be described in detail with reference to Figure 3. The frequency discriminator 5 which in Figure 3 is shown enclosed within a broken line, comprises a voltage controlled monostable device 20 which is fed on a line 19 from the divider 4 with the pulsed input signal. The pulsed input signal is also fed via a line 21 to a
D-type flip-flop 22 which serves as a pulse sampler.
The leading edge of each input pulse applied via line 19 to the voltage controlled monostable device 20 initiates the generation by the voltage controlled monostable device of a monostable pulse on output lines 23 and 24. The monostable pulses on the lines 23 and 24 are similar but mutually in antiphase whereby the leading edge of the monostable pulse on the line 24 is a rising edge and the trailing edge of the monostable pulse on the line 23 is a rising edge.
The monostable pulse on the line 23 is fed via a line 25 to a clock terminal 26 of the D-type flip-flop 22.
The D-type flip-flop 22 operates to sample the signal on the line 21 when a rising edge is applied to its clock terminal 26, the sampled signal being transferred to a line 27.
Referring now to Figure 4 and Figure 5 wave forms a, bc, and d, of each Figure illustrate operation of the voltage controlled monostable device 20 in association with the D-type flip-flop 22.
Thus, if an input pulse is applied to the voltage controlled monostable device 20 on the line 19 which corresponds to the wave-form a, monostable output pulses will be produced on the lines 24 and 23 corresponding to the wave-forms b and c respectively of Figure 4 and Figure 5. In Figure 4 the input pulse shown as wave-form a is shorter than the monostable pulses of wave-forms band c, whereas in Figure 5, the input pulse shown as wave4orm a, is longer than the monostable pulses shown in wave-forms b, and c. Thus if the waveforms as shown in Figure 4 obtain, when the D-type flip-flop 22 operates consequent upon receiving the rising trailing edge of the wave-form c, on line 25, the input pulse as shown in wave-form a, will have a low logic level and this will be reflected at the output line 27 as shown by wave-form d, of Figure 4.If however, the wave-forms a, b, and c, as shown in
Figure 5 obtain, then when the D-type flip-flop 22 samples the input wave-form a, consequent upon receiving the rising trailing edge of the wave-form c, on line 25, a high logic level will obtain and this high logic level will be reflected at the output line 27 as shown by wave-form d, of Figure 5.
In order to transfer the signal on line 27 to the output line 7 an output gate 28 is provided which is responsive to the signal from a monostable device 29 which is operated by the rising trailing edge of the monostable signal on the line 25. The monostable pulse produced by the monostable device 29 is shown as wave-form e, in Figures 4 and 5 and as can be seen from Figures 4 and 5, the monostable pulse of wave-form e, is applied to the gate 28 to produce on the line 7 a discriminator output signal f, from the gate 28. The amplitude of the discriminator output signal on the line 7 rises and falls in accordance with the sampled logic level on the line 27 as an integrator, represented by the resistor 17 and the capacitor 18 which are embodied in the filters 8 as shown in Figure 1 is charged or discharged.
It will be appreciated that it is necessary to control the pulse length of the monostable pulse produced by the voltage controlled monostable device 20 precisely and the manner in which the pulse length is controlled will now be described.
The leading edge of the monostable pulse on the line 24 is fed to a counter 30 so that the counter begins counting pulses fed thereto on a line 31 from the reference oscillator 6. The counter 30 is arranged to produce an output pulse on line 32 when a predetermined count state is reached which in the present case corresponds to a frequency of 10 kHz and thus the frequency of the pulses on the line 32 will be a sub-multiple of the reference frequency oscillator 6. The pulsed reference signal on the line 32 is fed to a D-type flip-flop 33 which operates in a similar manner to the D-type flip-flop 22 as a sampler. Thus the logic level of the pulsed reference signal on the line 32 which obtains when the rising trailing edge of the monostable pulse produced by the voltage controlled monostable device 20 occurs on the line 25, will be transferred to an output line 34 of the flip-flop 33.The sampled logic level on the line 34 is fed to a control gate 35 which is responsive to the pulse produced by the monostable device 29 and applied to the control gate 35 via a line 36. An output signal from the control gate 35 is fed via a line 37 to an integrator 38. The integrator 38 serves to integrate the logic level on the line 37 as sampled by the control gate 35 and the integrated output from the integrator 38 serves as a control voltage which is fed on a line 39 to the voltage controlled monostable device 20 to control its pulse period precisely in accordance with the pulsed reference signal applied from the counter 30 on the line 32.
Thus it will be understood that the voltage controlled monostable device 20 produces a monostable output pulse the length of which is precisely controlled. The length of input pulses on the line 19 are thus in effect compared with the length of the precision monostable pulse and a discriminator output signal is produced in dependence upon the result of the comparison.
Thus it will be appreciated that the output gate 28, the monostable device 29 and the D-type flip-flop 22 may be considered to operate as a comparator which serves to compare the length of pulses of the pulsed input signal on the line 19 with pulses of the pulsed reference signal on the line 32.
It will also be appreciated that the D-type flip-flop 33, the control gate 35 and the integrator 38 operate in a feed back loop configuration to produce the control voltage on the line 39.
The discriminator just before described has the advantage that it operates within one cycle of pulsed input signal to appropriately modify the control signal.
Various modifications may be made to the arrangement just before described without departing from the scope of the invention and for example various alternative kinds of comparator may be utilised and alternative feed back loop configurations are to be possible as will be appreciated by those skilled in the art.
Claims (10)
1. A digital frequency discriminator operative to provide a discriminator output signal in dependence upon the frequency difference between a pulsed input signal and a pulsed reference signal comprising a voltage controlled monostable device connected in a feedback loop so that the duration of its monostable pulses is controlled by a control voltage to correspond with the pulse period of the pulsed reference signal and which is triggered by each pulse of the pulsed input signal to produce the monostable pulses and comparator means responsive contemporaneously to pulses of the pulsed input signal and to the monostable pulses for producing the discriminator output signal, the digital state of which digital output signal, (0 or 1), is determined in dependence upon the pulse length of pulses of the pulsed input signal as compared with the pulse length of corresponding pulses of the pulsed reference signal.
2. A digital frequency discriminator as claimed in
Claim 1 wherein the feedback control loop is operatively associated with a reference oscillator, and a counter responsive to the leading edge of the monostable pulses to begin counting pulses from the reference oscillator so as to produce the pulsed reference signal at a frequency which is a submultiple of the reference oscillator frequency, the said loop comprising a signal sampler responsive to the trailing edge of the monostable pulses for sampling the state of the pulsed reference signal and for holding the sampled state, integrator means, gating means which is triggered synchronously with the trailing edge of the monostable pulses for applying the sampled state (0 or 1) of the pulsed reference signal to the integrator means, for a predetermined period, thereby to produce the control voltage in dependence upon which the pulse length of the monostable pulses is determined.
3. A digital frequency discriminator as claimed in
Claim 2 wherein the comparator means comprises a pulse sampler responsive to the trailing edge of the monostable pulses for sampling the state (0 or 1) of the pulsed input signal and for holding that sampled state, a further monostable device responsive to the trailing edge of the monostable pulses for producing gating pulses, an output gate responsive to each gating pulse for applying to an output line forthe period of each gating pulse the digital state (0 or 1) sampled by the pulse sampler thereby to produce on the output line the discriminator output signal.
4. A digital frequency discriminator as claimed in
Claim 3 wherein the gating means comprises a control gate responsive to the gating pulses for applying the sampled state (0 or 1) of the pulsed reference signal to the integrator means thereby to produce the control voltage in dependence upon which the pulse length of the monostable pulses is determined.
5. A digital frequency discriminator adapted to be responsive to a pulsed input signal and a pulsed reference signal and to produce a discriminator output signal in dependence upon the frequency difference between the pulsed input signal and the pulsed reference signal comprising a voltage controlled monostable device arranged to produce a monostable pulse responsively to each pulse of the pulsed input signal, the monostable pulse having a pulse length derived in dependence upon the pulsed reference signal, a pulse sampler responsive to the trailing edge of the monostable pulses for sampling the state (0 or 1) of the pulsed input signal and for holding that sampled state, a further monostable device responsive to the trailing edge of the monostable pulses for producing gating pulses, an output gate responsive to each gating pulse for applying to an output line for the period of each gating pulse the sampled state 0 or 1 held by the pulse sampler thereby to produce on the output line the discriminator output signal, a reference oscillator, a counter responsive to the leading edge of the monostabie pulses to begin counting pulses from the reference oscillator so as to produce the
pulsed reference signal at a frequency which is a submultiple of the reference oscillator frequency, a
signal sampler responsive to the trailing edge of the
monostable pulses for sampling the state of the
pulsed reference signal and for holding the sampled
state, integrator means, a control gate responsive to the gating pulses for applying the sampled state (0
or 1) of the pulsed reference signal to the integrator
means, thereby to produce a control voltage in
dependence upon which the pulse length of the
monostable pulses is determined.
6. A digital frequency discriminator as claimed in
Claim 4 or Claim 5 wherein the pulse sampler and
the signal sampler are D-type flip-flops.
7. A digital frequency discriminator as claimed in
any of Claims 2 to 6 wherein the integrator means
comprises a series resistor and a shunt capacitor.
8. A digital frequency synthesiser comprising a
digital frequency discriminator as claimed in any
preceding claim.
9. A digital frequency synthesiser as claimed in
Claim 8 comprising a voltage controlled oscillator (VCO) providing an a.c. output signal, the VCO
frequency being controlled in dependence upon the
discriminator output signal of the digital frequency
discriminator in the presence of a frequency
difference between the pulsed reference signal and
a pulsed input signal derived from the VCO via a
variable divider in accordance with the setting of
which the frequency of the a.c. output signal is
determined, characterised in that the frequency
discriminator is coupled consequent upon operation
of switch means via a selected one of a plurality of
sample and hold analogue stores to the (VCO) so
that the discriminator output signal updates the
voltage stored in the selected sample and hold
store, the stored voltage being used to control the frequency of the (VCO), the switch being operated for selection purposes in accordance with the setting of the variable divider as determined by a program stored in a read only memory (ROM) so that for a given setting of the variable divider, a predetermined sample and hold analogue store is selected contemporaneously with the setting of the variable divider, the (ROM) being responsive to a clock signal derived from the variable divider for changing repeatedly in steps the setting of the variable divider and thus the frequency of the a.c.
output signal.
10. A digital frequency discriminator substantially as herein before described with reference to the accompanying drawing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB08324665A GB2146861B (en) | 1983-09-14 | 1983-09-14 | Digital frequency discriminator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB08324665A GB2146861B (en) | 1983-09-14 | 1983-09-14 | Digital frequency discriminator |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB8324665D0 GB8324665D0 (en) | 1983-10-19 |
| GB2146861A true GB2146861A (en) | 1985-04-24 |
| GB2146861B GB2146861B (en) | 1987-01-14 |
Family
ID=10548799
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB08324665A Expired GB2146861B (en) | 1983-09-14 | 1983-09-14 | Digital frequency discriminator |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB2146861B (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1063641A (en) * | 1964-06-01 | 1967-03-30 | Thorn Electronics Ltd | Improvements in frequency discriminators |
| GB1175096A (en) * | 1966-04-04 | 1969-12-23 | Paillard Sa | Improvements in or relating to an Electronic Speed Regulator for Electric Motors |
| GB1183452A (en) * | 1966-02-17 | 1970-03-04 | Dawe Instr Ltd | Improvements in or relating to Speed Indicating Apparatus |
| GB1188281A (en) * | 1966-01-21 | 1970-04-15 | Serck Controls Ltd | Improvements in or relating to Detection Means for Frequency Modulated Signals |
| GB1251374A (en) * | 1968-02-09 | 1971-10-27 |
-
1983
- 1983-09-14 GB GB08324665A patent/GB2146861B/en not_active Expired
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1063641A (en) * | 1964-06-01 | 1967-03-30 | Thorn Electronics Ltd | Improvements in frequency discriminators |
| GB1188281A (en) * | 1966-01-21 | 1970-04-15 | Serck Controls Ltd | Improvements in or relating to Detection Means for Frequency Modulated Signals |
| GB1183452A (en) * | 1966-02-17 | 1970-03-04 | Dawe Instr Ltd | Improvements in or relating to Speed Indicating Apparatus |
| GB1175096A (en) * | 1966-04-04 | 1969-12-23 | Paillard Sa | Improvements in or relating to an Electronic Speed Regulator for Electric Motors |
| GB1251374A (en) * | 1968-02-09 | 1971-10-27 |
Also Published As
| Publication number | Publication date |
|---|---|
| GB8324665D0 (en) | 1983-10-19 |
| GB2146861B (en) | 1987-01-14 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 732 | Registration of transactions, instruments or events in the register (sect. 32/1977) | ||
| PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 20020914 |