GB2124047A

GB2124047A - Frequency synthesiser

Info

Publication number: GB2124047A
Application number: GB08220140A
Authority: GB
Inventors: Christopher Keith Richardson
Original assignee: Plessey Co Ltd
Current assignee: Plessey Co Ltd
Priority date: 1982-07-10
Filing date: 1982-07-10
Publication date: 1984-02-08

Abstract

A digital frequency synthesiser comprising a voltage controlled oscillator (VCO) providing an output signal, the VCO frequency being controlled in dependence upon a control signal produced by a frequency comparator (5) in the presence of frequency difference between a reference frequency signal (6) and a signal derived from the VCO via a variable divider (4). The frequency comparator is coupled, upon operation of switch means (9, 10), via a selected one of a plurality of sample and hold analogue stores (8) to the VCO, so that the control signal updates a voltage stored in the selected sample and hold analogue store, the stored voltage being used to control the frequency of the VCO, the switch means being operated for selection purposes in accordance with the setting of the variable divider as determined by a programme stored in a read-only memory (ROM) means so that for a given setting, a predetermined sample and hold analogue store is selected contemporaneously with the setting of the variable divider, the ROM means being responsive to a clock signal derived from the variable divider for changing repeatedly in steps the setting of the variable divider and thus the frequency of the output signal. The output frequency of the synthesiser may thus be rapidly "hopped". <IMAGE>

Description

SPECIFICATION Synthesiser This invention relates to synthesisers.

More especially it relates to digital synthesisers of the kind comprising a voltage controlled oscillator (VCO) which provides an output signal, the frequency of which is controlled in dependence upon a signal produced by a frequency or phase comparator in the presence of frequency or phase difference between a reference frequency signal and a signal derived from the VCO via a variable divider in accordance with the setting of which the frequency of the output signal is determined.

For some applications it is desirable to provide a digital synthesiser of the kind defined which can be rapidly switched from frequency to frequency. One such application is in frequency hopping radio equipment wherein it is required rapidly to hop from channel to channel. The speed at which a digital synthesiser can be switched is determined by the time constant of a loop which comprises the VCO, the variable divider and the frequency or phase comparator and the time constant is determined in dependence upon the reference frequency. The reference frequency also determines the minimum channel spacing and so with a predetermined channel spacing the reference frequency and thus the time constant is fixed and is not normally short enough with acceptable channel spacing to facilitate fast switching of the synthesiser.

It is an object of the present invention to provide a synthesiser which can be rapidly switched from frequency to frequency for frequency hopping purposes for example.

According to the present invention a digital frequency synthesiser comprises a voltage controlled oscillator (VCO) providing an output signal, the VCO frequency being controlled in dependence upon a control signal produced by a frequency comparator in the presence of frequency difference between a reference frequency signal and a signal derived from the VCO via a variable divider in accordance with the setting of which the frequency of the output signal is determined, characterised in that the frequency comparator is coupled consequent upon operation of switch means via a selected one of a plurality of sample and hold analogue stores to the VCO, so that the control signal updates a voltage stored in the selected sample and hold analogue store, the stored voltage being used to control the frequency of the VCO, the switch means being operated for selection purposes in accordance with the setting of the variable divider as determined by a programme stored in a read only memory (ROM) means so that for a given setting, a predetermined sample and hold analogue store is selected contemporaneously with the setting of the variable divider, the ROM means being responsive to a clock signal derived from the variable divider for changing repeatedly in steps the setting of the variable divider and thus the frequency of the output signal.

In operation of the digital synthesiser, when the setting of the variable divider is changed to provide a different required output frequency, a predetermined sample and hold analogue store is selected contemporaneously which presents immediately to the VCO a stored voltage which will correspond to, or nearly correspond to, the voltage required to produce the required output frequency. Thus the VCO will change immediately to the required frequency or nearly to the required frequency and there will therefore be little or no delay due to the loop setting time constant before the required frequency is produced.

Any voltage difference that there may be between the voltage stored in the sample and hold analogue store and the required voltage, will be small, (once the synthesiser has settled down after 'switch on') and since the voltage difference between the required voltage and the stored voltage is small it will rapidly be compensated for by loop operation.

The switch means may comprise logic gates connected one on each side of each sample and hold analogue store, the said stores being arranged in parallel whereby a predetermined one of the said stores can be selected by 'opening' the logic gates between which it is connected.

The sample and hold analogue stores may each comprise a series resistor connected between the logic gates with which it is operatively associated and a shunt storage capacitor connected to that end of the resistor which is coupled to the VCO.

The ROM means may comprise address logic which is fed from the varaible divider via a fixed divider with clock pulses whereby the output frequency is changed synchronously with the clock pulses at a sub-harmonic of the frequency fed to the phase comparator from the variable divider.

The frequency comparator may comprise a frequency sensitive detector which provides a control signal defined by one or other of two logic levels in dependence upon whether the frequency from the variable divider is higher than or lower than the reference frequency.

One embodiment of the invention will now be described solely by way of example with reference to the accompanying drawings in which: Figure 1 is a generally schematic block diagram of a synthesiser; and in which Figure 2 is a circuit diagram of a part of the synthesiser shown in Fig. 1.

Referring now to Fig. 1, the synthesiser comprises a voltage controlled oscillator (VCO) 1, which provides on a line 2 an output signal and which feeds a signal via a line 3, at the same frequency as the output signal, to a variable divider 4. The variable divider 4 feeds a frequency comparator 5. The frequency comparator 5 also receives a signal from a reference frequency source 6. The frequency comparator 5 compares the signal from the variable divider with the reference frequency and produces on a line 7 a control signal in dependence upon which the frequency of the VCO 1 is set.The control signal on the line 7 is in practice either a high logic level or low logic level (1 or 0) the logic level provided being dependent upon whether the frequency from the variable divider 4 is higher than the frequency of the reference source 6 or lower than the frequency of the reference source 6.

The control signal on the line 7 is fed to a selected one of a plurality of sample and hold analogue stores 8. The sample and hold analogue stores 8 are connected in parallel between input logic gates 9 and output logic gates 10, the arrangement being such that each sample and hold analogue store 8 is connected between one pair of gates 9 and 10 (not shown in detail) so that any one of the sample and hold analogue stores 8 can be selected by appropriate operation of the gates 9 and 10.The logic gates 9 and 10 are controlled in dependence upon signals from a read only memory 11 which provides control signals for the gates via lines 1 2 and 1 3. The read only memory 11 also controls the variable divider 4 via control lines 14 and in use of the synthesiser it is arranged that a predetermined sequence of division factors are selected corresponding to a predetermined sequence of output signal frequencies, which are provided on the line 2 in accordance with the contents of a programme stored in the read only memory 11. An address section of the read only memory (not shown in detail) is fed via a line 1 5 with clock pulses from a fixed divider 1 6 fed from the variable divider 4.Thus in operation of the synthesiser the ROM 11 is clocked at a sub-harmonic of the output frequency from the variable divider 4 corresponding to the clock pulse frequency on the line 1 5 in response to which the output frequency is changed. As the division factor of the variable divider 4 is changed in steps by the ROM 11 it is arranged that the ROM 11 contemporaneously controls the gates 9 and 10 so that an appropriate sample and hold analogue store is selected. The selected sample and hold analogue store holds a stored voltage level which is applied to control the VCO 1 so as to produce the required frequency on the line 3.

In operation of the synthesiser immediately after switch on the sequence of frequencies to be selected in accordance with the stored programme in the ROM 11 will be continuously repeated until the voltage levels stored in the sample and hold analogue stores 8 are appropriate to corresponding settings of the frequency divider 4. Thereafter, when a particular frequency is selected, a corresponding sample and hold analogue store will also be selected which is already primed with an appropriate control voltage to be applied to the voltage controlled oscillator 1.In practice the voltage stored in the sample and hold analogue stores 8 may deviate slightly from an ideal value but it will be appreciated that the feedback loop which includes the VCO, the variable divider 4 and the frequency comparator 5 will operate so as to provide appropriate logic level signals on the control line 7 so as to correct the stored voltage appropriately.

In the present case if a 100 mHz output signal is required on the line 2 and the reference frequency is arranged to be 10 kHz as would be appropriate for a 10 kHz channel spacing, the variable divider is in this case set to divide by a divisor of 10,000. In order to produce 100 hops or frequency changes per second, the output frequency from the variable divider 4 is arranged to be divided by 100 by the fixed divider 1 6 so as to provide clock pulses at 100 Hz.

The various parts of the synthesiser such as the read only memory, the variable divider 4, the VCO, the frequency comparator, the reference frequency source and the logic gates are well known to those skilled in the art and will not be described in great detail herein. The sample and hold analogue stores may comprise any suitable sample and hold analogue storage device and for example may simply comprise a series resistor 1 7 and a shunt capacitor 18, which as shown in Fig. 2, is connected to an appropriate one of the gates 10 on the VCO side of the resistor 1 7.

Claims

1. A digital frequency synthesiser comprising a voltage controlled oscillator (VCO) providing an output signal, the VCO frequency being controlled in dependence upon a control signal produced by a frequency comparator in the presence of frequency difference between a reference frequency signal and a signal derived from the VCO via a variable divider in accordance with the setting of which the frequency of the output signal is determined, characterised in that the frequency comparator is coupled consequent upon operation of switch means via a selected one of a plurality of sample and hold analogue stores to the VCO, so that the control signal updates a voltage stored in the selected sample and hold analogue store, the stored voltage being used to control the frequency of the VCO, the switch means being operated for selection purposes in accordance with the setting of the variable divider as determined by a programme stored in a read only mem ory (ROM) means so that for a given setting, a predetermined sample and hold analogue store is selected contemporaneously with the setting of the variable divider, the ROM means being responsive to a clock signal derived from the variable divider for changing repeatedly in steps the setting of the variable divider and thus the frequency of the output signal.

2. A digital frequency synthesiser as claimed in claim 1 wherein the switch means comprises logic gates connected one on each side of each sample and hold analogue store, the said stores being arranged in parallel whereby a predetermined one of the said stores can be selected by 'opening' the logic gates between which it is connected.

3. A digital frequency synthesiser as claimed in claim 2 wherein the sample and hold analogue stores each comprise a series resistor connected between the logic gates with which it is operatively associated and a shunt storage capacitor connected to that end of the resistor which is coupled to the VCO.

4. A digital frequency synthesiser as claimed in any preceding claim wherein the ROM means comprises address logic which is fed from the variable divider via a fixed divider with clock pulses whereby the output frequency is changed synchronously with the clock pulses at a sub-harmonic of the frequency fed to the phase comparator from the variable divider.

5. A digital frequency synthesiser as claimed in any preceding claim wherein the frequency comparator comprises a frequency sensitive detector which provides a control signal defined by one or other of two logic levels in dependence upon whether the frequency from the variable divider is higher than or lower than the reference frequency.

6. A digital frequency synthesiser substantially as here and before described with reference to the accompanying drawings.