GB2273833A - Digital phase locked loop with self tuning - Google Patents

Abstract

A phase locked loop comprises a phase detector 130 responsive to the divided output of a controlled oscillator 100, and reference signal, derived from a transducer reading a patterned disc, a programmable divider 110, a feedback and control arrangement 140 the controlled oscillator 100 being responsive to the output of a phase control pulse generator 90, characterised in that the feedback and control arrangement 140 includes at least two sets of stored values within a table; the values are calculated in response to the phase difference over at least one iteration of a self-calibration means; the values in table control, via the feedback and control arrangement the phase control pulse generator 90 and programmable divider 110 in order to reduce the phase difference between the phase capture signal and the reference signal, thereby increasing the performance of such a system in that all feedback errors with a fundamental period equal to one revolution are eradicated leaving a much smaller error signal comprising random control loop speed variations and noise, both electrical and mechanical, allowing the control loop to have a higher cut off frequency and hence better tracking of motor speed. The oscillator 100 may include a crystal oscillator, a programmable delay line and an up-down counter. The divider 110 may include an up-down counter coupled to at least one delay line. <IMAGE>

Description

DIGITAL PHASE LOCKED LOOP WITH SELF TUNING DESCRIPTION The present invention relates to a digital phase locked loop system, in particular to a phase locked loop system enabling the generation of a master clock signal which is phase locked to a reference signal.

In many electronic systems it is necessary to recover or generate a master clock signal which is phase locked to a reference signal at a much lower frequency. A common design approach is to use a phase locked loop and a pulse counter to multiply the frequency of the reference signal to generate a master clock signal. This can be very successful as the feedback signal in the phase locked loop can be filtered to reduce the effects of noise, in the reference signal, on the master clock stability.

More recently phase locked loop designs utilise digital technology.

The traditional voltage controlled oscillators have been replaced with phase controlled oscillators and programmable delay lines. The digital designs are simple and have less stringent design criteria as they are not as susceptible to noise or thermal effects as the analog equivalents.

The disadvantages of the digital implementation are that the lock-in range is smaller and feedback tuning is more complex.

In magnetic recording disk files, a read/write head, attached to an actuator, is positioned and maintained over a desired data track through the use of a servo control system. The servo information for positioning the head is obtained from a dedicated servo disk located among the stack of disks in the direct access storage device. The specific pattern of servo information located in the servo tracks on the servo disk sectors of the data disk can be of the conventional quadrature type, such as described in the IBM Technical Disclosure Bulletin 21, P805, July 1978.

In the production of the servo pattern for the direct access storage device it is necessary to generate a signal at the master data rate for the device which is phase locked to the rotation of the disks.

The servo pattern of a direct access storage device comprises positional information stored as magnetic patterns on one or more surfaces of the rotating magnetic medium. The servo pattern has to be placed accurately in two dimensions. One of these dimensions being the radius of the circular pattern being written. The radius is normally determined by the accurate positioning of the head which writes the servo pattern. The other dimension being the rotational position of the disk which translates to a timing accuracy of the electrical signals fed to the head writing the servo pattern. The servo pattern is written in concentric circles. Each circle of the servo pattern must line up to within a fine tolerance of the other circles. In order to achieve such accurate alignment it is essential that the electronic circuits which generate the servo pattern being written are synchronised to the rotation of the disk.

It is a well established practice within the art to use a separate read/write head on an unused portion of one of the disks within the direct access storage device to write and then read back a reference signal. This reference signal, which is of the order of one tenth of the frequency of the desired master clock signal, is conditioned by a phase locked loop to provide the stable master clock signal. The disadvantage of such a system is that the read/write heads are only ever utilised during the manufacture of the disk. The direct access storage device must be kept very clean and is usually sealed. To allow the insertion of an extra head, production operations where this is performed must be clean typically to class 100 or better. Clean room space is expensive and any procedure which minimises it is an advantage.

The phenomena which can introduce misalignments into the servo pattern are (1) motor wow (periodic variations in motor speed).

(2) motor flutter (random variations in motor speed).

(3) motor spindle alignment.

(4) pattern inaccuracies on the patterned disc (periodic switching errors).

(5) concentricity errors in attaching the patterned disk (low frequency switching errors).

(6) noise in an optical transducer reading the patterned disc (random switching errors).

EP-A-373131 discloses a disk sector boundary signal generating system for the production of a sector boundary signal which follows only the wow and flutter elements of a motor. The system is implemented using an optical pattern which is adhered to the rotor of the motor. The optical pattern is read by an optical detector. The output of the optical detector has error conditions comprising sensor error, pattern error and wow and flutter components of the motor. The system tracks the rotation of the disk notwithstanding the above errors. The sector boundary signal is used to write the servo pattern on the disk. Owing to the fact that the transducer is coupled to the exterior of the sealed disk enclosure, a clean room is extraneous. This is an advantage in some respects but the quality of signal derived from an optical pattern is generally worse than that of a signal read directly from the direct access storage device.

Further, the signal derived from the optical pattern is at a lower frequency than that read directly from the direct access storage device thereby requiring much greater multiplication.

There is a need for a system capable of tracking motor wow and flutter which eliminates the need for a permanent external patterned disc in order to do so.

According to the present invention there is provided a phase locked loop system comprising a phase controlled oscillator, a phase detector having an input to receive a periodic reference signal and another input to receive a variable phase signal from the phase controlled oscillator, the phase detector being connected to supply a phase difference to a feedback and control means arranged to vary the phase of the phase controlled oscillator in response to the phase difference signal characterised in that there is provided a programmable divider to divide to frequency of the variable phase signal from the phase controlled oscillator, by a variable value chosen from a first cyclical set of values stored by the feedback and control means in a table means, before application to the phase detector.

In order to increase the accuracy of the phase matching the phase pulse control generator means is also responsive to a value from a second list of values contained in the feedback and control means.

Therefore, in accordance with an aspect of the present invention there is provided a phase locked loop system further comprising a phase control pulse generator means responsive to a value chosen from a second cyclical set of values stored by feedback and control means within the table means.

The table of values is used to anticipate the phase difference between the phase capture signal and the periodic reference signal. The first cyclical set of values represent the coarse adjustments applied to the programmable divider means in order to effect large changes in the phase of the phase capture signal. The second cyclical set of values represent the fine adjustments applied to the phase control pulse generator means in order to further decrease the phase difference between the phase capture signal and the periodic reference signal. The phase capture signal is brought into phase with the periodic reference signal using the above sets of values. It must be noted that the values for each period of the reference signal can be different.

Accordingly, in a specific embodiment of the present invention there is provided a phase locked loop system wherein the table means comprises the first and second cyclical sets of values representing the anticipated phase difference between the variable phase signal and the periodic reference signal, said values being derived from a selfcalibration means.

It is essential for timing purposes that the frequency of the first signal can be either advanced or retarded in the event of a phase difference being detected between the phase capture signal and the periodic reference signal. It will be evident that this function may be performed utilising a variable frequency oscillator and a means for controlling the same.

Accordingly, in a particular embodiment of the present invention there is provided a phase locked loop system wherein the phase controlled oscillator means comprises a stable crystal oscillator, a programmable delay line and a binary up/down counter, said counter being responsive to the phase control pulse generator means and operable to vary the delay of said delay line in multiples of a predetermined duration.

The programmable divider counts the master clock pulses and generates the phase capture signal for each N master clock pulses detected. The value of N is determined by the state of a register. The contents of that register being under the control of the feedback and control means. The feedback and control means loads the register with a value chosen from the first cyclical set of values thereby effecting a large change in phase.

Therefore, in accordance with another embodiment of the present invention there is provided a phase locked loop system wherein the programmable divider comprises at least one programmable binary up/down counter coupled to at least one delay line, the programmable divider being responsive to a value selected from the first cyclical set of values within the table means.

It is well known within the art that a digital phase detector providing a linear output is more suitable for complex control systems such as the present invention than the analogue equivalent.

Consequently, in another specific embodiment of the present invention there is preferably provided a phase locked loop system wherein the phase detector means is a linear digital phase detector.

In operation, the phase locked loop system, when first initialised, selects an arbitrary index position from a patterned disc. The index position is utilised to determine the nth period of the reference signal.

Although a particular embodiment of the present invention may use an arbitrary index position, it will be apparent to one skilled in the art that the present invention is not limited to such an index. It can equally be implemented using a fixed index position.

Viewed from another aspect, the present invention provides a phase locked loop system wherein the periodic reference signal is derived from a transducer reading a patterned disc having either an arbitrarily selected or fixed index position.

The patterned disc which is adhered to the rotor of the motor provides the periodic reference signal which is indicative of the rotation of the motor. The patterned disc provides 792 reference signal periods per revolution. It will be apparent to one skilled in the art that notwithstanding the use of a disc having 792 periods, the present invention is not limited to such a number of periods.

In a particular embodiment of the present the invention there is provided a phase locked loop system wherein the periodic reference signal is derived from an optical transducer reading an etched metal disc having either an arbitrarily selected or fixed index position.

It will be obvious to one skilled in the art that the lock-in range of the phase locked loop system can be varied by varying the number of delay lines utilised.

Appropriately, a particular embodiment of the present invention provides a phase locked loop system wherein a plurality of delay lines are utilised to vary the lock-in range of the system.

The invention will now be described, by way of example, with reference to the accompanying drawings in which: Figure 1 illustrates a schematic servo pattern of a direct access storage disk according to the prior art.

Figure 2 illustrates a schematic diagram of a phase locked loop system according to the present invention.

Figure 3 illustrates schematically the relationship between the phase capture signal and the periodic reference signal according to the present invention.

Figure 4 illustrates schematically the operation of a phase locked loop according to the present invention.

Referring to Figure 1, there is shown a schematic servo pattern 10 including the radial 20 and rotational 30 positional variables which can affect the accuracy of such a pattern. It can be seen that the magnetisation along a track 40 alternates between two states of polarity.

The shaded areas 50, represent regions of the track 40 which are polarised in one direction and the unshaded areas 60 represent regions which are polarised in the opposite direction. It can be seen that while writing a servo pattern 10 to the disk, alignment errors 80 between the tracks 40, 70 can result as a consequence of, inter alia, anomalous motor operation.

In Figure 2 there is shown a phase locked loop system according to the present invention comprising a digital phase detector means 130 , a programmable divider means 110, a feedback and control means 140, a phase control pulse generator means 90, a phase controlled oscillator means 100 and a signal conditioning means 120. The output of the phase controlled oscillator means 100 is connected to the direct access storage device for the purpose of writing a servo pattern 10 as described above.

In operation, the phase control pulse generator means 90 receives an input of digital pulses corresponding to the phase control command 260. The phase control command 260 instructs the phase control pulse generator means 90 to effect a change of phase in the master clock signal 210. The operation is effectively that of a binary rate multiplier, which generates a variable number of pulses and a direction signal. Each pulse produced by the phase control pulse generator means 90 causes a 3 nanosecond shift in the output of the phase controlled oscillator means 100, the master clock signal 210. In the present invention the number of pulses generated is between 0 and 127. The timing of the pulses is controlled by the master clock 210 divided by 8, the phase control pulse generator clock 180.

The phase controlled oscillator means 100 uses a stable crystal at the master clock rate. The output of the phase controlled oscillator means 100 is coupled to the programmable divider means 110. The programmable divider means 110 is implemented utilising a programmable delay line which is fed from an up/down binary counter so a single count can add or subtract a short delay. Each pulse on the clock input to the counter causes the counter output value to increment or decrement. When the counter overflows (increments from 15 to 0) or underflows (decrements from 8 to 7) a predetermined value is loaded into the counter. This basic method of implementing such a programmable divider means 110 is well known within the art. However, to increase the variability of the programmable divider 110, as required by the invention, the up/down binary counter is coupled to a binary rate multiplier. The binary rate multiplier supplies a number of pulses per master clock cycle. This extends the variability of the output frequency by approximately two orders of magnitude, in multiples of 3 nanoseconds, and is more accurate than and not as susceptible to noise as the analog equivalent.

The programmable divider means 110 counts the master clock signal pulses 210 and generates a signal, the phase capture signal 220, for each N master clock signal pulses 210 detected. The value of N is determined by the state of a register. The contents of that register being under the control of the feedback and control means 140. Two signals 220,230 are generated by the programmable divider means 110. One is the phase capture signal 220 which is used by the phase detector 130 to compare the phase of the master clock signal 210 with that of the periodic reference signal 250. The second signal, cycle reference signal 230, toggles between 1 and 0 each time a phase capture signal 220 is generated. The cycle reference signal 230 is coupled to the feedback and control means 140 to indicate the start of a new division cycle. A division cycle corresponds to one cycle of the phase capture signal 220. This indicates to the feedback and control means 140 that a new divisor should be loaded into the programmable divisor means 110 from the table means 330.

The function of the conditioning means 120 is to ensure that the phase detector 130 receives a noise free signal. The conditioning is necessary because the optical detector output may suffer from voltage overshoot or undershoot and slow rise and fall times. The output from the conditioning block has the reduced undershoot or overshoot and fast rise and fall times necessary for the correct functioning of the present invention.

The digital phase detector 130 generates a signal representing the time difference between the periodic reference signal 250 and the phase capture signal 220. The periodic reference signal 250 propagates along a tapped delay line contained within the phase controlled oscillator means 100. The present invention has taps at 5 nanoseconds intervals and a latch which is 8 bits wide allowing a phase measurement over a range of 20 nanoseconds (30 if overflow and underflow are utilised) with 5 nanosecond resolution. Each latch simultaneously latches the state of its input when a pulse occurs on the phase capture signal 220. The latched value is converted by the feedback and control means 140 into a value representing the phase difference 320 between the periodic reference signal 250 and the phase capture signal 220.

The digital phase detector means 130 provides a linear digital signal over a narrow range which is more suitable for a complex control system such as the present invention than the simple leading/lagging signal utilised in the prior art.

In a specific embodiment of the present invention, the feedback and control means is implemented using a TMS320C25 digital signal processor chosen for its fast instruction cycle time of 100 nanoseconds. Such a fast instruction cycle time is necessary as each iteration of the control algorithm must be completed within 21 microseconds. However, it will be apparent to one skilled in the art that the present invention is not limited to the use of such a processor. The invention may equally be implemented using other processors having a sufficiently fast instruction cycle.

Figure 3 illustrates schematically the interrelationship between the periodic reference signal 250 derived from the patterned disc, after conditioning, the arbitrary index position 300, the phase capture signal 220 and the two cyclical sets of values 340,350 contained within the table 330.

In operation, the phase locked loop system undergoes the following initialisation sequence in order to establish the contents of the table 330: (1) initialising all values 340,350 within the table 330 to a predetermined value; (2) selecting a fixed or arbitrary index position 300 from the periodic reference signal 250; (3) knowing the number of expected periodic reference signal 250 periods between two consecutive index positions 300, keeping track of the number of periodic reference 250 signal periods since the most recent index position and hence the "nth reference signal period" 310; (4) using the "nth reference signal period" 310 to access, via an accession means, the "nth" value 360 in the table 330.

(5) adjusting the "nth" value 360 of the first 340 cyclical set of values within the table 330 such that the phase difference 240 between the phase capture signal 220 and the periodic reference signal 250 is reduced; (6) repeating steps (3) to (6) at least once for all reference signal 250 periods and all corresponding values in the first cyclical set of values 340; and (7) constructing a second cyclical set of values 350 in the table 330.

The second cyclical set of values 350 representing the average residual phase error between the phase capture signal 220 and the periodic reference signal 250, for each reference signal period.

(8) the determination of the first 340 and second 350 sets of values comprises three stages, each resulting in an increased degree of refinement: (a) a fixed division ratio stage aiming for large phase variations, resulting in large master clock signal 210 adjustments based in simple feedback culminating in bad tracking of the motor speed; (b) a variable division ratio stage aiming for smaller phase variations, resulting in small master clock signal 210 adjustment based on simple feedback culminating in poor tracking of motor speed;and (c) a variable division ratio stage aiming for yet smaller phase variations resulting in small master clock signal 210 adjustments based on optimised control loop culminating in good tracking of motor speed.

(9) Once the above is complete the disk can be used with improved tracking. The values 340,350 being used to anticipate and compensate for anomalous motor operation.

Appropriately, in accordance with a further aspect of the present invention there is provided a method of determining the two cyclical sets of values in a table, as used in a phase locked loop system described above, comprising the following steps: (1) initialising all values within the table to a predetermined value; (2) selecting a fixed or arbitrary index position from the second signal; (3) knowing the number of expected periodic reference signal periods between two consecutive index positions, keeping track of the number of periodic reference signal periods since the most recent index position and hence the "nth reference signal period"; (4) using the "nth reference signal period" to access, via an accession means, the "nth" value in the table.

(5) adjusting the "nth" value of the first cyclical set of values within the table such that the phase difference between the variable phase signal and periodic reference signal is reduced; (6) repeating steps (3) to (6) at least once for all reference signal periods and all corresponding values in the first cyclical set of values; and (7) constructing a second cyclical set of values in the table. The second cyclical set of values representing the average residual phase error between the variable phase signal and the periodic reference signal, for each reference signal period.

Referring to figure 4 there is shown a periodic reference signal 250 which, for the nth period of the periodic reference signal, leads the phase capture signal by 24 nanoseconds on the first iteration of the self-calibration means. This lead will be translated to a first cyclical value 360 presenting 21 nanoseconds and a second cyclical value 370 representing 3 nanoseconds for the nth period of the periodic reference signal 250. Consequently, the feedback and control means 140, when it receives the cycle reference signal 230 for the nth period of the periodic reference signal 250, knowing that the reference signal is periodic, is anticipating the periodic reference signal 250 leading the phase capture signal by 24 nanoseconds. The feedback and control means then instructs both the phase controlled pulse generator means and the programmable divider to advance the phase capture signal by 3 nanoseconds and 21 nanoseconds respectively thereby bringing the signals into phase as shown in figure 4.

In a typical direct access storage device, with a 60 revolutions per second motor utilising the self-calibration method according to a particular embodiment of the present invention, the duration of the selfcalibration stage may be approximately 10 to 20 seconds.

The phase locked loop system according to the present invention can be distinguished from a simple phase locked loop frequency multiplier on at least two counts. Firstly, the programmable divider means 110 is both programmable and variable and, secondly, the phase difference 240 is passed back to the feedback and control means 140 which not only controls the phase controlled oscillator means 100 but also the divisor of the programmable divider means 110.

The increase in performance of such a phase locked loop system according to the present invention is due to all feedback errors with a fundamental period equal to one revolution, i.e. motor wow, concentricity errors and patterned disc errors, being eradicated thereby leaving a much smaller error signal comprising motor flutter and noise, both electrical and mechanical. The eradication of the above errors allows the feedback and control means to have a higher cut off frequency and hence better tracking of motor speed.

The invention has been realised utilising digital technology. It will be apparent to one skilled in the art that the invention can equally be implemented using the analog equivalents instead of or in conjunction with the digital elements of the present invention.

The capture range of a phase locked loop system according the present invention is 0.2%. The capture range can be increased if the range of the digital phase detector means 130 is increased with additional delay lines and latches. It will be apparent to one skilled in the art that an alternative approach is to vary the initial divide ratio, in this way the capture and lock-in ranges can be increased indefinitely with the only limit being the possibility of locking onto a sub-multiple of the reference signal frequency.

It will be apparent to one skilled in the art that the present invention may be used in any system to eradicate or reduce the effect of periodic errors howsoever caused.

A specific embodiment of the present invention may have the following advantages over the prior art: (a) due to the digital implementation, the design is not as susceptible to noise, thermal instability or aging; (b) it is simpler to maintain as it has only one phase locked loop system, no analog adjustments and is self calibrating; or (c) it is more stable, especially when the reference signal has a repeated error (described as a pattern error or pattern attaching error in EP-A-373131).

Claims (10)

1. A phase locked loop system comprising a phase controlled oscillator (100), a phase detector (130) having an input to receive a periodic reference signal (250) and another input to receive a variable phase signal from the phase controlled oscillator (100), the phase detector being connected to supply a phase difference (240) to a feedback and control means (140) arranged to vary the phase of the phase controlled oscillator (100) in response to the phase difference signal (240) characterised in that there is provided a programmable divider (110) to divide to frequency of the variable phase signal from the phase controlled oscillator (100), by a variable value'chosen from a first cyclical set of values (340) stored by the feedback and control means (140) in a table means (330), before application to the phase detector (130).

2. A phase locked loop system as claimed in claim 1 further comprising a phase control pulse generator means (90) is responsive to a value chosen from a second cyclical set of values (350) stored by feedback and control means (140) within the table means (330).

3. A phase locked loop system as claimed in any preceding claim wherein the table means comprises the first (340) and second (350) cyclical sets of values representing the anticipated phase difference (240) between the variable phase signal (220) and the periodic reference (250) signal, said values (340,350) being derived from a self-calibration means.

4. A phase locked loop system as claimed in any preceding claim wherein the phase controlled oscillator (100) comprises a stable crystal oscillator, a programmable delay line and a binary up/down counter, said counter being responsive to the phase control pulse generator means (90) and operable to vary the delay of said delay line in multiples of a predetermined duration.

5. A phase locked loop system as claimed in any preceding claim wherein the programmable divider (110) comprises at least one programmable binary up/down counter coupled to at least one delay line, the programmable divider (110) being responsive to a value selected from the first (340) cyclical set of values within the table means (330).

6. A phase locked loop system as claimed in any preceding claim wherein the phase detector means (130) is a linear digital phase detector.

7. A phase locked loop system as claimed in any preceding claim wherein the periodic reference signal (250) is derived from a transducer reading a patterned disc having either an arbitrarily selected or fixed index position (300).

8. A phase locked loop system as claimed in any preceding claim wherein the periodic reference signal (250) means is derived from an optical transducer reading an etched metal disc having either an arbitrarily selected or fixed index position (300).

9. A method of determining the two cyclical sets of values in a table, as used in a phase locked loop system as claimed in any preceding claim, comprising the following steps: (1) initialising all values (340,350) within the table (330) to a predetermined value; (2) selecting a fixed or arbitrary index position (300) from the periodic reference signal (250); (3) knowing the number of expected periodic reference signal (250) periods between two consecutive index positions (300), keeping track of the number of periodic reference (250) signal periods since the most recent index position and hence the "nth reference signal period" (310); (4) using the "nth reference signal period" (310) to access, via an accession means, the "nth" value (360) in the table (330).

(5) adjusting the "nth" value (360) of the first (340) cyclical set of values within the table (330) such that the phase difference (240) between the variable phase signal (220) and periodic reference signal (250) is reduced; (6) repeating steps (3) to (6) at least once for all reference signal (250) periods and all corresponding values in the first cyclical set of values (340); and (7) constructing a second cyclical set of values (350) in the table (330). The second cyclical set of values (350) representing the.average residual phase error between the variable phase signal (220) and the periodic reference signal (250), for each reference signal period.

10. A data storage means wherein a phase locked loop system or method as claimed in any preceding claim is utilised for the purposes of producing a servo pattern (10).