GB2145243A - Optical lithographic processes - Google Patents

Optical lithographic processes Download PDF

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Publication number
GB2145243A
GB2145243A GB08416345A GB8416345A GB2145243A GB 2145243 A GB2145243 A GB 2145243A GB 08416345 A GB08416345 A GB 08416345A GB 8416345 A GB8416345 A GB 8416345A GB 2145243 A GB2145243 A GB 2145243A
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United Kingdom
Prior art keywords
layer
amorphous silicon
silicon
aluminum
deposited
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GB08416345A
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GB2145243B (en
GB8416345D0 (en
Inventor
Bruce Frederick Griffing
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General Electric Co
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General Electric Co
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Publication of GB2145243B publication Critical patent/GB2145243B/en
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    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/004Photosensitive materials
    • G03F7/09Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers
    • G03F7/091Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers characterised by antireflection means or light filtering or absorbing means, e.g. anti-halation, contrast enhancement
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274Photolithographic processes
    • H01L21/0276Photolithographic processes using an anti-reflective coating

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Architecture (AREA)
  • Structural Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

A film of amorphous silicon is deposited onto a layer of light reflective material prior to the deposition of a photo-sensitive material thereon to reduce reflections from the layer of light reflective material into the photosensitive material.

Description

SPECIFICATION Optical lithographic processes The present invention relates to optical lithographic processes, particularly photographic patterning of conductive surfaces as used, for example, in the fabrication of integrated circuits.
Metal layers are generally applied to an integrated circuit near the end of the fabrication process. The surface of the wafer on which the integrated circuit is formed is generally not planar at this point in the process and is often characterized by sharp steps.
When patterning of the metal layer is done by optical lithographic techniques, the high reflectivity of the metal layer and the presence of steps in the substrate result in non-uniform exposure of the photoresist and hence result in irregularity in the pattern produced therein. Thus, line widths of the pattern etched in the metal layer using the patterned photoresist would be non-uniform in the vicinity of the steps. Line widths of a pattern in the metal layer overlying planar portions of the substrate would also be non-uniform as reflections produce standing waves of radiation resulting in a non-uniform exposure of the photoresist.
In accordance with the present invention there is provided a method of preparing a layer of light reflective material for optical transference of a pattern thereto by light in the range of wavelengths from about 200 to about 700 nanometers from a mask imprinted with the pattern, the method comprising: depositing a film of amorphous silicon on the layer of light reflective material to reduce reflections from the said layer, and thereafter depositing on the film of amorphous silicon a layer of photosensitive material sensitive to light in the said range.
The invention thereby provides a method for obtaining substantially uniform exposure of a photo- sensitive layer overlying a highly reflective surface of an integrated circuit wafer. It achieves this by minimizing the adverse effect of the reflective surface in a simple manner compatible with existing processes for the fabrication of integrated circuits.
In the accompanying drawings, by way of example only: Figure 1 shows graphs of the relative reflection from layers of sputter deposited or amorphous silicon of various thicknesses deposited on an aluminum substrate as compared to the reflection from a bare aluminum surface as a function of wavelength.
Figure 2 is a cross-sectional view of a structure useful in describing an embodiment of the present invention.
Reference is now made to Figure 1 which shows graphs or reflection of light from an aluminum surface covered with various thicknesses of sputtered or amorphous silicon as compared to the reflection from a bare aluminum surface as a function of wavelength. Graph 11 was obtained by taking a wafer of silicon on which had been sputtered a layer of aluminum about 5000 Angstroms thick on which, in turn, had been sputtered a deposit of silicon approximately 200 Angstroms thick, and measuring reflections at each of successive wavelengths in the range from 200 to 750 nanometers obtained from surface of the sputtered deposited silicon. Reflections from a control wafer of silicon on which only aluminum had been deposited was also measured at the same wavelengths and compared with the reflections from the silicon covered surface of aluminum to obtain the various points on the graph.Similarly, graph 12 was obtained utilizing a wafer of silicon on which had been sputter deposited a layer of aluminum which, in turn, had sputter deposited on it a layer of silicon 400 Angstroms thick. The reflection from the surface of the layer of amorphous silicon 400 Angstroms thick was compared with the reflection from the surface of the wafer with just aluminum deposited thereon for each of successive wavelengths to obtain graph 12. Graph 13 was obtained by comparing the reflection from a wafer of silicon on which had been successively sputter deposited a layer of aluminum and a layer of silicon 600 Angstroms thick with the reflection from silicon wafer with just aluminum deposited thereon at each of successive wavelengths.From an examination of graphs 11, 12 and 13 representing successive layers of increased thickness of sputter deposited silicon on an aluminum reflective surface it is apparent that on average absorption increases and, hence, reflection decreases with increased thickness of the sputter deposited silicon. Also, the valleys of relative reflection occur at successively higher or greater wavelengths as a function of thickness of the sputtered deposited silicon. At 200 Angstroms of amorphous silicon a valley occurs at a wavelength of about 400 nanometers. From optical calculations using the optical parameters n and k of the index of refraction N, where n and karegiven by the relationship N = n + jk, it was determined that at a thickness of amorphous silicon of about 50 Angstroms a valley in the graph thereof would occur at a wavelength of about 250 nanometers.Relative reflection at this valley point would be about 50 percent.
Other graphs such as graphs 11, 12 and 13 may be obtained in the same manner as obtained above for thicknesses of sputtered silicon below 200 Angstroms and above 600 Angstroms and also for values of thickness between the values of thickness shown in the graphs, if desired. Also, the graphs could be extended to wavelengths below 200 and above 700 nanometers, if desired.
Sputter deposited silicon is amorphous in character in that it has essentially no crystallographic structure. Silicon in this form has an absorption length for radiation in the range from about 400 to about 450 nanometers which is about 1/10 the absorption length of crystalline silicon in this range.
Absorption length is defined as the depth of penetration of radiation incident on the surface of the amorphous silicon at which 63% of the radiation is absorbed. Thus, sputter deposited or amorphous silicon is highly advantageous for reducing reflections substantially from reflective surfaces in the aforementioned range.
The graphs shown in Figure 1 are for relative reflection from amorphous silicon layers in air.
These graphs are approximate for reflection from amorphous silicon layers into a layer of photoresist.
Similar graphs could be determined for the reflection from layers of amorphous silicon into a layer of photoresist. The character of the graphs is a function of the real component (n) of the index of refraction of the photoresist and the imaginary component (k) of the index of refraction of the pnotoresist as compared to these constants for air. For Shipley type AZ1470 photoresistthevalueforn is 1.7 and the value for k is 0.02 at the wavelength of 450 nanometers. These constants for air are: n = 1 and k=0. It was determined from these constants that corresponding graphs for photoresist on the amorphous silicon,forwhich n=4.13 and k=2.13 at 405 nanometers, would be shifted slightly downward and the valleys would be shifted slightly toward shorter wavelengths.
The graphs of Figure 1 can be readily utilized for selection of a particular thickness of amorphous silicon to be applied to an aluminum layer to minimize reflectons in the patterning thereof. For example, if an Optimetrix Type 8010 photolithographic projection apparatus is to be used for exposing the photoresist which is applied over a layer of amorphous silicon, the wavelength of exposure could be 436 nanometers. Accordingly, from an inspection of the graphs of Figure 1, it is apparent that graph 12 representing a thickness of amorphous silicon of 400 Angstroms would reduce reflections to 34% of the reflections from bare aluminum at 436 nanometers, and accordingly it would be the thickness of the amorphous silicon used on the surface of the aluminum layer.Other projection apparatus operate at different wavelengths and accordingly differentthicknesses of silicon would be used to provide minimum reflection.
A particular advantage in using amorphous silicon in addition to its desirable properties of reducing reflections from an aluminum surface to a overlying layer of photoresist is that it is compatible with the processing of the integrated circuit wafer. Carbon tetrachloride is used in the dry etching of aluminium.
This gas will also etch silicon. Also, other dry etchant gases which include chlorine radicals etch both aluminum and silicon. Accordingly, the silicon layer on the aluminum pattern may be etched in the same step that is used to etch the aluminum. Another advantage in the use of amorphous silicon is that a small percentage of silicon is usually included in the deposited aluminum to reduce spike formations of aluminum penetrating into a silicon substrate when aluminum is deposited thereon and the temperature is raised to value which causes silicon to dissolve into aluminum. Thus, a sputter deposited layer of amorphous silicon would provide two functions.
Further advantages of applicant's process is that the reflection reducing step may be easily and readily applied without any process complications. Silicon is sputtered in the same apparatus utilized for sputtering aluminum on the substrate.
While the graphs of Figure 1 show relative reflection for aluminum substrates, such graphs could readily be obtained for other conductive materials commonly utilized in the fabrication of integrated circuits such as molybdenum, tungsten, titanium and platinum. Such graphs could also be obtained for the silicides of the aforementioned metals. As silicon is readily etched in gases containing chlorine or fluorine which are commonly used for etching the various metal materials mentioned, the amorphous silicon and the underlying metal could be etched in one step of the process.
Reference is now made to Figure 2 which shows a cross section of a structure 20 useful in describing a specific application of the process of the present invention. A substrate 21 of P-type silicon semiconductor material about 20 mils thick having a resistivity of 10 ohm cm. and having a major surface 22 parallel to the (100) plane of the crystal is provided.
The substrate is cleaned and thereafter oxidized at 1000 C. in dry oxygen to grow a layer 23 of silicon dioxide 1000 Angstroms thick. A layer 24 of aluminum 5000 Angstroms thick is deposited on the layer 23 of silicon dioxide using conventional sputtering apparatus in which a target of aluminum is provided and inert gas ion bombardment of the target causes aluminum therefrom to be deposited on the layer of silicon dioxide. Thereafter, in the same apparatus used for sputtering aluminum on the substrate, a layer 25 of amorphous silicon is sputter deposited on the layer of aluminum to a thickness desired, for example, a thickness of 400 Angstroms.As mentioned above, a layer of amorphous silicon of this thickness reduces the reflection at 436 nanometers from the upper surface of the layer of amorphous silicon to approximately 34% of the reflection that would be obtained from the surface of the layer 24 of deposited aluminum. Thereafter, a layer 26 of a suitable photoresist is deposited on the layer 25 of amorphous silicon. As the apparatus to be used for the formation of an image in the photoresist is an Optimetrixtype 8010 projection apparatus operating on the wavelength of about 436 nanometers, a resist suitable forthis application would be Shipley type AZ1470.The substrate 20 with the various layers of materials thereon is then placed in the projection apparatus to form an image in the photoresist which is then developed to remove exposed portions thereof. The patterned photoresist is then utilized for etching a pattern in the layer of aluminum covered with amorphous silicon. A suitable etching process would be a dry etching process utilizing carbon tetrachloride which etches both amorphous silicon and aluminum. The developed photoresistwould then be removed. Thereafter, this structure 20 would be subjected to further processing depending upon the ultimate structure desired in the integrated circuit. The amorphous silicon could be retained on the layer to reduce "spiking" of aluminum into silicon as pointed out above. If desired, the amorphous silicon could be removed in an etch such as sodium hydroxide.
Results shown in Figure 1 are generally valid for any reflective surface on which a layer of amorphous silicon is deposited. This would include not only metallic surfaces, but surfaces of layers of materials having metal-like properties such as the silicides of the metals molybdenum,tungsten,titanium and platinum.
While amorphous silicon was deposited by sputtering, it could also be deposited by other means such as plasma assisted chemical vapor deposition.

Claims (9)

1. A method of preparing a layer of light reflective material for optical transference of a pattern thereto by light in the range of wavelengths from about 200 to about 700 nanometers from a mask imprinted with the pattern, the method comprising: depositing a film of amorphous silicon on the layer of light reflective material to reduce reflections from the said layer, and thereafter depositing on the film of amorphous silicon a layer of photosensitive material sensitive to light in the said range.
2. The method of Claim 1 in which the thickness of the film of amorphous silicon is in the range from about 50 to about 600 Angstroms.
3. The method of Claim 1 in which the light reflective material is a metal.
4. The method of Claim 3 in which the metal is aluminum.
5. The method of Claim 3 in which the metal is a metal selected from the class of molybdenum, tungsten, titanium and platinum.
6. The method of Claim 1 in which the light reflective material is a silicide of a metal selected from the class of molybdenum, tungsten, titanium and platinum.
7. The method of Claim Sin which the amorphous silicon is deposited by sputtering.
8. An integrated circuit wafer comprising a layer of light reflective material prepared by a method in accordance with any one of the preceding claims.
9. A method according to Claim 1 and substantially as herein described with reference to the accompanying drawings.
GB08416345A 1983-08-18 1984-06-27 Optical lithographic processes Expired GB2145243B (en)

Applications Claiming Priority (1)

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US52449783A 1983-08-18 1983-08-18

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Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2170649A (en) * 1985-01-18 1986-08-06 Intel Corp Sputtered silicon as an anti-reflective coating for metal layer lithography
US5153689A (en) * 1988-09-14 1992-10-06 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device having bit lines formed of an interconnecting layer of lower reflectance material than the material of the word lines
US5747388A (en) * 1992-09-18 1998-05-05 Siemens Aktiengesellschaft Antireflection layer and process for lithographically structuring a layer
US5926739A (en) * 1995-12-04 1999-07-20 Micron Technology, Inc. Semiconductor processing method of promoting photoresist adhesion to an outer substrate layer predominately comprising silicon nitride
US5985771A (en) * 1998-04-07 1999-11-16 Micron Technology, Inc. Semiconductor wafer assemblies comprising silicon nitride, methods of forming silicon nitride, and methods of reducing stress on semiconductive wafers
WO2001009683A1 (en) * 1999-08-02 2001-02-08 Infineon Technologies North America Corp. Reduction of resist poisoning
US6300253B1 (en) 1998-04-07 2001-10-09 Micron Technology, Inc. Semiconductor processing methods of forming photoresist over silicon nitride materials, and semiconductor wafer assemblies comprising photoresist over silicon nitride materials
US6316372B1 (en) 1998-04-07 2001-11-13 Micron Technology, Inc. Methods of forming a layer of silicon nitride in a semiconductor fabrication process
US6323139B1 (en) * 1995-12-04 2001-11-27 Micron Technology, Inc. Semiconductor processing methods of forming photoresist over silicon nitride materials
US6635530B2 (en) 1998-04-07 2003-10-21 Micron Technology, Inc. Methods of forming gated semiconductor assemblies

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0719842B2 (en) * 1985-05-23 1995-03-06 三菱電機株式会社 Redundant circuit of semiconductor device
JPH01241125A (en) * 1988-03-23 1989-09-26 Sony Corp Manufacture of semiconductor device
DE3930655A1 (en) * 1988-09-13 1990-03-22 Mitsubishi Electric Corp Semiconductor module with laminated coupling layer - has coupling section, extending over insulating film on semiconductor substrate main surface
ATE123345T1 (en) * 1989-01-23 1995-06-15 Siemens Ag METHOD FOR PRODUCING A SILICON NITRIDE LAYER AS USED AS AN ANTIREFLECTION LAYER IN PHOTOLITHOGRAPHY PROCESSES IN THE PRODUCTION OF HIGHLY INTEGRATED SEMICONDUCTOR CIRCUITS.
KR950011563B1 (en) * 1990-11-27 1995-10-06 가부시끼가이샤 도시바 Manufacturing method of semiconductor device
US5302240A (en) * 1991-01-22 1994-04-12 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor device
JPH0590224A (en) * 1991-01-22 1993-04-09 Toshiba Corp Manufacture of semiconductor device

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS561533A (en) * 1979-06-18 1981-01-09 Hitachi Ltd Method of photoetching
GB2061615A (en) * 1979-10-25 1981-05-13 Gen Electric Composite conductors for integrated circuits
JPS5680133A (en) * 1979-12-06 1981-07-01 Chiyou Lsi Gijutsu Kenkyu Kumiai Formation of pattern

Cited By (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2170649A (en) * 1985-01-18 1986-08-06 Intel Corp Sputtered silicon as an anti-reflective coating for metal layer lithography
US5153689A (en) * 1988-09-14 1992-10-06 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device having bit lines formed of an interconnecting layer of lower reflectance material than the material of the word lines
US5747388A (en) * 1992-09-18 1998-05-05 Siemens Aktiengesellschaft Antireflection layer and process for lithographically structuring a layer
US6323139B1 (en) * 1995-12-04 2001-11-27 Micron Technology, Inc. Semiconductor processing methods of forming photoresist over silicon nitride materials
US5926739A (en) * 1995-12-04 1999-07-20 Micron Technology, Inc. Semiconductor processing method of promoting photoresist adhesion to an outer substrate layer predominately comprising silicon nitride
US7057263B2 (en) 1995-12-04 2006-06-06 Micron Technology, Inc. Semiconductor wafer assemblies comprising photoresist over silicon nitride materials
US6693345B2 (en) 1995-12-04 2004-02-17 Micron Technology, Inc. Semiconductor wafer assemblies comprising photoresist over silicon nitride materials
US6297171B1 (en) 1995-12-04 2001-10-02 Micron Technology Inc. Semiconductor processing method of promoting photoresist adhesion to an outer substrate layer predominately comprising silicon nitride
US6451504B2 (en) 1995-12-04 2002-09-17 Micron Technology, Inc. Semiconductor processing method of promoting photoresist adhesion to an outer substrate layer predominately comprising silicon nitride
US6417559B1 (en) 1995-12-04 2002-07-09 Micron Technology, Inc. Semiconductor wafer assemblies comprising photoresist over silicon nitride materials
US6670288B1 (en) 1998-04-07 2003-12-30 Micron Technology, Inc. Methods of forming a layer of silicon nitride in a semiconductor fabrication process
US6635530B2 (en) 1998-04-07 2003-10-21 Micron Technology, Inc. Methods of forming gated semiconductor assemblies
US6326321B1 (en) 1998-04-07 2001-12-04 Micron Technology, Inc. Methods of forming a layer of silicon nitride in semiconductor fabrication processes
US6300671B1 (en) 1998-04-07 2001-10-09 Micron Technology, Inc. Semiconductor wafer assemblies comprising photoresist over silicon nitride materials
US6429151B1 (en) 1998-04-07 2002-08-06 Micron Technology, Inc. Semiconductor wafer assemblies comprising silicon nitride, methods of forming silicon nitride, and methods of reducing stress on semiconductive wafers
US6300253B1 (en) 1998-04-07 2001-10-09 Micron Technology, Inc. Semiconductor processing methods of forming photoresist over silicon nitride materials, and semiconductor wafer assemblies comprising photoresist over silicon nitride materials
US6461985B1 (en) 1998-04-07 2002-10-08 Micron Technology, Inc. Semiconductor wafer assemblies comprising silicon nitride, methods of forming silicon nitride, and methods of reducing stress on semiconductive wafers
US6316372B1 (en) 1998-04-07 2001-11-13 Micron Technology, Inc. Methods of forming a layer of silicon nitride in a semiconductor fabrication process
US7141850B2 (en) 1998-04-07 2006-11-28 Micron Technology, Inc. Gated semiconductor assemblies and methods of forming gated semiconductor assemblies
US6677661B1 (en) 1998-04-07 2004-01-13 Micron Technology, Inc. Semiconductive wafer assemblies
US6093956A (en) * 1998-04-07 2000-07-25 Micron Technology, Inc. Semiconductor wafer assemblies comprising silicon nitride, methods of forming silicon nitride, and methods of reducing stress on semiconductive wafers
US6756634B2 (en) 1998-04-07 2004-06-29 Micron Technology, Inc. Gated semiconductor assemblies
US5985771A (en) * 1998-04-07 1999-11-16 Micron Technology, Inc. Semiconductor wafer assemblies comprising silicon nitride, methods of forming silicon nitride, and methods of reducing stress on semiconductive wafers
WO2001009683A1 (en) * 1999-08-02 2001-02-08 Infineon Technologies North America Corp. Reduction of resist poisoning

Also Published As

Publication number Publication date
JPS6074529A (en) 1985-04-26
GB2145243B (en) 1987-08-26
DE3428565A1 (en) 1985-03-07
GB8416345D0 (en) 1984-08-01

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