GB2129631A - Power control apparatus - Google Patents

Power control apparatus Download PDF

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Publication number
GB2129631A
GB2129631A GB08323486A GB8323486A GB2129631A GB 2129631 A GB2129631 A GB 2129631A GB 08323486 A GB08323486 A GB 08323486A GB 8323486 A GB8323486 A GB 8323486A GB 2129631 A GB2129631 A GB 2129631A
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GB
United Kingdom
Prior art keywords
power
counting
load
output
coded
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB08323486A
Other versions
GB8323486D0 (en
Inventor
John Alder
Robert Sidney Ireland
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Plessey Co Ltd
Original Assignee
Plessey Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Plessey Co Ltd filed Critical Plessey Co Ltd
Priority to GB08323486A priority Critical patent/GB2129631A/en
Publication of GB8323486D0 publication Critical patent/GB8323486D0/en
Publication of GB2129631A publication Critical patent/GB2129631A/en
Withdrawn legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K17/00Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/72Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices having more than two PN junctions; having more than three electrodes; having more than one electrode connected to the same conductivity region
    • H03K17/725Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices having more than two PN junctions; having more than three electrodes; having more than one electrode connected to the same conductivity region for ac voltages or currents
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00Conversion of dc power input into dc power output
    • H02M3/02Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/157Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control

Abstract

A power control arrangement for controlling load power comprises counting means ICI arranged to be driven by clock pulses from the load ac power supply LPS when power is required to be supplied to the load so that said counting means provides a continuously changing coded count output and comparator means IC2 which compares the coded count output from the counting means IC1 with a pre-set or variable correspondingly coded output from power level control means PLC whereby according to whether the count output from the counting means IC1 is greater,equal or less than the coded output from the power level control means PLC the comparator output causes switching means in the load power circuit to be rendered conducting or non-conducting for a number of cycles at the power supply dependent upon the difference between the coded outputs. Thus, in each counting cycle, the switching means is inhibited until the counting means output reaches the preset output of the control means PLC, at which time the switching means is triggered to pass complete supply cycles until the end of the counting cycle. <IMAGE>

Description

SPECIFICATION Improvements relating to power control arrangements This invention relates to power control arrange mentsforcontrolling the ac power supplied to a load according to requirements.
According to the present invention a power control arrangementforcontrolling load power comprises counting means arranged to be driven through successive counting cycles by clock pulses preferably derived from the load ac power supply so that during each cou nting cycle the cou nting means provides a continuously changing coded count putput and comparator means which compares the coded count output from the counting means with a pre-set or variable correspondingly coded output from power level control means whereby according to whetherthe countoutputfrom the counting means is greater, equal or less than the instantaneous coded output from the power level control means the comparator output causes switching means in the load power circuit to be rendered effectively closed or open (eg conducting or non-conducting) for a number of cycles ofthe power supply during each counting cycle of the counting means dependent upon the difference between the coded outputs.
In carrying outthe invention the counting means maycomprisea binarycounterwith a count of 1 to 16 so that the clock pulses derived from the power supply will cause the counterto perform a full counting cycle for every 16 cycles of the supply. The correspondingly binary coded output from the power level control means may be pre-setto any binary code from 1 to 16 accordingtowhich in each period of ? 6 cycles of the power supply one or more cycles ofthe supply will be excluded by rendering the switching means conducting onlyfrom the point where the count position and coded output of the counting means correspond to the binary coded output of the power level control means up to the last count position ofthecounterbeforethe counter restores to zero.
It will readily be appreciated that the coded output from the power level control means may be variable in accordance with some parameter instead of being pre-setto a fixed value.
The comparator may comprise a four bit magnitude comparntorwhich compares the four bitword inputs from the binary counter and the power level control means.
By way of example one embodiment of the invention will now be described with reference to the accompanying drawing which shows a block schematic diagram of a power control circuit arrangement.
Referring to the drawing a four bit binary counter IC1 providing a binary count 1 to 16 and connected across a dc supply is arranged to be driven by clock pulses received from a load ac power supply circuit LPS over line L1. For a clock pulse received by the counter IC1 in respect of each cycle of the power supply the counter is advanced by one step so that for every 16 cycles of the power supply the counter completes a full counting cycle.
The binary coded output (iefour bit word) from the terminals QA QB QC and OD of the counter IC1 is applied to one set of input terminals A0, Al, A2 and A3 of a magnitude comparator IC2 also connected across the dc supply. Another set of comparator input terminals B0, B1, B2 and B3 receive a pre-set binary code input (iefour bit word) from output terminals PA, PB, PC and PD of power level control switching means PLC. The switching means comprisefourchange-over switches SW1 to SW4which can be pre-set selectively to apply positive dc potential to the inputs BO, B1, B2 and B3 ofthe comparator IC2.
In operation ofthe power control arrangement the binary counter 101 will be enabled by an inputto its "enable" terminal in response to a demand for power from the load supply circuit The counterthen commences counting from its start position (0000) as it receives clock pulses from the load supply circuit. An output from the comparator causes transistorTR1 to conduct and this may cause thyristorsthrough which power is to be suppled to the load to remain non-conducting. The power level control switching means PLC will have been pre-setto provide a binary coded output in accordance with the power requirements of the load in question.
The binary counter IC1 continues counting until the binary coded output therefrom is identified by the comparator IC2 as being equal to the coded output from the power level control means PLC. At this juncturethe outputfrom the comparatorchangesto cause the conducting transistorTR1 to become non-conducting and in turn this causes the thyristors in the load supply circuitto conduct and thereby supply power to the load.This power will continue to be supplied to the load until the binary counter reaches its last binary count position (1111 ),followed by a return of the counter to its start position (0000) on receipt ofthe next clock pulse which then causes the comparator output to render transistorTR1 once again conducting and to switch off the thyristors supplying the load.
The procedure justabove described isthen repeated and thus for each period of 16 cycles ofthe power supply the supply is disconnected from the load for a numberofcyclescorresponding to the binary coded output ofthe power level control means. For example if the power level control binary coded output is pre-set at binary 5 then five cycles will be excluded from every period of 1 6 cycles of the supply.
The present invention has particular application in heating (e.g. aircraft windshield) arrangements where the power level control means binary output can be varied in accordance with requirements in dependence upon the ambient conditions obtaining at the time.
1. Apowercontrol arrangementforcontrolling load power comprising counting means arranged to be driven through successive counting cycles by clock pulses so that during each counting cycle the counting The drawing(s) originally filed was/were informal and the print here reproduced is taken from a later filed formal copy.
**WARNING** end of DESC field may overlap start of CLMS **.

Claims (7)

**WARNING** start of CLMS field may overlap end of DESC **. SPECIFICATION Improvements relating to power control arrangements This invention relates to power control arrange mentsforcontrolling the ac power supplied to a load according to requirements. According to the present invention a power control arrangementforcontrolling load power comprises counting means arranged to be driven through successive counting cycles by clock pulses preferably derived from the load ac power supply so that during each cou nting cycle the cou nting means provides a continuously changing coded count putput and comparator means which compares the coded count output from the counting means with a pre-set or variable correspondingly coded output from power level control means whereby according to whetherthe countoutputfrom the counting means is greater, equal or less than the instantaneous coded output from the power level control means the comparator output causes switching means in the load power circuit to be rendered effectively closed or open (eg conducting or non-conducting) for a number of cycles ofthe power supply during each counting cycle of the counting means dependent upon the difference between the coded outputs. In carrying outthe invention the counting means maycomprisea binarycounterwith a count of 1 to 16 so that the clock pulses derived from the power supply will cause the counterto perform a full counting cycle for every 16 cycles of the supply. The correspondingly binary coded output from the power level control means may be pre-setto any binary code from 1 to 16 accordingtowhich in each period of ? 6 cycles of the power supply one or more cycles ofthe supply will be excluded by rendering the switching means conducting onlyfrom the point where the count position and coded output of the counting means correspond to the binary coded output of the power level control means up to the last count position ofthecounterbeforethe counter restores to zero. It will readily be appreciated that the coded output from the power level control means may be variable in accordance with some parameter instead of being pre-setto a fixed value. The comparator may comprise a four bit magnitude comparntorwhich compares the four bitword inputs from the binary counter and the power level control means. By way of example one embodiment of the invention will now be described with reference to the accompanying drawing which shows a block schematic diagram of a power control circuit arrangement. Referring to the drawing a four bit binary counter IC1 providing a binary count 1 to 16 and connected across a dc supply is arranged to be driven by clock pulses received from a load ac power supply circuit LPS over line L1. For a clock pulse received by the counter IC1 in respect of each cycle of the power supply the counter is advanced by one step so that for every 16 cycles of the power supply the counter completes a full counting cycle. The binary coded output (iefour bit word) from the terminals QA QB QC and OD of the counter IC1 is applied to one set of input terminals A0, Al, A2 and A3 of a magnitude comparator IC2 also connected across the dc supply. Another set of comparator input terminals B0, B1, B2 and B3 receive a pre-set binary code input (iefour bit word) from output terminals PA, PB, PC and PD of power level control switching means PLC. The switching means comprisefourchange-over switches SW1 to SW4which can be pre-set selectively to apply positive dc potential to the inputs BO, B1, B2 and B3 ofthe comparator IC2. In operation ofthe power control arrangement the binary counter 101 will be enabled by an inputto its "enable" terminal in response to a demand for power from the load supply circuit The counterthen commences counting from its start position (0000) as it receives clock pulses from the load supply circuit. An output from the comparator causes transistorTR1 to conduct and this may cause thyristorsthrough which power is to be suppled to the load to remain non-conducting. The power level control switching means PLC will have been pre-setto provide a binary coded output in accordance with the power requirements of the load in question. The binary counter IC1 continues counting until the binary coded output therefrom is identified by the comparator IC2 as being equal to the coded output from the power level control means PLC. At this juncturethe outputfrom the comparatorchangesto cause the conducting transistorTR1 to become non-conducting and in turn this causes the thyristors in the load supply circuitto conduct and thereby supply power to the load.This power will continue to be supplied to the load until the binary counter reaches its last binary count position (1111 ),followed by a return of the counter to its start position (0000) on receipt ofthe next clock pulse which then causes the comparator output to render transistorTR1 once again conducting and to switch off the thyristors supplying the load. The procedure justabove described isthen repeated and thus for each period of 16 cycles ofthe power supply the supply is disconnected from the load for a numberofcyclescorresponding to the binary coded output ofthe power level control means. For example if the power level control binary coded output is pre-set at binary 5 then five cycles will be excluded from every period of 1 6 cycles of the supply. The present invention has particular application in heating (e.g. aircraft windshield) arrangements where the power level control means binary output can be varied in accordance with requirements in dependence upon the ambient conditions obtaining at the time. CLAIMS
1. Apowercontrol arrangementforcontrolling load power comprising counting means arranged to be driven through successive counting cycles by clock pulses so that during each counting cycle the counting The drawing(s) originally filed was/were informal and the print here reproduced is taken from a later filed formal copy.
means provides a continuously changing coded count output and comparator means which compares the coded count outputfrom the counting means with a correspondingly coded output from power level control means whereby according to whetherthe count outputfrom the counting means is greater, equal or less than the instantaneous coded output from the power level control means the comparator output causes switching means associated with the load power circuit to be rendered effectively closed or open for a number of cycles of the power supply during each count cycle of the counting means dependent upon the difference between the coded outputs.
2. A power control arrangement as claimed in Claim 1 in which the clock pulses are derived from the load a.c. power supply.
3. A power control arrangement as claimed in Claim 1 or Claim 2, in which the correspondingly coded outputfrom the power level control means is pre-setto a fixed value in accordance with the desired level of load power.
4. A power control arrangement as claimed in any preceding claim, in which the counting means comprises a binary counter having a count of 1 to 16 so that clock pulses derived from the power supply or other meanswillcausethecounterto perform a full counting cycle for every 16 cycles ofthe supply whereby in each period of 16 cycles ofthe power supply one or more cycles of the supply will be excluded by rendering the switching means conducting only from the point where the count position and coded output of the counting means correspond to the correspondingly binary coded output of the power level control means up to the last count position ofthe counting means before the latter restores to zero.
5. A power control arrangement as claimed in Claim 1 Claim 2, in which the coded outputfrom the power level control means is made variable in accordance with some parameter.
6. Apowercontrol arrangement asclaimed in Claim 4, in which the comparator comprises a four bit magnitude comparatorwhich compares the four bit word inputs from the binary counter and the power level control means respectively.
7. A power control arrangement substantially as herein before described with reference to the accom- pany drawing.
GB08323486A 1982-10-29 1983-09-01 Power control apparatus Withdrawn GB2129631A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB08323486A GB2129631A (en) 1982-10-29 1983-09-01 Power control apparatus

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB8231036 1982-10-29
GB08323486A GB2129631A (en) 1982-10-29 1983-09-01 Power control apparatus

Publications (2)

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GB8323486D0 GB8323486D0 (en) 1983-10-26
GB2129631A true GB2129631A (en) 1984-05-16

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GB08323486A Withdrawn GB2129631A (en) 1982-10-29 1983-09-01 Power control apparatus

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1148316A (en) * 1965-05-04 1969-04-10 Automatisme Cie Gle Improved current control system
GB2041672A (en) * 1979-02-01 1980-09-10 Gen Electric Pulse repetition rate power control for resistive heater
GB2041673A (en) * 1979-02-01 1980-09-10 Gen Electric Power control for resistive heaters
GB2041674A (en) * 1979-02-01 1980-09-10 Gen Electric Power control for resistive heater using high inrush current element
GB2060224A (en) * 1979-10-01 1981-04-29 Xerox Corp Electrical Power Regulating Arrangement
GB2108734A (en) * 1981-10-16 1983-05-18 Raytheon Co Regulated power supply apparatus and method of regulating power

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1148316A (en) * 1965-05-04 1969-04-10 Automatisme Cie Gle Improved current control system
GB1190215A (en) * 1965-05-04 1970-04-29 Automatisme Cie Gle Current Control Apparatus
GB2041672A (en) * 1979-02-01 1980-09-10 Gen Electric Pulse repetition rate power control for resistive heater
GB2041673A (en) * 1979-02-01 1980-09-10 Gen Electric Power control for resistive heaters
GB2041674A (en) * 1979-02-01 1980-09-10 Gen Electric Power control for resistive heater using high inrush current element
GB2060224A (en) * 1979-10-01 1981-04-29 Xerox Corp Electrical Power Regulating Arrangement
GB2108734A (en) * 1981-10-16 1983-05-18 Raytheon Co Regulated power supply apparatus and method of regulating power

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Publication number Publication date
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WAP Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1)