GB2060224A - Electrical Power Regulating Arrangement - Google Patents

Abstract

An open loop controller regulates the voltage across a controlled element in a host machine by varying the duty cycle of a triac controlling the power supply to the controlled element in response to the measured voltage of a power source. The output of the power source is sampled by circuitry electrically isolated from it, and a signal representative of the variable electrical input to the controlled element supplied to the controller, which supplies a digital equivalent of the sample signal to vary the duty cycle of the triac so as to provide a constant average voltage across the controlled element.

Description

SPECIFICATION Electrical Power Supply This invention relates to electrical power supplies.

In computerized control of host machines or processes, it is often desirable to control a relatively high voltage input to a heating element, lamp or other alternating current operating device. A common method of control in the prior art is shown in U.S. Patent 3,553,428 in which the temperature of a heater is monitored by a thermocouple and a corresponding signal conveyed to an amplifier and SCR firing circuit to trigger an SCR switch inserted in the power line between the power source and the heater.

Proportional control is obtained by providing a feedback circuit between the SCR switch and the input to the control amplifier from a summing point. This type of control is generally referred to as closed loop or feedback control.

Another method of control is a sampling technique in which the voltage across the controlled element is sampled by a lamp. The emitted light from the lamp is proportional to RMS voltage across the controlled element. A photodetector converts the light into a direct current voltage for controlling a switch and a triac. The triac is gated in order to remove cycles of alternating current across the controlled element in order to regulate voltage across the controlled element.

A disadvantage of the prior art control systems is that the control is often at a relatively high voltage level and specific to the sensing of a predetermined state of the controlled device for example, the voltage across the element. A particular disadvantage in systems using a lamp is that the lamp degrades with time.

Other typical prior art power supply circuits for heating elements maintain constant power to the heating element by using a series regulator. These circuits, however, have low efficiencies because of the dissipation of power in the series regulator.

Other prior art power supply circuits such as shown in U.S. Patent 3,794,808 control power to the heating element by automatically changing the duty cycle to correspond with changes in the supply voltage. A resistor and capacitor are connected in series with the power supply and the power supply is also connected across the heating element. A switch is inserted in parallel with the capacitor to periodically discharge the capacitor to a comparator circuit for comparing the capacitor voltage with a reference voltage.

The output of the comparator provides an on and off signal to another switch in series with the heating element and the power supply to gate the power supply voltage across the heating element.

A disadvantage with this type of system and similar systems is that in order to provide different levels of heating power across the heating element it is necessary to change component values, for example, the values of capacitance and resistance in series with the power supply.

It would therefore, be desirable to provide a reliable control system, at a relatively low, isolated voltage level to regulate the voltage across a controlled element. It would also be desirable to provide a control system that is independent of feedback and not limited to sensing a predetermined state of the controlled device.

Accordingly, it is an aim of the present invention to provide a power supply with a versatile and flexible open loop control.

The present invention provides a power supply as claimed in the appended claims.

By 'triac' in this specification is meant a bidirectional triode thyristor.

For a better understanding of the present invention, reference may be had to the accompanying drawings, wherein the same reference numerals have been applied to like parts and wherein.

Figure 1 is a general block diagram illustration of a controller and host machine in accordance with the present invention; Figure 2 is a schematic diagram of the analogto-digital conversion circuitry of the controller shown in Figure 1; Figure 3 is a more detailed block diagram of the controller in accordance with the present invention; Figures 4a, 4b and 4c are schematic diagrams of details of the controller shown in Figure 3.

With reference to Figure 1 , there is shown a controller generally indicated at 10 including microprocessor 12, dedicated circuitry 16, powerup reset circuitry 18, and zero crossover circuitry 20 controlling the host machine or process 22, including a low voltage power supply 23 connected to an input line voltage source ACH, ACN. Preferably, the microprocessor 12 includes a 2K by 8 read only memory ROM 24, address stack 26, 64 by 8 random access memory RAM 28, an 8 bit arithmetic logic unit ALU 30, control 32, clock counter 34, programmable timer 36, interrupt control 38, an 8 bit input-output port 40, and analog-to-digital converter ADC 42 interconnected to a common internal bus. A bidirectional bus 62 is shown interconnecting the microprocessor 12 and host machine 22.The bus 62 generally conveys signals from sensors and switches of host machine 22 to microprocessor 12 and conveys control signals from microprocessor 12 to host machine 22.

In accordance with the present invention, as seen in Figures 1 and 3, dedicated circuitry 1 6 interconnects low voltage power supply 23 with analog-to-digital converter ADC 42 of microprocessor 12. The low voltage power supply 23 responds to an AC input voltage source, typically 11 5 volts AC as illustrated by lines ACH and ACN, to provide the dedicated circuitry 16 with a stepped down and rectified voltage.

Dedicated circuitry 16 conveys to ADC 42 a stabilized reference voltage and a sample voltage related to the input voltage source. These signals are processed by microprocessor 12 to provide a digital signal for selective gating or control of a predetermined element in host machine 22.

Microprocessor 12 is also connected to conventional power-up reset circuitry 18 and zero crossover detection circuitry 20 providing suitable signals for synchronization. It should be noted that analog to digital converter ADC 42 could be external to microprocessor 12. With reference to Figure 2, analog to digital converter ADC 42 comprises a 6 bit counter 44, a resistor switching network 46, an analog comparator 48, and clock divider and control 50 with suitable clock signals for converting a 3 through 7 volt analog input voltage VIN to a 6 bit digital output. At the beginning of the conversion sequence, an enable flip-flop 52 gates on the clock divider and control 50 causing the 6 bit counter 44 to count up.The digital values in the counter 44 are applied to the resistor switching network 46 through suitable gates in combination with a reference voltage VREF setting up a resistor combination that produces an analog output signal VCMP. The output signal VCMP is a fraction of the input reference voltage VREF as determined by digital value in the counter 44 applied to resistor switching network 46. The output of the network 46 provides one input to analog comparator 48 and the second input to the analog comparator 48 is the input voltage VIN.

A typical method of conversion is the following: if voltage VIN is greater than voltage VCMP, counting continues. The compare voltage VCMP, in analog form, is equivalent to the count in the 6 bit counter 44. An increment of one bit in the counter causes an increment of one analog unit or 62.5 millivolts in VCMP. When voltage VIN becomes less than voltage VCMP, conversion is complete and the digital value in the counter is within one bit value of the analog input VIN. The enable flip-flop 52 is reset and the clock divider and control 50 gated off. The contents of the counter 44 representing the digital equivalent of voltage VIN are then transferred via the internal data bus 43 within the microprocessor 12.

With reference to Figures 3, 4a, 4b and 4c, there is shown a control in accordance with the present invention. In particular, the signals of various host machine switches 54 and sensors 56 are conveyed through a resistance network 58 and suitable buffers 60 to an 8 bit external data bus 62 connected to microprocessor 12.

Typically, the resistance network 58 is any standard dual inline package configuration of thick film elements baked onto a ceramic substrate, terminated with wire leads and providing resistance in the range of 22 ohms to 220K ohms. Buffers 60 are preferably octal buffers and line drivers with three state outputs.

The 8 bit data bus 62 is also connected to a suitable memory device such as EPROM 64 interconnected to microprocessor 12 through suitable address lines 66. It should be noted that the EPROM device 64 can be replaced by a suitable read only memory internal to the microprocessor 12.

Outputs to the host machine controlled elements are conveyed from the microprocessor 12 along the external data bus 62 to various latches 68a, 68b and 68c. The latches are preferably Schotky TTL octal d-type flip-flops and are interconnected to various drivers 70, 71 and 72, or transistors 73 to activate various clutches, solenoids, motor drives, triacs and power supplies in machine 22. Typical drivers 70 are high voltage, high current Darlington transistor arrays with high breakdown voltage and internal suppression diodes. Preferably, drivers 71 and 72 are peripheral NAND gates.

The special dedicated circuitry,16, provides voltage reference signal VREF at pin 19 of the microprocessor 12 and voltage VIN at pin 18 of the microprocessor. The voltage VIN represents input line voltage, in essence, the degree of variation of the input line voltage. The variation in the input line voltage as reflected by the voltage VIN to the microprocessor 12 provides a sample signal for controlling a specific element of the process or machine 22 operating on the AC input line voltage.

The low voltage power supply 23 as seen in Figure 4a includes step down transformer 128 and fuil wave rectifier 130 providing a +26 volt signal to dedicated circuitry 16. The dedicated circuitry 16 responds to the low voltage power supppy signal to provide VREF through suitable stabilization circuitry 92 and to provide sample signal VIN through operational amplifier 90.

Sample signal VIN is thus transformer isolated from the input voltage source and rectified to provide a DC sample voltage centered around 5 volts at the output of amplifier 90. The DC sample voltage is converted to an equivalent digital signal by converter ADC 42.

In accordance with the present invention, microprocessor 12 then relates the AC input voltage to the equivalent digital signal and controls the average RMS voltage across a specific controlled element by selective activation of a triac gating the AC input voltage across the controlled element. The host machone 22, as illustrated in Figure 3, includes AC load 74 activated by triac 78 through transformer 82.

Therefore, microprocessor 12 monitors the input voltage source through dedicated circuitry 1 6 and power supply 23 and provides the control of the triac 78 to produce a relatively constant average RMS voltage across AC load 74 regardless of variations in the input voltage source.

Specifically, the microprocessor 12 responds to the digital equivalent of VIN in counter 44 to selectively activate triac 78. For example, if 101 RMS input volts provides an average of 101 volts RMS across AC load 74, then 115 volts RMS input would produce an average RMS voltage greater than 101 volts. Therefore, in order to maintain an average 101 volts RMS across AC load 74, at 11 5 volts RMS input, it is necessary to inhibit or steal selected AC cycles through AC load 74. This is achieved by the selective gating of triac 78 to inhibit cycles across the load 74 to produce an average 101 volts RMS across load 74.

With further reference to Figures 3, 4a, 4b and 4c, there is pulse train generation circuitry connected to the microprocessor 12 including a dual 4 bit binary counter 86 receiving clock out signals from the microprocessor 12 and an octal buffer and driver 88. The counter 86 counts down the clock out signal producing a suitable periodic signal conveyed to the octal buffer and driver 88.

The output of the driver 88 provides a pulse train TTF to peripheral driver 71 and the other input to the peripheral driver 71 is the output of pin 40 of latch 68a. The output of pin 4Q going high, enables driver 71 and the output of the driver 71 activates triac 78 through transformer82. In effect, the combination of the pulse train TTF and the output from pin 40 of the octal latch 68a in response to data from the microprocessor 12 over the data bus 62, generates an output from the driver 71 activating triac 78. The driver 71 activating triac 78 determines the duty cycle or degree of activation of the controlled AC load 74. In effect, an open loop control of a particular machine element is provided by monitoring the input voltage source and without the necessity of a sensor and feedback signal.

The stabilized reference voltage VRF and the input voltage VIN are applied to pins 1 9 and 1 8 of microprocessor 12 respectively. Pin 18 is one input to analog comparator 48 as seen in Figure 2 and the reference VREF is an input to the resistor switching network 46. Since driver 71 is a NAND gate, the output of driver 71 will be low when the pulse train signals TTF, and the output from pin 4Q are both high. The output of pin 4Q going high at a particular pulse train signal TTF going high, provides a low signal output from the driver 71 and inhibits activation of the triac 78 through the transformer 82. In effect, the output of the octal latch 68a going high determines the activation of the triac 78 or the duty cycle of the AC load 74.

By selectively gating the triac 78, the average RMS voltage across the load 74 is controlled.

Claims (9)

Claims

1. An electrical power supply for a load, including terminals across which a power source is to be connected, and connected through a switch with terminals across which the load is to be connected; means, electrically isolated from the power source terminals, for sampling the output of the power source; a comparator for comparing the sampled signal with a reference signal, and means for varying the duty cycle of the switch in dependence on the output of the comparator.

2. A power supply as claimed in claim 1, in which the sampled signal is digitized before it is fed to the comparator.

3. The power supply according to claim 2, in which the comparator and means for digitizing includes a resistor switch network, an analog comparator, and a digital counter; in which the input signals to the analog comparator are the sampled signal and the output of the resistor switch network, and in which the input signals to the resistor switch network are the reference signal and the output of the digital counter.

4. The power supply according to any preceding claim, in which the sampling means is isolated from the comparator by a transformer and rectifier.

5. The power supply according to any preceding claim, wherein the switch is a bidirectional triode thyristor, and in which the sample signal is provided by an operational amplifier producing three to seven volts.

6. A method of supplying an electrical load with a substantially-constant voltage from a variable power source through a switch connected therebetween, despite fluctuations in the voltage of the source, including the steps of: providing a sample signal representative of the voltage source; isolating the sample signal from the voltage source; providing a reference signal; comparing the sample signal with the reference signal, and selectively activating the switch in response to the result of the comparison.

7. The method according to claim 6 wherein the sample signal is digitised by feeding the contents of a digital counter to a resistor network, obtaining from the network an analog signal related to the contents of the digital counter, and comparing the analog signal with the sample signal.

8. The method according to claim 6 or 7, wherein the sample signal is rectified and integrated before the comparison step.

9. The method according to claim 6 or 7, wherein the sample signal is isolated from the comparator by means of a step-down transformer.

1 0. An electrical power source substantially as described and claimed herein with reference to the accompanying drawings.