CA1156338A - Open loop controller - Google Patents

Abstract

ABSTRACT
An open loop controller employing dedicated circuitry and a processor for regulating the voltage across a controlled element in a host machine. The dedicated circuitry provides a sample signal represen-tative of a variable electrical input to the controlled element and the controller provides a digital equivalent of the sample signal to selectively activate a triac gating the controlled element. The selective activation of the triac regulates the voltage to provide a relatively constant average voltage across the controlled element.

Description

-OPEN LOOP CONTROLLER
BACKGROUND
This invention relates generally to computerized controllers of host machines and in particular, to open loop control of host machine elements.
In computerized control of host machines or processes, it is often desirable to control a relatively high voltage input to a heating element, lamp or other alternating current operating device. A common method of control in the prior art shown in U.S. Patent 3,553,428 in which the temperature of the heater is monitored by a thermocouple and a corresponding signal conveyed to an amplifier and SCR firing circuit to trigger an SCR
switch inserted in the power line between the power source and the heater. Proportional control is obtained by providing a feedback circuit between the SCR switch and the input to the control amplifier from a summing point. This type of control is generally referred to as closed loop or feedback control.
Another method of control is a sampling tech-nique in which the voltage across the controlled element is sampled by a light bulb. The emitted light from the light bulb is proportional to RMS voltage across the controlled element. A photodetector converts the light into a direct current voltage for controlling a switch and a triac. The triac is gated in order to remove cycles of alternating current across the controlled element in order to regulate voltage across the controlled element.
A disadvantage of the prior art control systems is that the control is often at a relatively high voltage level and specific to the sensing of a predetermined state of the controlled device for example, the voltage across the element. A particular disadvantage in systems using a light bulb is that the light bulb degrades with time.

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1 i56338 Other typical prior art power supply circuits for heating elements maintain constant power to the heating element by using a series regulator. These circuits, however, have low efficiencies because of the dissipation of power in the series regulator. Other prior art power supply circuits such as shown in U.S.
Patent 3,794,808 control power to the heating element by automatically changing the duty cycle to correspond with changes in the supply of voltage. A resistor and capacitor are connected in series with the power supply and the power supply is also connected across the heating element. A switch is inserted in parallel with the capacitor to periodically discharge the capacitor to a comparator circuit for comparing the capacitor voltage with a reference voltage. The output of the comparator provides an on and off signal to another switch in series with the heating element and the power supply to gate the power supply voltage across the heating element.
A disadvantage with this type of system and similar systems is that in order to provide different levels of heating power across the heating element it is necessary to change component values, for example, the values of capacitance and resistance in series with the power supply.
It would, therefore, be desirable to provide a reliable control system at a relatively low, isolated voltage level to regulate the voltage across a controlled element. It would also be desirable to provide a control syætem that is independent of feedback and not limited to sensing a predetermined state of the controlled de~vice.
Accordingly, it is an object of/the ~ en~
invention to provide an improved controller providing a versatile and flexible open loop control. Further advantages of the present invention will become apparent as the following description proceeds, and the features characterizing the invention will be pointed out in the .

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claims and next to and forming a part of this specifi-cation.
Briefly, the present invention is concerned in one aspect with a controller having dedicated circuitry and a processor for controlling a host machine having at least one controlled element connected to a variable voltage source. The dedicated circuitry interconnects the variable voltage source to analog to digital conver-sion circuitry through a low voltage power supply and the dedicated circuitry provides to the analog to digital conversion circuitry a reference signal and also a sample signal representative of the variable voltage source.
The analog to digital conversion circuitry provides a digital equivalent of the sample signal and in response to the digital equivalent, the controller activates a triac connected to the controlled element. The triac selectively gates the variable voltage source through the controlled element in order to provide a relative constant average voltage across the controlled element.
Other aspects of the invention are as follows:
A power supply for a heating element comprising a heating element, a power source for energizing the heating element, a gate for selectively connecting and dis-connecting the heating element and the power source;
means for generating a substantially constant reference vol~age;
sampling means for providing a sample of the voltage of the power source;
isolation means including a transformer and voltage rectifier disposed between the power source and the sampling means 1 ~5633~

-3a-a comparator for comparing the sampled voltage from the power source with the constant reference voltage;
means to digitize the compared voltage; the com-parator and means for digitizing including a resistor switch network, an analog comparator, and a digital counter and wherein the input signals to the analog comparator are the sampled voltage and the output of the resistor switch network and the input signals to the resistor switch net-work are the reference voltage and the output of the digital counter; and means responsive to the digitized voltage for increasing the duty cycle of the gate in response to decreases in sampled voltage relative to the constant reference voltage and for decreasing the duty cycle of the gate in responses to increases in the sampled voltage .
relative to the constant reference voltage.
For a better understanding of the present inven-tion, reference may be had to the accompanying drawings, wherein the same reference numerals have been applied to like parts and wherein:
Figure 1 is a general block diagram illustration of a controller and host machine in accordance with the present invention;
Figure 2 is a schematic diagram of the analog to digital conversion circuitry of the controller shown in Fig. l;
Figure 3 is a more detailed block diagram of the contrsller in accordance with the present invention;
Figures 4a, 4b and 4c are schematic diagrams of details of the controller shown in Figure 3.
DESCRIPTION OF THE INVENTION
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With reference to Figure 1, there is shown a controller generally indicated at 10 including micro-:
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processor 12, dedicated circuitry 16, power up resetcircuitry 18, and zero crossover ciucuitry 20 controlling the host machine or process 22 including a low voltage power supply 23 connected to an input line voltage source ACH, ACN. Preferably, the microprocessor 12 includes a 2K by 8 read only memory ROM 24, address stack 26, 64 by 8 random access memory RAM 28, an 8 bit arithmatic logic unit ALU 30, control 32, clock counter 34, pro-grammable timer 36, interrupt control 38, an 8 bit input-output port 40, and analog to digital converter ADC 42interconnected to a common internal bus A bidirectional bus 62 is shown interconnecting the microprocessor 12 and host machine 22. The bus 62 generally conveys signals from sensors and switches of host machine 22 to micro-processor 12 and conveys control signals from micropro-cessor 12 to host machine 22.
In accordance with the present invention, as seen in Figures 1 and 3, dedicated circuitry 16 inter-connects low voltage power supply 16 with analog to digital converter ADC 42 of microprocessor 12. The low voltage power supply 23 responds to an AC input voltage source, typically 115 volts AC as illustrated by lines ACH and ACN, to provide the dedicated circuitry 16 with a stepped down and rectified voltage. Dedicated cir-cuitry 16 conveys to ADC 42 a stabilized reference voltage and a sample voltage related to the input voltage source.
These signals are processed by microprocessor 12 to provide a digital signal for selective gating or control of a predetermined element in host machine 22.
Microprocessor 12 is also connected to con-ventional power up reset circuitry 18 and zero crossover detection circuitry 20 providing suitable signals for synchronization. It should be noted that analog to d~gital converter ADC 42 could be external to micropro-cessor 12.
With reference to Figure 2, analog to digital 1 ~ 5~

converter ADC 42 comprises a 6 bit counter 44, a resistor switching network 46, an analog comparator 48, and clock divider and control 50 with suitable clock signals for converting a 3 through 7 volt analog inp~t voltage VIN to a 6 bit digital output. At the beginning of the conversion sequence, an enable flip-flop 52 gates on the clock divider and control 50 causing the 6 bit counter 44 to count up. The digital values in the counter 44 are applied to the resistor switching network 46 through suitable gates in combination with a reference voltage VREF setting up a resistor combination that produces an analog output signal VCMP. The output signal VCMP is a fraction of the input reference voltage VREF
as determined by digital value in the counter 44 applied to resistor switching network 46. The output of the network 46 provides one input to analog comparator 48 and the second input to the analog comparator 48 is the input voltage VIN.
A typical method of conversion is the following:
if voltage VIN is greater than voltage VCMP, counting continues. The compare voltage VCMP, in analog form, is equivalent to the count in the 6 bit counter 44.
An increment of one bit in the counter causes an incre-ment of one analog unit or 62.5 millivolts in VCMP.
When voltage VIN becomes less than voltage VCMP, con-version is complete and the digital value in the counter is within one bit value of the analog input VIN. The enable flip-flop 52 is reset and the clock divider and control S0 gated off. The contents of the counter 44 representing the digital equivalent of voltage VIN are then transferred via the internal data bus 43 within the microprocessor 12. For a more detailed discussion of microprocessor 12 including ADC 42, reference is made to U. S. Patent No. 4,137,567, George E. Mager et al, issued January 30, 1979.
With reference to Figures 3, 4a, 4b and 4c, , .~ ' . ~ . , ',- :

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1 ~6338 there is shown a control in accordance with the present invention. In particular, the signals of various host machine switches 54 and sensors 56 are conveyed through a resistance network 58 and suitable buffers 60 to an 8 bit external data bus 62 connected to microprocessor 12. Typically, the resistance network 58 is any standard dual inline package configuration of thick film elements baked onto a ceramic substrate, terminated with wire leads and providing resistance in the range of 22 ohms to 220R ohms. Buffers 60 are preferably octal buffers and line drivers with three state outputs. The 8 bit data bus 62 is also connected to a suitable memory device such as EPROM 64 interconnected to microprocessor 12 through suitable address lines 66. It should be noted that the EP~OM device 64 can be replaced by a suitable read only memory internal to the microprocessor 12.
~ utputs to the host machine controlled elements are conveyed from the microprocessor 12 along the external data bus 62 to various latches 68a, 68b and 68c. The latches are preferably Schotky TTL octal d-type flip-flops and are interconnected to various drivers 70, 71 and 72, or transistors 73 to activate various clutches, solenoids, motor drives, triacs and power supplies in machine 22. Typical drivers 70 are high voltage, high current Darlington transistor arrays with high breakdown voltage and internal suppression diodes. Preferably, drivers 71 and 72 are peripheral NAND gates.
The special dedicated circuitry, 16, provides voltage reference signal VREF at pin 19 of the micro-processor 12 and voltage VIN at pin 18 of the micro-processor. The voltage VIN represents input line voltage, in essence, the degree of variation of the input line voltage. The variation in the input line voltage as reflected by the voltage VIN to the microprocessor 12 provides a sample signal for controlling a specific element of the process or machine 22 operating on the :

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, AC input line voltage.
The low voltage power supply 23 as seen in Figure 4a includes step down transformer 128 and full wave rectifier 130 providing a +26 volt signal to dedi-cated circuitry 16. The dedicated circuitry 16 respondsto the low voltage power supply signal to provide VREF
through suitable stabilization circuitry 92 and to provide sample signal VIN through operational amplifier 90. Sample signal VIN is thus transformer isolated from the input voltage source and rectified .o provide a DC $ample voltage centered around 5 volts at the output of amplifier 90. The DC sample voltage is converted to an equivalent digital signal by converter ADC 42.
In accordance with the present invention, microprocessor 12 then relates the AC input voltage ; to the equivalent digital signal and controls the average RMS voltage across a specific controlled element by selective activation of a triac gating the AC input voltage across the controlled element. The host machine 22, as illustrated in Figure 3, includes AC load 74 activated by triac 78 through transformer 82. Therefore, microprocessor 12 monitors the input voltage source through dedicated circuitry 16 and power supply 23 and provides the control of the triac 78 to produce a relatively constant average RMS voltage across AC load 74 regardlegs of variations in the input voltage source.
Specifically, the microprocessor 12 responds to the digital e~uivalent of VIN in counter 44 to selec-tively activate triac 78. For example, if 101 RMS input volts provides an average of 101 volts RMS across AC
load 74, then 115 volts RMS input would produce an average RMS voltage greater than 101 volts. Therefore, in order to maintain an average 101 volts RMS across AC load 74, at 115 volts RMS input, it is necessary to inhibit or steal selected AC cycles through AC load 74. This is achieved by the selective gating of triac .

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78 to inhibit cycles across the load 74 to produce an average 101 volts RMS across load 74.
With further reference to Figures 3, 4a, 4b and 4c, there is pulse train generation circuitry con-nected to the microprocessor 12 including a dual 4 bitbinary counter 86 receiving clock out signals from the microprocessor 12 and an octal buffer and driver 88.
The counter 86 counts down the clock out signal producing a suitable periodic signal conveyed to the octal buffer and driver 88.
The output of the driver 88 provides a pulse train TTF to peripheral driver 71 and the other input to the peripheral driver 71 is the output of pin 4Q
of latch 68a. The output of pin 4Q going high, enables driver 71 and the output of the driver 71 activates triac 78 through transformer 82. In effect, the com-bination of the pulse train TTF and the output from pin 4Q of the octal latch 68a in response to data from the microprocessor 12 over the data bus 62, generates an output from the driver 71 activating triac 78. The driver 71 activating triac 78 determines the duty cycle or degree of activation of the controlled AC load 74.
In effect, an open loop control of a particular machine element i8 provided by monitoring the input voltage source and without the necessity of a sensor and feedback signal.
The stabilized reference voltage VREF and the input voltage VIN are applied to pins 19 and 18 of microprocessor 12 respectively. Pin 18 is one input to analog comparator 48 as seen in Figure 2 and the reference VREF is an input to the resistor switching network 46. Since driver 71 is a NAND gate, the output of driver 71 will be low when the pulse train signals TTF, and the ou~put from pin 4Q are both high. The output of pin 4Q going high at a particular pulse train signal TTF going high, provides a low signal output 1 15633~

from the driver 71 and inhibits activation of the triac 78 through the transformer 82. In effect, the output of the octal latch 68a going high determines the acti-vation of the triac 78 or the duty cycle of the AC load 74. By selectively gating the triac 78, the average RMS voltage across the load 74 is controlled.
While there has been illustrated and described what is at present considered to be a preferred embodi-ment of the present invention, it will be appreciated that numerous changes and modifications are likely to occur to those skilled in the art, and it is intended in the appended claims to cover all those changes and modifications which fall within the true spirit and scope of the present invention.

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Claims

WHAT IS CLAIMED IS:

1. A power supply for a heating element comprising a heating element, a power source for energizing the heating element, a gate for selectively connecting and dis-connecting the heating element and the power source;
means for generating a substantially constant reference voltage;
sampling means for providing a sample of the voltage of the power source;
isolation means including a transformer and voltage rectifier disposed between the power source and the sampling means a comparator for comparing the sampled voltage from the power source with the constant reference voltage;
means to digitize the compared voltage; the comparator and means for digitizing including a resistor switch network, an analog comparator, and a digital counter and wherein the input signals to the analog comparator are the sampled voltage and the output of the resistor switch network and the input signals to the resistor switch network are the reference voltage and the output of the digital counter; and means responsive to the digitized voltage for increasing the duty cycle of the gate in response to decreases in sampled voltage relative to the constant reference voltage and for decreasing the duty cycle of the gate in responses to increases in the sampled voltage relative to the constant reference voltage.