GB2117149A

GB2117149A - A device for generating binary digit pseudo-random sequences

Info

Publication number: GB2117149A
Application number: GB08301090A
Authority: GB
Inventors: Maurizio Pioli
Original assignee: International Standard Electric Corp
Current assignee: International Standard Electric Corp
Priority date: 1982-01-15
Filing date: 1983-01-15
Publication date: 1983-10-05
Also published as: FR2520136A1; AU557654B2; GB2117149B; ES519024A0; IT8219147A0; IT1153414B; JPH0220021B2; ES8402437A1; JPS58170144A; GB8301090D0; FR2520136B1; CH660102A5; AU9154782A

Abstract

A device which comprises a binary digit pseudo random sequence source (4) and four Exclusive-OR logic circuits (20, 21, 22, 23) for coupling said source to logic apparatus, to which four lines are coupled for transmitting logic data (T1, T2, T3, T4)having a predetermined frequency and supplying at the output (a) of a multiplexer (1) a multiplexer signal having a frequency which is four times the predetermined frequency and responsive to the control of the subject device, in such a way as to define for said multiplexed signal a pseudo-random sequence having a period 2<7>-1 for tributary data T1=T2=T3=T4=logic level "0". <IMAGE>

Description

SPECIFICATION A device for generating binary digit pseudorandom sequences This invention relates to a device for generating pseudo-random sequences of binary digits, of the type comprising seven like logic sequential blocks synchronously driven by a predetermined frequency signal and each thereof assuming at the output the logic level of a related input depending on each pulse of said predetermined frequency signal and assuming at said output a predetermined logic level as a predetermined logic level is present at an input thereof as supplied through a RESET line, the outputs of the first, second, third, fourth, fifth, sixth blocks being respectively coupled to the inputs of the second, third, fourth, fifth, sixth, seventh blocks and the outputs of said sixth and seventh blocks being coupled to corresponding inputs of an Exclusive OR logic circuit the output thereof is coupled to the input of the first block; said device being in use associated with a logic apparatus coupling four discrete lines, which binary code information is transmitted having a frequency equal to the frequency of said predetermined frequency signal with a line for transmitting binary code signals having a frequency which is four times said predetermined signal frequency; said logic apparatus being of the type comprising; four twoinput AND logic circuits, the first inputs thereof being correspondingly coupled to said four lines and the second inputs thereof being derived from a line effective to supply a synchronization signal, first, second, third and fourth Exclusive-OR logic circuits, provided with at least two inputs the first inputs thereof being correspondingly coupled to the outputs of said AND circuits and the second inputs thereof being coupled to said device; and a multiplexer provided with four inputs, to which there are correspondingly coupled the outputs of said first, second, third and fourth Exclusive-OR circuits, and an output coupled to said transmission line, There is already known a device called a "Parallel Selfsynchronising Scrambler" (indicated at 3 in Fig. 1) to whose inputs are coupled four lines respectively transmitting tributary data T1, T2, T3, T3 (at a frequency of 141 Mbits/sec) and whose four outputs are coupled to a multiplexer 1 which is driven at 565 MHz by an oscillator or clock 2 (a frequency divider 2a is associated, therewith for driving the device 3 at 141 MHz); thus at the output A of the multiplexer 1 the data T1, T2, T3, T4 are effectively scrambled and are transmitted on the transmission line at a frequency of 565 Mbits/sec.

The above mentioned device 3 is however affected by drawbacks, which can be summarised as follows: 1) the line errors are three times greater, and 2) it is necessary to provide additional logic control networks for reducing the possibility of having long recursive consecutive zero sequences.

In order to overcome the above mentioned drawbacks there may be used the well known Reset Scrambler (which for example is recommended by the German and French Administrations) indicated in block form in Fig. 2A and 2B.

In Fig. 2a the real scrambler, schematically indicated at 4, is actually a pseudo-random sequence source; said source or generator consists of seven like sequential blocks (or flipflops) A#, A2, A3, A4, AS, A6, A7 at each thereof there have been indicated at D, Q, CK, PR, respectively the input, output clock input (as derived from the divider 2a supplying a clock pulse sequence having a frequency of about 141 MHz) and the present input.

The outputs 01, 02, Q3, Q4, Q5, 06, are directly coupled to the D inputs of the Blocks A2, A3, A4, AS, A6, A7 respectively, while the outputs Q6, Q7, of the blocks A6, A7 are coupled to an Exclusive-OR gate 5, the output of which is coupled to the D input of the block Al.

The tributary data T1, T2, T3, T4 are sent to corresponding AND logic circuits 6, 7, 8, 9, which are jointly applied by synchronization signal S (see Fig. 2a).

The outputs 02, Q1, Oa, Q5 of the AND circuits A2, A1, A7, AS are coupled, respectively to corresponding Exclusive-OR logic circuits 16, 1 7, 1 8, 1 9. The outputs c, d, e, f of the circuits 16 17, 18, 19 are coupled to corresponding inputs of the multiplexer 1.

More specifically said multiplexer 1 provides at the output A thereof the data which are present at the inputs thereof, under the control of a logic block 10 and according to the truth table H1 of Fig. 2b, it should be noted that the input "a" of the logic block 10 is coupled to the output 0 of the first of two flip-flops 1 a, 1 1 b forming the frequency divider 2a, the remaining input b of that same logic block 10 being coupled to the output of an AND circuit 12 to the two inputs thereof there are respectively sent the synchronization signal S and the signal derived from the 0 output of the second flip flop 1 b of the divider 2a.

The operation of the circuitry of Fig. 2a may be easily derived from the truth table of Fig. 2b.

More specifically the first column of said table indicates the elementary times t scanned by the clock signals supplied by the divider 2a, the second to the eighth columns indicate the logic levels of the mentioned outputs 01, 02, Q3, Q4, Q5, 06, 07, the ninth column indicates the logic levels of the preset signal PR, the tenth column indicates the logic level of the synchronization signal S, the eleventh to the fourteenth columns illustrate the signals G 1, G2, G3, G4 of the source 4 used for the scrambling operation, and, finally the fifteenth to the eighteenth columns indicate the logic levels of the signal sequentially sent in that order (that is from the fifteenth to the eighteenth column) at the output A of the Multiplexer 1.

At the elementary time zero (first column) the preset signal is logic level ~ and the signal S is also ~ the outputs of the blocks Al to A7 are at a 1 logic level; in other words at the output A there are present the logic levels of the inputs c, d, as it may be derived from the table H 1.

At the second and third clock pulses (with the preset signal at the logic level 1) the signal S is again ~, thereby to the output A there are sequentially sent the logic levels present at the inputs c, d, thus, by three clock pulses, at the output A there is formed a frame aligning word F (fib. sb table H2) which is known, is: "1 1 1 1 1 ~1 ~~~~~".

At the fourth clock pulse, the signal S is~"1", thereby all the four outputs Q2, Q1, Q7, Q5 of the block A2, Al, A7, AS are used for carrying out the scrambling of the tributary signals T1, T2, T3, T4 (to this end seen the contents of the fourth and following rows from the fifteenth to the eighteenth columns of table H2).

The device illustrated in Fig. 2a, in addition to overcoming the mentioned drawbacks of items 1 (and 2) affords the great advantage that as it is reset it generates the mentioned hard copy frame aligning word F.

On the other hand, said Reset Scrambler is affected by a great drawback. In fact the case where the signals T1, T2, T3, T3 are of the periodic type, in particular T1=T2=T3=T4=QI, the multiplexed signal (at the output A) does not represent a pseudo-random succession of Period 2'-1 but a sequence with a rather approximative randomness, which is greatly objectionable, since in those cases it would be necessary to have sequences as random as possible.

Accordingly the main object of the present invention is to provide a device for generating binary digit pseudo-random sequences, so designed as to give at the output thereof a multiplexed signal consisting of a pseudo-random sequence having a period 2#-1 even in the presence of tributary signals T1, T2, T3, T4 having simultaneously the logic level ~ and the frame aligning word 1 1 1 1 1C#1#QIQ) in hard copy form.

According to one aspect of the present invention there is provided a device an embodiment of the present invention will now be described with reference to the accompanying drawings, in which: Fig. 1 illustrates, in block form, a known device, which has been briefly described hereinbefore, for generating pseudo-random sequences of binary digits; Fig. 2a illustrates also in block form a further known device, also briefly described above, for generating pseudo-random sequences and Fig. 2b illustrating the truth tables of the logic blocks and necessary for understanding the operation of device illustrated in Fig. 2a; Fig. 3 illustrates, in block form, a device according to an embodiment of the present invention; and Fig. 4 illustrates the truth tables for the most significant logic blocks of Fig. 3.

With reference to Fig. 3. it will be clearly apparent that the logic blocks indicated at 1, 2, 4, 2a, 11a, llb, 10,6,7,8,9,16,17,18, 19, are identical to the blocks indicated by those same reference numbers in Fig. 2a.

A RESET line 30 (Fig.3) is coupled to the SET inputs of the sequential blocks Al , A3, A4, A6, A7 and to the RESET inputs of the blocks A2, AS.

Between the Exclusive-OR circuits 1 6, 1 7, 18, 1 9 (respectively the first, second, third and fourth Exclusivc OR circuits) and the source of generator 4, there are arranged four Exclusive~ OR logic circuits 20, 21, 22, 23, (respectively the fifth, sixth, seventh and eight Exclusive-OR circuits), which are coupled as it is shown in Fig.

3.

The Exclusive---OR circuit 20 is provided with three inputs coupled to the outputs 01, 04, 06 of the blocks Al, A4, A6 while the related output is coupled to the second input of the circuit 1 6 of the AND logic circuit 6).

The Exclusivc OR circuit 21 has the input thereof coupled to the output Q6 (block A6) while the related output is coupled to the second input of the circuit 17 (the first input thereof is coupled to the output of the AND logic circuit 7).

The Exclusive-OR circuit 22 is provided with three inputs respectively coupled to the outputs 02, 04, Q5 (blocks A2, A4, A5), while the corresponding output is coupled to the second input of the circuit 18 the first input thereof is coupled to the output of the AND logic circuit 8).

The Exclusive--OR circuit 23 is provided with two inputs respectively coupled to the output 05, Q2 (blocks AS, A2) the corresponding output being coupled to the third input of the circuit 19 (the first input thereof is coupled to the output of the AND logic circuit 9, and the second input thereof is coupled to the RESET line 30).

From an examination of the truth tables K1, K2, K3 (Fig. 4) respectively related to the sequential blocks A7 to Al to the AND logic circuits and to the Exclusive-OR logic circuits or blocks, and from the examination of the particular mutual coupling of the mentioned logic blocks, the mode of operation of the device according to the present invention will be evident, the truth table K4 thereof is illustrated in Fig. 4.

In the first column of said table K4 there is indicated the elementary clock time t scanned by the divider 2a (operating at about 141 MHz); in the second column there are indicated the logic levels S/R present on the RESET line 30; in the third column there is indicated the logic level of the synchronization signal sin the fourth to tenth columns there are indicated the logic levels of the outputs Q7, Q6, Q5, 04, 03, Q2, 01,; in the eleventh to the fourteenth columns there are indicated the logic levels of the outputs P1, P2, P3, P4 respectively of the Exclusive-OR circuits 20, 21, 22, 23, and in the fifteenth to eighteenth columns there are indicated the logic levels of the inputs c, d, e, f of the multiplexer 1. At the time t=~ of the clock (first column, table K4) Sw and S/R=~, the outputs P 1, P2, P3, P4, are at a logic level 1, and there is set the zero time of the clock timing; in the mentioned situation the inputs c, d, e, f, are all at a logic level 1.

More specifically, the particular coupling of the Exclusive-OR circuits 20, 21, 22, 23 to the source 4, brings, at the time t=i of the clock timing, with S# and S/R=~, the outputs P1, P2, P3, P4, respectively to the logic levels "1~1~", which logic levels are correspondingly present at the inputs c, d, e, f.

At the time t=2 of the clock timing (with S again equal to ~), SIR is brought to the logic level the particular coupling of the Exclusive-OR circuits 20, 21, 22, 23 thereinabove mentioned to the source 4, bring the outputs P1, P2, P3, P4, respectively to the logic levels "~~~1 " while the inputs c, d, e, f are brought to the logic levels "~~0~": it should be noted that the fourth bit, at the input f, does not coincide with the logic level 1 of the output P4, since at the second input of the Exclusive-OR circuit 19 there is present the logic level 1 of the line 30.

The mentioned three sequences of four bits, comprise at the output A of the Multiplexer 1 the frame aligning word which, as it is well known, is: "1111 ~1~~~~~".

The logic level S/R=1 at the time t=2 defines, at the time t=3 of the clock timing, a predetermined combination of the logic levels at the outputs Q7, Q6, Q5, 04, 03, 02, Q1 (see the fourth row of the table K4) which, synchronously with the fact that it is S/R# and S=1, starts the scambling operation on the signals T1, T2, T3, T4 (to this end see the inputs c, d, e, f, in the fourth row).

By employing the technical approach according to the present invention (that is the provision of the Exclusive-OR circuits 20, 21, 22, 23 and of the particular connection of the latter with the outputs of the sequential blocks A7 to Al) affords the possibility of obtaining a multiplexed signal (at the output A of the multiplexer 1) having a frequency of about 565 MHz, comprising a pseudo-random sequence of period 2#-1 in the presence of T1=T2=T3=T4=~.

Finally, the coupling of the RESET line 30 to an input of the Exclusive-OR circuit 1 9, as well as the particular coupling of that same line to the SET, RESET inputs of the sequential blocks A7 Al, permits the frame aligning word to be obtained in hard copy form.

It should be noted that the preceding description has been provided only by way of a not limitative example, thereby the above illustrated blocks or logic circuits may be replaced by corresponding ones effective to provide the same function.

Claims

1. A device for generating pseudo-random sequences of binary digits, of the type comprising seven like logic sequential blocks synchronously driven by a predetermined frequency signal and each thereof assuming at the output the logic level of a related input depending on each pulse of said predetermined frequency signal and assuming at said output a predetermined logic level as a predetermined logic level is present at an input thereof as supplied through a RESET line, the outputs of the first, second, third, fourth, fifth, sixth blocks being respectively coupled to the inputs of the second, third, fourth, fifth, sixth, seventh blocks and the outputs of said sixth and seventh blocks being coupled to corresponding inputs of Exclusive-OR logic circuit the output thereof is coupled to the input of the first block; said device being in use associated with a logic apparatus coupling four discrete lines, which binary code information is transmitted having a frequency equal to the frequency of said predetermined frequency signal, with a line for transmitting binary code signals having a frequency which is four times said predetermined signal frequency; said logic apparatus being of the type comprising four two-input and logic circuits, the first inputs thereof being correspondingly coupled to said four lines and the second inputs thereof being derived from a line effective to supply a synchronization signal; first, second, third and fourth Exclusive-OR logic circuits, provided with at least two inputs, the first inputs thereof being correspondingly coupled to the outputs of said AND circuits and the second inputs thereof being coupled to said device and a multiplexer provided with four inputs, to which there are correspondingly coupled the outputs of said first, second, third and fourth Exclusive~ OR circuits, and an output coupled to said transmission line; characterized in that the device further comprises; a fifth Exclusive-OR logic circuit provided with three inputs, coupled respectively to the outputs of said first, fourth and sixth sequential blocks, and with an output coupled in use of the device to the second input of said first Exclusive-Or circuit; a sixth Exclusive~ OR circuit the input thereof is coupled to the output of said sixth sequential logic block and the output thereof is in use of the device coupled to the second input of said second Exclusive-OR circuit; a seventh Exclusive-OR logic circuit provided with three inputs, respectively coupled to the outputs of said second, fourth and fifth sequential blocks and the output thereof is in use of the device coupled to the second input of said third Exclusive-OR logic circuit, and eighth Exclusive-OR logic circuit provided with two inputs coupled respectively to the outputs of said second and fifth sequential blocks and the output thereof is in use of the device coupled to the second input of said fourth Exclusivc OR circuit and that said RESET line is in use of the device coupled to a third input of said fourth Exclusive~ OR circuit and is coupled to the SET inputs of said first, third, fourth, sixth and seventh sequential blocks to the RESET inputs of the second and third sequential blocks.

2. A device for generating pseudo-random sequences of binary digits substantially as herein described with reference to Figs. 3 and 4 of the accompanying drawings.

3. A method of generating pseudo-random sequences of binary digits substantially as herein described with reference to Figs 3 and 4 of the accompanying drawings.