JPH0220021B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Background of the Invention] A device called a parallel self-synchronous scrambler is known, which is shown as 3 in FIG. Data signals T1, T2, T3, T4 respectively
(a frequency of 141 Mbit/s) is input through it, and its four outputs are coupled to a multiplexer, which is provided with an oscillator or clock 2 (in conjunction with which is shown a frequency divider) which outputs a frequency of 141 Mbit/s. driven by)
Driven at 565NHz. Therefore, at the output A of multiplexer 1, data signals T1, T2,
T3 and T4 are effectively scrambled to 565M
It is transmitted over a transmission line at a frequency of bits per second.

However, the device 3 described above is known to have the following drawbacks. That is, (a) the line error becomes three times larger.

(b) It is necessary to provide additional logic circuitry to reduce the possibility of having long recursive consecutive zero sequences.

To overcome these drawbacks, a well-known reset scrambler as shown in FIG. 2 is used.

In FIG. 2a, the actual scrambler, generally designated 4, is a pseudo-random sequence source, which is a source or generator of seven similar clock devices (or flips), A1, A2, A3, A4, A5, A6 and A7, each having an input D, an output Q, a clock input CK (driven by frequency divider 2a providing an output at a frequency of approximately 141 MHz) and a preset input PR.

Outputs Q1, Q2, Q3, Q4, Q5, Q6 are directly connected to blocks A2, A3, A4, A5, A, respectively.
6, coupled to input D of A7, while block A
The outputs Q6, Q7 of block A1 are coupled to an exclusive OR circuit 5, the output of which is coupled to the input D of block A1.

Data signals T1, T2, T3, and T4 are sent to corresponding AND circuits 6, 7, 8, and 9 together with a synchronizing signal S.

Each of the AND circuits mentioned above is sent to a corresponding exclusive OR circuit 16, 17, 18, 19, where the outputs Q2, Q1, Q of blocks A2, A1, A7, A5 are sent.
7, Q5 are connected. Circuit 16, 17, 1
The outputs of 8, 19 are coupled to the corresponding inputs c, d, e, f of multiplexer 1.

More specifically, multiplexer 1 operates under the control of logic clock 10 to generate the table shown in FIG. 2b.
The data given to its input is output from output A according to H1. The input a of the logic clock 10 is coupled to the output Q of the first of the two flip-flops 11a forming the frequency divider 2a, the remaining input b of the logic clock 10 is coupled to the output of the AND circuit 12, The two inputs of the circuit 12 are respectively coupled with a synchronizing signal S and a signal from the output Q of the second flip-flop 11b of the frequency divider 2a.

The operation of the circuit shown in FIG. 2a can be easily understood from the table in FIG. 2b.

More specifically, the first column of the table shows the base time scanned by the clock signal provided by frequency divider 2a. The second to eighth columns show the logic levels of the aforementioned outputs Q1 to Q7. The ninth column shows the logic level of the preset signal PR.
The tenth column shows the logic level of the synchronization signal S. The 11th to 14th columns show signals G1, G2, G3, and G4 of the signal source 4 used for the scrambling operation. Columns 15 to 18 show the logic levels of the signals in the order sent at output A of multiplexer 1 in that order (columns 15 to 18).

At base time zero (first column) the preset signal PR is 0/ and the signal S is also 0/. The outputs of blocks A1-A7 are at logic level 1. In other words, at output A, the logic levels of inputs c and d expected from table H1 are given.

On the second and third clock pulses (the logic level of the preset signal is 1), the synchronization signal S is again 0/, so that the output A continues to receive the logic level applied to the inputs c, d. . Three clock pulses thus form a frame alignment word F (see FIG. 2b, H2) at output A. As it is well known, “111110/
10/0/0/0/0/”.

At the fourth clock pulse, the synchronization signal S is "1", which causes the blocks A2, A1,
4 outputs of A7, A5 Q2, Q1, Q7, Q5
are used to scramble the signals T1, T2, T3, T4 (see columns 15 to 18 of Table H2).

The device shown in Figure 2a suffers from the disadvantages (a) and (b) mentioned above.
It has the advantage of not only overcoming the problem but also generating the aforementioned hardcopy frame alignment word F when resetting. On the other hand, the preset scrambler has a major drawback when the signals T1, T2, T3, and T4 are periodic, especially when T1=T2=
In the case of T3=T4=0/, the multiplexed signal (signal at output A) is not reproduced in a pseudo-random order of ^27-1 , but becomes a somewhat approximate random sequence, which is very undesirable. In such cases it is necessary to have as random a sequence as possible.

[Summary of the invention]

The main object of the invention is to provide signals T1, T2, T
3. Even if T4 goes to logic level 0/ at the same time, multiple signals can be obtained at its output constituting a pseudo-random sequence with a period of 2 ⁷ -1, and in hard copy form the frame alignment word "111110/10/0/0/0/0/''.

According to the invention, this object consists of four separate lines carrying an input signal of binary encoded information having a predetermined frequency, each coupled to a first input and having a synchronization signal at a second input. Four AND circuits are supplied, each having two or more inputs, the first input of which is coupled to the output of the AND circuit, and the second
first, second, third and fourth exclusive OR circuits, the inputs of which are coupled to the pseudo-random sequence generator; and the inputs of the binary code information are coupled to the outputs of these exclusive OR circuits; A pseudo-random sequence generator operating in conjunction with a logic device comprising a multiplexer to output a binary encoded information signal at four times the frequency of the input signal, the pseudo-random sequence generator are driven synchronously to produce at the output the logic level of the associated input depending on each pulse of those signals, and produce a predetermined logic level at the output when the predetermined logic level is supplied through the reset line and appears at its input. 7
comprising blocks of similar logical sequences,
The outputs of the first, second, third, fourth, fifth, and sixth blocks are coupled to the inputs of the second, third, fourth, fifth, sixth, and seventh blocks, respectively; The outputs of the sixth and seventh blocks are coupled to the corresponding inputs of another exclusive-OR circuit, the output of which is a pseudo-random sequence of binary digits coupled to the input of the first block. A generator comprising three inputs respectively coupled to outputs of the first, fourth and sixth blocks and an output coupled to a second input of the first exclusive OR circuit. a sixth exclusive-OR circuit comprising a fifth exclusive-OR circuit and an input coupled to an output of said sixth block and an output coupled to a second input of said second exclusive-OR circuit; a circuit having three inputs each coupled to an output of each of said second, fourth, and fifth blocks and an output coupled to a second input of said third exclusive-OR circuit; 7 exclusive OR circuits, two inputs coupled to the outputs of the second and fifth blocks, respectively, and an output coupled to the second input of the fourth exclusive OR circuit. an eighth exclusive-OR circuit, a reset line being coupled to a third input of the fourth exclusive-OR circuit;
This is achieved by a pseudo-random sequence generator, characterized in that it is coupled to the set input of each block and to the reset input of the remaining second and fifth blocks.

Further features of the invention will become apparent from the following detailed description of embodiments with reference to the accompanying drawings.

[Embodiments of the invention]

Referring to FIG. 3, logic blocks 1, 2, 4,
2a, 11a, 11b, 10, 6, 7, 8, 9, 16, 17,
18 and 19 are identical to the blocks designated by the same reference numerals in FIG. 2a.

Reset line 30 (FIG. 3) connects blocks (clock devices) of the logic sequence A1, A3, A4, A
6, A7 set input and blocks A2, A5
is tied to the reset input.

According to the invention, exclusive OR circuits 16, 17, 1
8, 19 (first, second, third, and fourth exclusive OR circuits, respectively) and the signal source or oscillator 4, four exclusive OR circuits 20, 21, 22, 23 are provided.
(fifth, sixth, seventh, and eighth exclusive OR circuits, respectively) are arranged and are coupled as shown in FIG. 3 and described later.

The exclusive OR circuit 20 consists of blocks A1, A4, and A.
6 has three inputs coupled to outputs Q1, Q4, Q6 of circuit 6, while the output is coupled to a second input of circuit 16 (the first input of circuit 16 is coupled to the output of AND circuit 6). ).

The exclusive OR circuit 21 outputs the output Q6 (block A
6) whose output is coupled to circuit 1
(The first input of circuit 17 is coupled to the output of AND circuit 7.) Exclusive OR circuit 22 outputs Q2, Q4, Q5.
(blocks A2, A4, A5), the output of which is coupled to a second input of circuit 18 (the first input of circuit 18 is coupled to the output of AND circuit 8). ).

Exclusive OR circuit 23 has two inputs coupled to outputs Q5, Q2 (blocks A5, A2),
Its output is coupled to a second input of circuit 19 (the first input of circuit 19 is coupled to the output of AND circuit 9 and the third input is coupled to reset line 30).

Tables K1, K2, K3 relating to blocks A ₁ to _{A 7} for AND circuits and exclusive OR circuits, respectively
The mode of operation of the device of the invention is clear from consideration of the specific interconnections of the logic clocks (FIG. 4) and described above. The true value table is shown in FIG.

The first column of Table K4 in Figure 4 shows the frequency divider 2.
The basic clock time t is shown scanned by a (operating at about 141 MHz). The second column shows the logic level S/R applied to reset line 30. The third column shows the logic level of the synchronization signal S. The 4th to 10th columns have outputs Q7 to Q.
A logic level of 1 is shown. Rows 11 to 14
Each output P ₁ of the exclusive OR circuits 20 to 23 is in the column.
Logic levels from P to _P4 are shown. The 15th to 18th columns are the inputs c, d, and
The logic levels of e and f are shown. At clock time t=0/ (first column of table _K4 ), S=0/,
and S/R=0/, and outputs P1, P2, P
3, P4 is at logic level 1 and sets the zero time of the clock timing. In this state, inputs c, d, e, and f are all at logic level 1.

To explain in more detail, the exclusive OR circuits 20, 21, 22, and 23 are specially coupled to the signal source 4, so that at clock timing t=1, S=0/ and S/R=0/. Yes, the logic level of each output P1, P2, P3, P4 is "10/1"
0/”, and this logic level corresponds to the input c,
given to d, e, f.

At clock timing t=2, S is again 0/ and S/R is at logic level 1. an exclusive OR circuit 20 as described above for the signal source 4;
By special combination of 21, 22, 23, output P
1, P2, P3, P4 are respectively at logic level 0/0/
It becomes 0/1. On the other hand, inputs c, d, e, and f are set to logic level 0/0/0/0/. Note that the fourth bit at input t does not correspond to logic level 1 at output P4. This is because the logic level 1 on reset line 30 is provided at the second input of exclusive-OR circuit 19.

The above three sequences of bits are 111110/10/0/0/0/0 at the output A of the multiplexer.
Construct a frame alignment word, commonly known as /.

The logic level S/R=1 at time t=2 defines a predetermined combination of logic levels at outputs Q7-Q1 (see row 4 of Table K4) at clock timing t=3, which is S/R.
In synchronization with R=0/and S=1, the signal T
1, T2, T3, T4 start scrambling operation (c, d, in the fourth row of Table K4)
(see e, f).

By summarizing the technical approach according to the invention (exclusive OR circuits 20, 21, 22, 2
3 and make special connections with them and the outputs of successive blocks A7...A1) T1=T2=T3=
In the presence of T4=0/ it is possible to obtain a multiplexed signal (signal at output A of multiplexer 1) consisting of a pseudo-random sequence of period ^27-1 and having a frequency of approximately 565 MHz.

Finally, exclusive OR circuit 19 of reset line 30
The connection to the input of block A7...A connects that same line to the input of
In combination with one set/reset input, it is possible to obtain a frame alignment word in hardcopy form.

Although the present invention has been described above with reference to preferred embodiments, these explanations are merely illustrative, and the present invention should not be limited to these embodiments, and the aforementioned blocks and logic circuits do not fall within the scope of the claims. Substitutions may be made by other corresponding devices performing the same function without departing from the scope of the invention as described.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional apparatus for generating pseudo-random sequences of binary digits; FIG.
The figure is a block diagram of another conventional device, FIG. 2b is an explanatory diagram of the operation of the device of FIG. 2a, and FIG.
A block diagram of the embodiment, FIG. 4 is an explanatory diagram of the operation of the apparatus shown in FIG. 3. 1...Multiplexer, 2...Clock, 2a
...Frequency divider, 3...Scrambler, 4...
Scrambler, 6, 7, 8, 9...and circuit,
11a, 11b...flip flop, 16,
17, 18, 19, 20, 21, 22, 23...
Exclusive OR circuit, A1, A2, A3, A4, A
5, A6, A7...Clock device.

Claims (1)

Claims: 1. Four separate lines carrying an input signal of binary encoded information having a predetermined frequency are each coupled to a first input and a synchronization signal is provided to a second input. four AND circuits, and first and second circuits each having two or more inputs, the first input of which is coupled to the output of the AND circuit, and the second input coupled to the pseudorandom sequence generator. , third and fourth exclusive OR circuits, and a multiplexer coupled to the outputs of these exclusive OR circuits to output a binary code information signal having a frequency four times that of the input signal of the binary code information. a pseudo-random sequence generator operating in conjunction with a logic device that is driven synchronously by signals of a frequency equal to said input signal frequency and whose related input signals depend on each pulse of said signals; a block of seven similar logic sequences which produce a logic level at the output and produce a predetermined logic level at the output when the predetermined logic level is applied through the reset line and appears at its input; The outputs of the third, fourth, fifth, and sixth blocks are respectively coupled to the inputs of the second, third, fourth, fifth, sixth, and seventh blocks; in a binary digit pseudo-random sequence generator, the output of the block being coupled to the corresponding input of another exclusive-OR circuit, the output of this exclusive-OR circuit being coupled to the input of the first block; a fifth exclusive OR circuit having three inputs respectively coupled to the outputs of the first, fourth and sixth blocks and an output coupled to the second input of the first exclusive OR circuit; a sixth exclusive-OR circuit having an input coupled to an output of the sixth block and an output coupled to a second input of the second exclusive-OR circuit; , a seventh exclusive OR circuit having three inputs respectively coupled to the outputs of the fourth and fifth blocks, and an output coupled to the second input of the third exclusive OR circuit. and an eighth exclusive OR circuit having two inputs coupled to the outputs of the second and fifth blocks, respectively, and an output coupled to the second input of the fourth exclusive OR circuit. a reset line is coupled to a third input of the fourth exclusive-OR circuit, and a reset line is coupled to the set input of each of the first, third, fourth, sixth and seventh blocks and the remaining A pseudorandom sequence generator, characterized in that it is coupled to reset inputs of the second and fifth blocks.