DE3513916A1 - Pseudo-noise generator - Google Patents

Abstract

The pseudo-noise generator contains a shift register (101 to 10n), two outputs (10n and 10N) of which are connected to an exclusive OR gate circuit (13), the output of which is connected to the input of the register (101). The output sequence is picked up at the output of the register (12N). The number to be converted initialises the registers (111 to 11n). To obtain a virtually unambiguous relation between the converted word and the original word, the number of clock pulses which separate the output word from the input word is changed in dependence on the value of the input word. <IMAGE>

Description

PRINCE, QUIETER, BUNKE ^

Patent Attorneys · Eurodfeari Patöot "AtCorneVs." .... "0 C 1 OQ 1 C Munich" 2 Stuttgart

SOCIETE D'ELECTRONIQUE DE LA ^{27 March 1985}

PAYS DE LOIRE SEREL REGION
74 / rue du Surmelin

75020 Paris / France

Our reference: S 3257

Pseudo-random generator

The invention relates to a pseudo-random generator.

Such a device converts a binary number applied to its input into another binary number. the The number of digits in the output number or output word is generally large. Such a generator is used for coding purposes, for example. The size of the number of binary digits in the output word makes unauthorized decoding more difficult.

However, the law for converting the input word into an output word is not completely random / because if this were the case, no reproducible conversion could take place and decoding would be impossible.

Without knowledge of the implementation law, however, it appears that this is purely coincidental.

HD / bl

Such a generator is generally formed from a shift register and an exclusive OR gate circuit, whose output is connected to the serial input of the register. The first input of the exclusive OR gate circuit receives the signal from a cell of the register with an ordinal number of a certain intermediate value, while the second input of this gate circuit is connected to the output of the same register. the The number or the word is usually entered in parallel into the register on the input side, i.e. all of them at the same time Storage cells. The operation of the register is controlled by a clock signal. With every clock pulse the output of the exclusive OR gate circuit is fed into the first cell of the register, and the content each cell is shifted towards the output, so that the content of the cell with the ordinal number m before the clock pulse becomes the content of the memory cell with the ordinal number m-1.

The output number or the output word is obtained after a certain number X of clock pulses, wherein this number X is fixed and constant for a given pseudo-random generator. The starting word is either by the contents of the various shift register cells at the end of these X clock pulses or by the contents a fraction of these cells, or by a serial sequence of binary digits at the output of the Shift register. In the latter case, the duration of the sequence, i.e. the number of binary digits of the output signal, determined by the structure of the pseudo-random generator.

The output word depends on three parameters: the input word, the intermediate number of the memory cell, to which the first input of the exclusive OR gate circuit is connected, and the number X of clock pulses, which separate the input word from the output word. Since the

the last two parameters are constant, there is no risk of an unauthorized person discovering these parameters disappearing.

The invention increases the difficulty of unauthorized decoding.

For this purpose, the output word does not appear until a time t, which depends on the input word, after it has been created of this input word. In this way, another parameter is built into the implementation through which decoding becomes even more difficult.

In another embodiment, the number of binary digits in the output word also depends on the value of the input word away.

To change the duration t depending on the value of the input word, a read-only memory is used, for example used, in which the values of the durations t are stored, which are stored in the memory as a function of the input words applied to it are submitted. The amendment law can also be programmed by means of Microprocessor to be created.

If the output word is in parallel and has the same number of binary digits as the input word, the change in the duration t depending on the value of the input word can be made even more complex in the following way: at the end of a first duration t ₁ , which depends on the value of the input word G. depends, the output word G. is viewed as a new input word that defines a new value t_. Such an interruption of the sequence occurs A times, this number A preferably depending on the value of the input word. The output word G _A is that which appears after A cycles or interruptions of sequences.

Further features and advantages of the invention emerge from the following description of exemplary embodiments and from the drawing referred to. In the drawing show:

1 shows a block diagram of a pseudo-random generator;

2 shows an illustration of the output word of such a pseudo-random generator; and

Figure 3 is a flow diagram showing the control of the pseudo-random number generator according to Fig. 1 shows.

A pseudo-random generator contains a shift register 10, which is formed from bistable flip-flops 1CL, 10 ₂ - .. 10-, which are connected in series. The serial input is formed by the input of the first flip-flop 1O ₁ , while the serial output is formed by the output 12 of the last flip-flop 1O _n .

Each flip-flop contains an additional input 1O ₁ , 102 · - · 1 0-, / to which a binary digit of a parallel input word is applied.

An output of an intermediate trigger circuit 10 (n <N) is connected to the first input 1S _{1 of} a gate circuit 13 of the "Exclusive OR" type, the second input 13 of which is connected to the output 12 of the trigger circuit _{1O n.} The output 13 of the gate circuit 13 is connected to the serial input of the flip-flop circuit 1O ₁ . The truth table of the exclusive OR gate circuit is as follows:

13.,

¹³ I 1 ¹³ 2

0 I o

ο! 1

1 ! ο

O
1
1
O

χ The operation of the pseudo-random generator is through clock pulses H controlled, which are applied to the corresponding inputs of the trigger circuits 10 ..... 10.

A conventional pseudo-random generator works as follows: the binary digits of a number G, which is referred to as the input word, are applied to the parallel inputs 11 ^ ... 11__. After the first clock pulse H, the flip-flop 1O ₁ stores the output signal of the IQ gate 13, the flip-flop 10 stores the digit that was previously in the flip-flop 10, and in the same way each of the other flip-flops stores the previous contents of the previous flip-flop.

The output word appears after a predetermined number X of clock pulses. This output word, which is parallel, for example, is _{tapped at the outputs 12 .., 12 2} · ..12. It can also be a serial output word: in this case it is the one at output 12,. Binary number appearing from the X th clock pulse. This serial number has, for example, m binary digits. So it is received during the m clock pulse.

The output signal is periodic. The period is:

P = (2 - -1) t, where τ is the period of the clock signal.

Because of the periodic behavior of the output sequence S, it can be represented by a circle 15 (FIG. 2) be on. On this circle, point 16 represents the moment the injection of the input word G, while point 17 is the point in time at which the output word occurs begins, the time interval between points 16 and 17 being: t = X. τ

The arc 18 represents the duration of the m bits of the output word when this is serial.

-tr

According to one embodiment of the invention, the Number X is not independent of the input word, i.e. the position of point 17 changes depending on the value of the Input word G. According to a second embodiment of the invention, the number of bits of the output word depends i.e. the number m or the length of the arc 18, depending on the value of the input word G. The features of the second embodiment can be used in combination with those of the first or independently.

So that the number X depends on the word G, a read-only memory (not shown) is used, for example, in which values X are stored and the input word G is applied to the inputs. The number X is used in order to load a time register or a counter (not shown), the content of which with each clock pulse decreases by one unit and which indicates the end of the sequence when its content has decreased to zero.

The law of transformation for converting the input word G into a time t _D can also be obtained by programming, as will be described with reference to FIG. 3.

In this embodiment, several cycles or interruptions of the sequence or sequence are made therewith the transformation law for the implementation of G in t becomes even more complex. The meaning of the term "interruption the sequence "results from the following description.

Figure 3 is a flow chart which forms part of the present description of the invention.

The initialization word G _Q is the one that is applied to inputs 11 ..... 11: it is the input word.

A number A of cycles to be carried out is assigned to the word G _Q. The implementation can be done by means of a read-only memory or according to a predetermined law that is calculated by a computer or microcomputer. The output word G _n is also used to define a number X of clock pulses, after which the sequence is interrupted or after which the output word K occurs.

The time t = X (G). τ is entered as the number T in a time register. So that this number T is not too small, becomes arbitrarily the bit of the ordinal number Ω of this number T is set to the value 1, thus the time between the points

16 and 17 has at least the value 2.

The part 20 on the left in the flow chart of FIG. 3 corresponds to the operation of a conventional pseudo-random generator.

At the end of a first cycle, i.e. when the content of the time register has become zero, the time t has expired, and the content of the register into which the number A was entered is decreased by one unit; if this content has not yet reached the value zero, the output word G 'is used to give a duration t

Define XV. This process represents an interruption in the sequence or sequence.

If, on the other hand, the content of the register for the numbers A has become zero, the sequence or sequence is ended, and the content of the various flip-flops forms the output word G '.

Claims (6)

PRINZ, LEISER, BUNT ^ E: Sc: PARTIER / Patentanwälte · Euroheah Pafanf Attorneys · - "OE 1 OQ 1 G <* Munich Stuttgart SOCIETE D'ELECTRONIQUE DE LA March 27, 1985 REGION PAYS DE LOIRE SEREL 74, rue du Surmelin 75020 Paris / France Our reference: S 3257 patent claims 1. Pseudo-random generator through which a binary input number or a binary input word G is converted into an output word G ¹ , the conversion occurring with each clock pulse H and the output word a certain number X of clock pulses occurring after the input word has been applied, thereby characterized in that it contains means for changing the number X of clock pulses which separate the input word from the output word as a function of the value of the input word G. 10 2. Pseudo-random generator for converting a binary input number or a binary input word G into an output word G ¹ , the conversion taking place with each clock pulse H and the output word occurring a certain number X of clock pulses after the application of the input word, characterized in that the number of binary digits in the output word depends on the value of the input word. HD / bl 3. Pseudo-random generator according to claim 1, characterized in that that after a first time t, whose Value is determined by the value of the input word G, the output word of the generator is used to form a new input word which _{defines a new time t D} , the output word occurring after a certain number A of such interruptions in the output sequence. 4. Generator according to claim 3, characterized in that the number A of interruptions in the sequence is variable depends on the value of the input word G-. 5. Pseudo-random generator according to one of the preceding claims, characterized in that it comprises, in a manner known per se, a shift register (10) with N cells (10 ..... 10) and an exclusive-OR gate circuit (13 ) whose first input (13) is connected to the output of a cell (10) of an ordinal number having an intermediate value, while the second input (13 ₂ ) is connected to the output (12) of the first cell and the output (13 ~) this gate circuit is connected to the input of the first cell (1O ₁ ). 25th 6. Pseudo-random generator according to claim 5, characterized in that that the input word and the output word are parallel words. 30th 35