DE3513916C2 - Pseudo-random generator - Google Patents

Description

The invention relates to a pseudo-random generator according to the preamble of claims 1 and 2.

Such a device places one placed at its entrance Binary number to another binary number. The number of digits of the starting number or the starting word is in general great. Such a generator, for example used for coding purposes. The size of the number of binary digits unauthorized decoding of the output word is difficult.

The law for converting the input word into an output word is not completely random, however, because if if this were the case, there could be no reproducible implementation, and decoding would be impossible. Without knowing the Implementation law, however, it appears that this is purely coincidental.  

Such a generator is generally made up of a shift register and an exclusive OR gate circuit formed Output connected to the serial input of the register is. The first input of the exclusive OR gate circuit receives the signal from a cell of the register with an atomic number of certain intermediate value, while the second input this gate circuit connected to the output of the same register is. The number or word becomes common on the input side entered in parallel in the register, i.e. simultaneously in all memory cells. Operation of the register is controlled by a clock signal. With every clock pulse the output signal of the exclusive OR gate circuit in the first cell of the register is fed, and the content of each Cell is moved towards the exit so that the content of the Cell with the ordinal number m before the clock pulse to the content the memory cell with the atomic number m-1.

The output number or the output word is after a certain X number of clock pulses received, this Number X specified for a given pseudo-random generator and is constant. The output word is either through the content of the various shift register cells at the end this X clock pulses or by the content of a fraction of these cells, or by a serial sequence of binary digits at the output of the shift register. In the latter Trap is the duration of the consequence, d. H. the number of binary digits of the output signal, by building the pseudo Random generator set.

The output word depends on three parameters: the input word, the intermediate ranking of that memory cell with which connects the first input of the exclusive OR gate and the number X of clock pulses that make up the input word separate from the source word. Since the last two Parameters are constant, there is still a risk that an unauthorized person detects these parameters.  

In a pseudo-random generator known from GB 21 00 485 A. of the type mentioned is one of one Shift register applied to the clock signal at the input the output signal of an exclusive OR gate loaded, the Inputs in turn with different outputs of the shift register are connected. The content of the shift register is loaded into an output register, which depends can be read from a cycle determined by a divider is whose input signal is through that for the shift register certain clock signal is formed.

Another pseudo-random generator with a shift register and an exclusive OR gate assigned to it is off GB 21 17 149 A known. The outputs of the shift register are further exclusive OR gates connected via the further, corresponding data lines assigned and for an exclusive OR gate controlled a multiplex operation become.

The aim of the invention is to provide a pseudo-random generator to create the type mentioned, the output signals in even more protected against unauthorized decoding are.

The task is performed by the in the characterizing part of claim 1 or 2 specified features solved.

Accordingly, the output word appears in the first embodiment only if after creating the input word a time t has elapsed from the input word depends. In this way, another will be implemented Parameter taken into account by which the decoding is additional is difficult.

In the other embodiment, the number of binary digits depends of the output word from the value of the input word, also a combination with the first embodiment is possible.  

By the duration t depending on the value of the input word a fixed value memory is used, for example, in which the values for the time period t are stored are which of the memory depending on the applied to it Input words are given. The Amendment Act can also be done by programming using a microprocessor to be created.

If the output word is in parallel and has the same number of binary digits as the input word, the change in the duration t depending on the value of the input word can be made even more complex in the following way: at the end of a first duration t 1, which depends on the value of the input word G. , the output word G₁ is regarded as a new input word which defines a new value t₂. Such an interruption of the sequence occurs A times, this number A preferably depending on the value of the input word. The starting word G _A is the one that appears after A cycles or interruptions of sequences.

Further advantageous design variants are in the subclaims specified the invention.  

Further advantages of the invention result from the following description of exemplary embodiments and from the drawing to which reference is made. In the drawing shows:

Fig. 1 is a block diagram of a pseudo-random generator;

Fig. 2 is a representation of the output word of such a pseudo-random generator; and

Fig. 3 is a flowchart showing the control of the pseudo-random generator of Fig. 1.

A pseudo-random generator contains a shift register 10 , which consists of N cells, which are by bistable flip-flops 10 ₁, 10 ₂. . . 10 _{N are} formed, which are in series. The serial input is formed by the input of the first multivibrator 10 1, while the serial output is formed by the output 12 _{N of} the last multivibrator 10 _N.

Each flip-flop 10 ₁, 10 ₂. . . 10 _N contains an additional input 11 ₁, 11 ₂. . . 11 _N , to which a binary digit of a parallel input word is applied.

An output of an intermediate flip-flop 10 _n (n <N) is connected to the first input 13 ₁ of a gate circuit 13 of the "exclusive OR" type, the second input 13 ₂ of which is connected to the output 12 _{N of} the flip-flop 10 _N. The output 13 ₃ of the gate circuit 13 is connected to the serial input of the flip-flop 10 ₁. The truth table of the exclusive OR gate circuit is as follows:

The operation of the pseudo-random generator is controlled by clock pulses H which 10 ₁ to the corresponding inputs of the flip-flops. . . 10 _{N are} created.

A conventional pseudo-random generator works as follows: to the parallel inputs 11 ₁. . . 11 _N the binary digits of a number G, which is called the input word, are applied. After the first clock pulse H, the flip-flop 10 ₁ stores the output signal of the gate circuit 13 , the flip-flop 10 ₂ stores the number that was previously in the flip-flop 10 ₁, and in the same way each of the other flip-flops stores the previous content of the previous flip-flop.

The output word appears after a predetermined number X of clock pulses. This example parallel output word is at the outputs 12 ₁, 12 ₂. . . 12 _N tapped. It can also be a serial output word: in this case it is the binary number appearing at output 12 _N from the Xth clock pulse. This serial number has, for example, m binary digits. It is therefore received during m clock pulses.

The output signal is periodic. The period is: P = (2 ^N -1) τ, where τ is the period of the clock signal.

Because of the periodic behavior of the output sequence S, it can be represented by a circle 15 ( FIG. 2). In this circle, point 16 represents the moment when the input word G is fed in, while point 17 is the point in time at which the output word begins to occur, the time interval between points 16 and 17 being the following:

t _R = X · τ

The arc 18 represents the duration of the m bits of the output word if it is serial.

According to a first embodiment of the invention, the number X is not independent of the input word, ie the position of the point 17 changes depending on the value of the input word G. According to a second embodiment of the invention, the number of bits of the output word depends, ie the number m or the length of the arc 18 , from the value of the input word G. The features of the second embodiment can be used in combination with or independently of those of the first.

So that the number X depends on the input word G, for example uses a read-only memory (not shown), in which values for the number X are stored and at its inputs input word G is created. The value for the number X is used a time register or a counter (not shown) load its contents with every clock pulse decreases by one unit and which is the end of the sequence indicates when its content has dropped to zero.

The transformation law for converting the input word G into a time t _R can also be obtained by programming, as will be described with reference to FIG. 3.

In this embodiment, multiple cycles or Interruptions of the sequence or sequence made so the transformation law for the conversion of G into t still becomes more complex. The meaning of the term "interruption the consequence "follows from the following description.

Figure 3 is a flow diagram which forms part of the present description of the invention.

The initialization word G₀ is that which at the inputs 11 ₁. . . 11 _{N is} applied: it is the input word.

The initialization word G₀ is a number A of cycles to be carried out assigned. The implementation can be done using a read-only memory happen or according to a predetermined law, that is calculated by a calculator or microcomputer becomes. The initialization word G₀ also serves to define one Number X of clock pulses, after which an interruption is carried out after the expiry or after its expiration the output word K occurs.

The time

t _R = X (G) · τ

is entered in a time register as the number T. So that this number T is not too small, the bit of the ordinal number Ω of this number T is arbitrarily set to the value 1, so that the time between points 16 and 17 has at least the value 2 ^Ω .

Part 20 on the left in the flowchart of FIG. 3 corresponds to the operation of a conventional pseudo-random generator.

At the end of a first cycle, when the content of the time register has become zero, the time t _{R has} expired and the content of the register into which the number A would be entered is reduced by one unit if this content does not yet correspond to the Has reached zero, the output word G 'is used to define a duration t _R. This process is an interruption of the sequence or sequence.

If, on the other hand, the content of the register for the numbers A has become zero, the sequence or sequence is ended, and forms the content of the various flip-flops the starting word G '.

Claims (6)

1. pseudo-random generator for converting a binary input number or a binary input word (G, G₀) into an output word (G '), the conversion taking place with each clock pulse (H) and the output word (G') a certain number (X ) of clock pulses after application of the input word (G, Glegen) occurs, characterized in that it contains switching means, depending on the number (X) of clock pulses that separate the input word (G, G₀) from the output word (G ′) to change the value of the input word (G, G₀). 2. Pseudo-random generator for converting a binary input number or a binary input word (G, G₀) in one Output word (G '), the implementation with each clock pulse (H) takes place and the output word (G ') a certain number (X) of clock pulses after the input word (G, G₀) occurs, characterized in that it has switching means contains the number of binary digits of the output word (G ′) depending on the value of the input word (G, G₀) to select.   3. pseudo-random generator according to claim 1, characterized in that it is designed such that after a first time (t _R ), the value of which is determined by the value of the input word (G), the output word (G ') of the generator is used to form a new input word (G) which defines a new time (t _R ), the output word (G ') occurring after a certain number (A) of such interruptions in the output sequence. 4. pseudo-random generator according to claim 3, characterized in that the number (A) of interruptions in the output sequence depending on the value of an input word (G₀) is variable. 5. Pseudo-random generator according to one of the preceding claims, characterized in that it has a shift register ( 10 ) with N cells in series ( 10 ₁... 10 _N ) and an exclusive OR gate circuit ( 13 ) contains whose first input ( 13 ₁) is connected to the output of a cell ( 10 _n ) of an atomic number having an intermediate value, while its second input ( 13 ₂) to the output ( 12 _N ) of the last cell ( 10 _N ) and the output ( 13 ₃) is connected to the input of the first cell ( 10 ₁). 6. pseudo-random generator according to claim 5, characterized in that the input word (G, G₀) and the output word (G ′) are bit-parallel words.