GB2115938A - Method of testing printed circuits - Google Patents

Abstract

A method of testing a printed circuit board (1) with the object of detecting small projections of excess conductive material extending from the conductive areas (3). A test printed circuit board (5), which is a mirror image, inverse representation of the printed circuit board (1), but with the conductive areas slightly reduced in size, is brought into face-to-face contact with the printed circuit board (1) so that its conductive areas (6) are in registration with the non-conductive areas (4) of the printed circuit board (1) and a check for contact between the conductive areas (6) (4) is made, at two different voltage levels. <IMAGE>

Description

SPECIFICATION Method of testing printed circuits Background of the invention This invention relates to a method of testing printed circuits.

Printed circuits may sometimes suffer from defects in manufacture. In particular, the conductive areas of a printed circuit may have small projections of excess conductive material which may cause short-circuits. It is therefore desirable to test the circuits before use so as to ensure that these defects are detected.

One known method of testing a printed circuit is to use a so-called bed-of-nails tester, consisting of an array of electrical probes. The probes are pressed against the circuit under test, and various tests can then be carried out to check the electrical continuity between any pair of the probes. However, this method is not suitable for detecting small defects.

The object of the present invention is therefore to provide a novel method of testing a printed circuit which can detect these small defects.

Summary ofthe invention According to the invention, a method of testing a printed circuit includes the steps of; forming a test printed circuit comprising an insulating substrate and a plurality of conductive areas positioned thereon such that when the test printed circuit is aligned in face-to-face relationship with the printed circuit under test the conductive areas correspond in shape and position to, but are slightly smaller than, the intended non-conductive areas of the printed circuit under test; bringing the faces of the aligned printed circuits into contact so that the conductive areas of the test printed crcuit are in registration with the non-conductive areas of the printed circuit under test whereby, if the printed circuit under test is acceptable, there is no contact between the conductive areas of the two printed circuits; and checking for such contact by introducing a voltage difference between the conductive areas of the two printed circuits and observing whether an electric current flows between them.

The invention may for example be used to test a power plane comprising a continuous layer of metal having a pattern of apertures in it. In this case, the test printed circuit would comprise a plurality of separate areas of metal, corresponding to the aper tures in the power plane.

Brief description of the drawings As an example of the invention, a method of testing a power plane for use in a multi-layer printed circuit board will now be described, by way of example, with reference to the accompanying drawing, in which, Figure 1 is a plan view of one corner of a power plane, Figure 2 is a plan view of a corresponding part of a test printed circuit for testing the power plane, and Figure 3 is a sectional scrap view of the test circuit superimposed upon the power plane.

Description ofan embodiment of the invention Referring now to the drawing, a power plane 1 comprises an insulating substrate 2 having a continuous layer of copper 3 on one face.

In the completed circuit board, the power plane is assembled with other planes to form a multi-layer structure. Plated-through holes are then formed through the board, to provide electrical connections between the various planes. These plated-through holes pass through all the planes of the board, including the power plane. Where it is desired that a plated-through hole should not make electrical contact with the power plane, a circular aperture 4 is formed in the copper layer 3 of the power plane 1, this aperture being large enough to allow the plated-through hole to pass through the power plane 1 without touching the copper 3. Typically, the plated-through holes are 0.95 mm (before plating) and the apertures 4 are 1.84 mm in diameter.

These apertures 4 are formed in the copper layer 3 (before assembly of the multi-layer structure) by a conventional masking and etching technique. It is found, however, that because of imperfections in the production process, the edges of the apertures 4 may have small projections of excess copper which, in the completed circuit board, may result in shortcircuits between the copper layer 3 and the platedthrough holes.

It is therefore desirable to test the power plane 1 before incorporating it into the multi-layer assembly, in order to detect these defects.

The power plane 1 is tested using a test printed circuit 5, which is a mirror image, inverse representation of the power plane, having a plurality of separate circular areas 6 of copper in positions corresponding to the apertures 4 in the power plane.

Each of these areas 6 is of the order of 0.2 mm smaller in diameter than the apertures 4. The areas 6 are connected, through the substrate of the test printed circuit 5, by plated-through holes 8, (Figure 3), to external terminals 9 to allow test voltages to be applied to them.

The test procedure is as follows.

As shown in Figure 3, the test printed circuit 5 is brought into contact with the power plane 1, with the circular areas of copper 6 in register with the apertures 4 in the power plane. As the areas of copper 6 are smaller in diameter than the apertures 4, there should be a small clearance between the areas of copper 6 and the copper layer 3 of the power plane 1. A low voltage (typically 42 volts) is then applied between the copper areas 6 of the test printed circuit 5 and the layer of copper 3 of the power plane 1. If the power plane is perfect, there will be no electrical contact between the copper areas 6 and the copper layer 3, and hence no current will flow. However, if there are any projections on the edges of the apertures 4 which touch any of the copper areas 6, a current will flow, indicating a fault.

If the power plane 1 passes this test, a further test is performed using a higher voltage (typically 350 volts). If there are any projections which nearly touch the copper areas 6, the high voltage will cause arcing between the projections and the copper areas, again resulting in a flow of current and indicating a fault.

It will be realised that, although the testing of a power plane has been described, the invention is applicable to any other form of printed circuit where unwanted projections of excess conductive material may be produced during manufacture, the test printed circuit in each case being a mirror image, inverse representation of the printed circuit to be tested but with the conductive areas slightly reduced in size.

The test printed circuit may be manufactured in conventional manner using masking and etching techniques. It has been found convenient to utilise the mask from which the printed circuit to be tested was formed to produce an inverse image from which a further mask may be formed for use in etching the test printed circuit. It will be understood that, in order to produce conductive areas on the test printed circuit which are slightly smaller than the non-conductive areas on the printed circuit to be tested, those parts of the further mask which represent the conductive areas of the test printed circuit, i.e. the opaque portion, will require to be slightly reduced in size.

The reduction of the size of the opaque portions may be carried out using digital thinning techniques as used for thinning characters for character recognition purposes. Thinning techniques are disclosed, for example, in British Patent Specification No.

1,487,920 and U.S. Patent 4,020,463, where the strokes forming characters are thinned to single cell thickness in a number of process steps. However, for the present purpose of reducing the size of the opaque portions, thinning is carried out only until the desired reduction has been obtained.

Claims (3)

1. A method of testing a printed circuit including the steps of; forming a test printed circuit comprising an insulating substrate and a plurality of conductive area positioned thereon such that when the test printed circuit is aligned in face-to-face relationship with the printed circuit under test the conductive areas correspond in shape and position to, but are slightly smaller than, the intended non-conductive areas of the printed circuit under test; bringing the faces of the aligned printed circuits into contact so that the conductive areas of the test printed circuit are in registration with the non-conductive areas of the printed circuit under test whereby, if the printed circuit under test is acceptable, there is no contact between the conductive areas of the two printed circuits; and checking for such contact by introducing a voltage difference between the conductive areas of the two printed circuits and observing whether an electric current flows between them.

2. A method as claimed in Claim 1, in which the printed circuit under test is a power plane including a continuous layer of conductive material having a pattern of circular apertures therein and in which the step of forming the test printed circuit includes; providing on said substrate a pattern of circular areas of conductive material corresponding in position to, but being slightly smaller than, the circular apertures in the conductive layer of the power plane, and forming electrical connections extending through the substrate from the circular areas of conductive material to enable the application of a voltage thereto.

3. A method of testing a printed circuit as hereinbefore described with reference to the accompanying drawing.

3. A method as claimed in Claim 1 or 2, in which the step of checking for contact between the conductive areas of the two printed circuit includes; a first stage in which a first voltage is applied between said conductive areas and a second stage in which a second voltage, of higher value than the first voltage, is subsequently applied therebetween.

4. A method of testing a printed circuit as hereinbefore described with reference to the accompanying drawing.

New claims or amendments to claims filed on 25 Apr 1983 Superseded claims 1-4 New or amended claims:

1. A method of testing a printed circuit including the steps of: forming a test printed circuit comprising an insulating substrate and a plurality of conductive areas positioned thereon such that when the test printed circuit is aligned in face-to-face relationship with the printed circuit under test the conductive areas correspond in shape and position to, but are slightly smaller than, the intended non-conductive areas of the printed circuit under test;; bringing the faces of the aligned printed circuits into contact so that the conductive areas of the test printed circuit are in registration with the nonconductive areas of the printed circuit under test whereby, if the printed circuit under test is acceptable, there is no contact between the conductive areas of the two printed circuits; and checking for such contact by introducing a first voltage difference between the conductive areas of the two printed circuits and observing whether an electric current flows between them and, if no such electric current flows, introducing a second voltage different of higher value than the first voltage difference between the conductive areas and again observing whether an electric current flows between the two printed circuits.

2. A method as claimed in Claim 1, in which the printed circuit under test is a power plane including a continuous layer of conductive material having a pattern of circular apertures therein and in which the step of forming the test printed circuit includes; providing on said substrate a pattern of circular areas of conductive material corresponding in position to, but being slightly smaller than, the circular apertures in the conductive layer of the power plane, and forming electrical connections extending through the substrate from the circular areas of conductive material to enable the application of a voltage thereto.