JPS58216967A - Inspecting instrument for printed circuit board and method for inspecting same - Google Patents
Inspecting instrument for printed circuit board and method for inspecting sameInfo
- Publication number
- JPS58216967A JPS58216967A JP57100167A JP10016782A JPS58216967A JP S58216967 A JPS58216967 A JP S58216967A JP 57100167 A JP57100167 A JP 57100167A JP 10016782 A JP10016782 A JP 10016782A JP S58216967 A JPS58216967 A JP S58216967A
- Authority
- JP
- Japan
- Prior art keywords
- printed wiring
- wiring board
- inspection
- round
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
- G01R31/2805—Bare printed circuit boards
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、導体パターンが形成された印刷配線基板を検
査するための印刷配線基板用検査器および検査方法に関
するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a printed wiring board inspection device and an inspection method for inspecting a printed wiring board on which a conductive pattern is formed.
従来、印刷配線基板の導体パターンの導通・非導通・短
絡検査を行う場合、複数個のテストピンまたはプローブ
テストピンを使用し、各ピンを導体パターンと一体のラ
ウンドに接触させ、２ピン間に電流を印加することによ
り導体パターンの導通・非導通・短絡の各状態を検査し
ていた。Conventionally, when testing conductor patterns on printed wiring boards for continuity, non-continuity, and short circuits, multiple test pins or probe test pins are used, each pin is brought into contact with the conductor pattern in a round, and a The conductive, non-conductive, and short-circuit states of the conductor pattern were inspected by applying current.
従来の方法によると、各ピンに均一な圧力か加わらずに
ピン相互間の接触が生ずるという欠点、ピン先端の摩耗
によりラウンドへの接触が不正確となるという欠点、印
刷配線基板自体のソリによるピンの不接触という欠点、
ラウンドにキズが生ずるという欠点、ピンを有する検査
器（治具）を製作しにくいという欠点、さらに検査時間
が長いという欠点があった。According to the conventional method, the disadvantages are that pressure is not applied uniformly to each pin and contact occurs between the pins, that contact with the round becomes inaccurate due to wear of the pin tips, and that the printed circuit board itself warps. Disadvantages of non-contact pins,
There are disadvantages of scratches on the round, difficulty in manufacturing an inspection device (jig) with pins, and long inspection time.
しかるに、本発明は上述のような欠点を除去するために
、非接触型の印刷配線基板用検査器および検査方法を提
供するもので、以下図面にもとづいて説明する。However, in order to eliminate the above-mentioned drawbacks, the present invention provides a non-contact type printed wiring board inspection device and inspection method, which will be described below with reference to the drawings.
先ず、第１図および第２図においで、（１）は被検査印
刷配線基板で、その表面にはラウンド（２）と導体パタ
ーン（３）とが所望のパターンを以って銅箔などにより
形成されている。（４）は印刷配線基板用検査器で、検
査用印刷配線基板（５）とそれに付着形成された絶縁体
（６）とからなる。この絶縁体（６）の形成にあたって
は、絶縁フィルムを接着しても良く、また絶縁物を塗布
しても良いものである。なお、検査用印刷配線基板（５
）には予め被検査印刷配線板（１）の各ラウンド（２）
に相対応して共通ラウンド（７）と選択ラウンド（８）
、および引出線用の導体パターン（９）が銅箔などによ
り形成されでいる。First, in Figures 1 and 2, (1) is a printed wiring board to be inspected, and on the surface thereof, rounds (2) and conductor patterns (3) are formed in a desired pattern using copper foil or the like. It is formed. Reference numeral (4) denotes a printed wiring board inspection device, which consists of a printed wiring board for inspection (5) and an insulator (6) attached thereto. In forming this insulator (6), an insulating film may be adhered or an insulating material may be applied. In addition, a printed wiring board for inspection (5
) are each round (2) of the printed wiring board to be inspected (1) in advance.
Common round (7) and selection round (8) correspond to
, and a conductor pattern (9) for a leader line are formed of copper foil or the like.
ここで、絶縁体（６）として膜厚２５〔μｍ〕のマイラ
フィルムを使用し、ラウンド（２）、（７）、（８）の
径を２〔７φ〕とし、印刷配線基板用検査器（４）を第
２図に示すように被検査印刷配線基板（１）に接触させ
ると、ラウンド（２）と（７ンとの間およびラウンド（
２）と（８）との間の静電容量Ｃ１と０２はそれぞれ５
１：ｐＦ）となる。それゆえ、ＣＩと０２ の直列静
電容量Ｃは２．５ＣｐＦ：ｌとなる。Here, a Mylar film with a film thickness of 25 [μm] is used as the insulator (6), the diameter of the rounds (2), (7), and (8) is 2 [7φ], and the printed wiring board inspection device ( 4) is brought into contact with the printed wiring board to be inspected (1) as shown in Figure 2.
The capacitances C1 and 02 between 2) and (8) are 5, respectively.
1:pF). Therefore, the series capacitance C between CI and 02 is 2.5 CpF:l.
次に、印刷配線基板用検査器（４）による被検査印刷配
線基板（１）の導体パターン（３）の導通・非導通・短
絡検査についで、第３図乃至第５図にもとづいて説明す
る。Next, the conduction/non-continuity/short-circuit inspection of the conductor pattern (3) of the printed wiring board to be inspected (1) using the printed wiring board tester (4) will be explained based on FIGS. 3 to 5. .
パルス発生器００）より第４図に示すようなパルスを発
生させ、このパルスをいずれかの選択ラウンド（８）に
印加すると、この人力パルスは選択ラウンド（８）とラ
ウンド（２）との間の静電結合Ｃ２、導体パターン（３
）、ラウンド（２）と共通ラウンド（７）との間の静電
結合０． を介して共通ラウンド（７）に出力される
。この出力パルスを充放電回路αυに入力するとＡ点の
信号波形は第５図へのようになり、さらに誘導ノイズを
打消すために低域フィルタ（１２）に通すと、Ｂ点の信
号波形は第５図Ｂのようになる。引続き、増幅器（１３
を介し、第５図Ｃに示す分布静電容量から派生する信号
を分離するために、比較器０４）に入力しここでレベル
シフトする。次いで、判定器αυにて入力信号を判定し
、その結果を表示器α６）により表示する０判定器αυ
とパルス発生器σ０は同期信号発生器αηからの同期信
号に同期しているので、導通・非導通のチャンネルは容
易に識別検査できる。When a pulse as shown in Fig. 4 is generated from the pulse generator 00) and this pulse is applied to any selection round (8), this manual pulse is generated between the selection round (8) and the round (2). capacitive coupling C2, conductor pattern (3
), the capacitive coupling between round (2) and common round (7) 0. is output to the common round (7) via. When this output pulse is input to the charging/discharging circuit αυ, the signal waveform at point A becomes as shown in Figure 5. Furthermore, when it is passed through a low-pass filter (12) to cancel the induced noise, the signal waveform at point B becomes The result will be as shown in Figure 5B. Next, the amplifier (13
is input to a comparator 04) where it is level shifted in order to separate the signal derived from the distributed capacitance shown in FIG. 5C. Next, the input signal is determined by the determiner αυ, and the result is displayed on the display device α6).
Since the pulse generator σ0 and the pulse generator σ0 are synchronized with the synchronizing signal from the synchronizing signal generator αη, conducting and non-conducting channels can be easily identified and tested.
また、導体パターン（３）の短絡についでは、信号波形
Ｂの振幅が大きくなるので、比較器αＢにより基準電圧
と比較し、判定器（１９にで判定し、表示器（Ｌ６）に
てその結果を表示する。判定器α９は同様に同期信号発
生器αηにより同期される。In addition, in the case of a short circuit in the conductor pattern (3), since the amplitude of the signal waveform B becomes large, it is compared with the reference voltage by the comparator αB, judged by the judge (19), and the result is shown on the display (L6). The determiner α9 is similarly synchronized by the synchronization signal generator αη.
ところで、第６図に示すように、被検査印刷配線基板（
１）がスルーホール３Ｑを有する両面印刷配線基板の場
合には、印刷配線基板用検査器（４）を２個使用し、そ
れぞれの面に接触させることにより検査することができ
る。この場合、一方の印刷配線基板用検査器（４ａ）の
ラウンド（８）にパルスを印加し、他方の印刷配線基板
用検査器（４ｂ）のラウンド（８）から出力パルスを得
る。By the way, as shown in FIG. 6, the printed wiring board to be inspected (
When 1) is a double-sided printed wiring board having through holes 3Q, the inspection can be performed by using two printed wiring board inspection devices (4) and bringing them into contact with each surface. In this case, a pulse is applied to the round (8) of one printed wiring board tester (4a), and an output pulse is obtained from the round (8) of the other printed wiring board tester (4b).
以上にで述べたように、本発明に係る印刷配線基板用検
査器は静電結合を利用した非接触型の検査器であるため
、ラウンドにキズを生じないとい査印刷配線基板のパタ
ち作成と同時に製作でき安価であるという利点、検査時
間を短くすることができるという利点を奏するものであ
る。As mentioned above, since the printed wiring board inspection device according to the present invention is a non-contact type inspection device that utilizes capacitive coupling, it is possible to inspect and create printed wiring board patterns without causing scratches on the round. At the same time, it has the advantage that it can be manufactured at low cost and that the inspection time can be shortened.
図面はいずれも本発明を説明するもので、第１図は本発
明の一実施例を示す斜視図、第２図は本発明における一
実施例の断面図、第３図は検査用の電気回路を示すブロ
ック図、第４回はパルス波形図、第５図は第３図におけ
る要部の信号波形図、第６図は本発明の他の一実施例を
示す断面図である。
図中、（１）・・・被検査印刷配線基板、（４）・・・
印刷配線基板用検査器、（５）・・・検査用印刷配線基
板、（６）・・・絶縁体、Ｑ、０）＝パルス発生器、（
１１）・・・充放電回路、（１岬・・低域フィルタ、α
３・・・増幅器、α小、ＯＢ・・・比較器、０５、σ臼
・・・判定器、０．６）・・・表示器、０７）・・・同
期信号発生器、特許出願人 エルナー株式会社
３９５−The drawings are for explaining the present invention. Figure 1 is a perspective view showing an embodiment of the invention, Figure 2 is a sectional view of an embodiment of the invention, and Figure 3 is an electric circuit for inspection. The fourth is a pulse waveform diagram, FIG. 5 is a signal waveform diagram of the main part in FIG. 3, and FIG. 6 is a sectional view showing another embodiment of the present invention. In the figure, (1)...Printed wiring board to be inspected, (4)...
Inspection device for printed wiring board, (5)... Printed wiring board for inspection, (6)... Insulator, Q, 0) = Pulse generator, (
11)...Charging/discharging circuit, (1 Misaki...Low pass filter, α
3... Amplifier, α small, OB... Comparator, 05, σ mill... Determiner, 0.6)... Display, 07)... Synchronization signal generator, Patent applicant Elna 395- Co., Ltd.
Claims (1)
応するように形成されたラウンドを有する検査用印刷配
線基板と、検査用印刷配線基板に付着形成された絶縁体
とからなる印刷配線基板用検査器。 （２、特許請求の範囲（１）において、検査用印刷配線
基板に形成されたラウンドは共通ラウンドと選択ラウウ
ドとからなることを特徴とした印刷配線基板用検査器。 （３） 被検査印刷配線基板に形成されたラウンドに
相対応するように形成されたラウンドを有する検査用印
刷配線基板と、検査用印刷配線基板に付着形成された絶
縁体とからなる印刷配線基板用検査器を被検査印刷配線
基板に接触させ、かつ検査用印刷配線基板の一方のラウ
ンドにパルスを印加し、他方のラウンドから出力パルス
を得、この出力パルスを判定するようにした罹刷配線基
板の検査方法。 （４）特許請求の範囲（３）において、スルーホールを
有する被検査両面印刷配線基板の両面にそれぞれ印刷配
線基板用検査器を接触させ、一方の印刷配線基板用検査
器のラウンドにパルスを印加し、他方の印刷配線基板用
検査器のラウンドから出力パルスを得、この出力パルス
を判定するようにした印刷配線基板の検査方法。[Claims] (1) A printed wiring board for inspection having rounds formed to correspond to the rounds formed on the printed wiring board to be inspected, and an insulator attached and formed on the printed wiring board for inspection. A printed wiring board inspection device consisting of. (2. In claim (1), the printed wiring board inspection device is characterized in that the rounds formed on the printed wiring board for inspection consist of a common round and a selection round. (3) Printed wiring to be inspected A printed wiring board tester consisting of a printed wiring board for testing having rounds formed to correspond to the rounds formed on the board and an insulator attached to the printed wiring board for testing is used to print the printed wiring board to be tested. A method for inspecting a damaged printed wiring board, which is brought into contact with a printed wiring board, applies a pulse to one round of the printed wiring board for inspection, obtains an output pulse from the other round, and judges this output pulse. (4) ) In claim (3), a printed wiring board tester is brought into contact with both sides of a double-sided printed wiring board to be inspected having through holes, and a pulse is applied to the round of one of the printed wiring board testers, A printed wiring board inspection method in which an output pulse is obtained from the round of the other printed wiring board inspection device and this output pulse is determined.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57100167A JPS58216967A (en) | 1982-06-10 | 1982-06-10 | Inspecting instrument for printed circuit board and method for inspecting same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57100167A JPS58216967A (en) | 1982-06-10 | 1982-06-10 | Inspecting instrument for printed circuit board and method for inspecting same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58216967A true JPS58216967A (en) | 1983-12-16 |
| JPH0343592B2 JPH0343592B2 (en) | 1991-07-03 |
Family
ID=14266754
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57100167A Granted JPS58216967A (en) | 1982-06-10 | 1982-06-10 | Inspecting instrument for printed circuit board and method for inspecting same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58216967A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6614250B1 (en) * | 1998-08-07 | 2003-09-02 | Oht Inc. | Sensor probe for use in board inspection and manufacturing method thereof |
| US6933740B2 (en) | 2000-05-17 | 2005-08-23 | Oht, Inc. | Electronic circuit inspection sensor and inspection system using same |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS48100659A (en) * | 1972-04-01 | 1973-12-19 |
-
1982
- 1982-06-10 JP JP57100167A patent/JPS58216967A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS48100659A (en) * | 1972-04-01 | 1973-12-19 |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6614250B1 (en) * | 1998-08-07 | 2003-09-02 | Oht Inc. | Sensor probe for use in board inspection and manufacturing method thereof |
| US6967498B2 (en) | 1998-08-07 | 2005-11-22 | Oht Inc. | Apparatus and method for inspecting electronic circuits |
| US7239127B2 (en) | 1998-08-07 | 2007-07-03 | Oht Inc. | Apparatus and method for inspecting electronic circuits |
| US6933740B2 (en) | 2000-05-17 | 2005-08-23 | Oht, Inc. | Electronic circuit inspection sensor and inspection system using same |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0343592B2 (en) | 1991-07-03 |
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