GB2115586A

GB2115586A - Alignment and merge operation on resultant long operands

Info

Publication number: GB2115586A
Application number: GB08235229A
Authority: GB
Inventors: Richard T Flynn; Jerry L Kindell
Original assignee: Honeywell Information Systems Italia SpA; Honeywell Information Systems Inc
Current assignee: Bull HN Information Systems Italia SpA; Bull HN Information Systems Inc
Priority date: 1979-01-02
Filing date: 1982-12-10
Publication date: 1983-09-07
Also published as: GB2117940A; GB2116756B; GB2041590B; GB2117940B; GB2117941A; GB2115586B; CA1145054A; GB2116756A; GB2117541B; FR2445986A1; GB2117541A; GB2041590A; FR2445986B1; GB2117941B; DE3000045A1

Abstract

A microprogrammed data processing system wherein the throughput of the system is increased during the processing of decimal numeric instructions by apparatus which anticipates and receives a long operand, greater than a predetermined number of words, which is the result of the prescribed calculation, assembles the resultant operand in accordance with information contained in an instruction descriptor respecting said operand, and transfers the resultant operand to a cache memory. An execution 714 is coupled to the decimal unit 730 and responds to microwords to receive aligned operands from the decimal unit, and performs the required decimal numeric operation. The decimal unit provides start write and send data signals in response to which the execution control unit 701 reads out the appropriate microword commands from the control store 701-2. <IMAGE>

Description

1 GB 2 115 586 A 1

SPECIFICATION Alignment and merge operations on resultant long operands

This invention relates generally to the processing of decimal numerical operands by a data processing system.

Data processing systems process data stored in memory generally in the form of decimal digits. 5 Computer instructions are also stored in memory. Some of the instructions when processed by the data processing system result in arithmetic operations being performed on the decimal digits. For example, a decimal numeric instruction may be processed by the computing system to add one set of decimal digits-operand 1, from one group of memory locations to another set of decimal digits from another group of memory locations-operand 2, and place the result-operand 3, into a third group of memory 10 locations.

Descriptors associated with the instruction define the characteristics of each of the operands. Each operand may be a floating point number or a scaled number. Each decimal digit may have 4 bits or 9 bits. Such characteristics are defined by a descriptor which also defines the number of decimal digits in the operand, the location of the decimal point, i.e. the scale factor, the character position within a word of the most significant character of the operand, and the location of the sign if the operand contains a sign, either in the most significant character position-leading sign, or the least significant character position in a scaled operand-trailing sign. The instruction will indicate if the operand is ASCII or EBCDIC and if the sign is part of an overpunched character.

Prior art hardware systems, for example, the Honeywell 6000 family of computers stored 20 operand 3 in the bank of registers using combination logic to set up the pointers to identify the number and positi ons of leading and trailing zones as well as the character size K bits or 9 bits) within each word and the position of the sign (trailing or leading). Microprogrammed systems were developed to perform the same functions as the hardware systems (such as the Honeywell 6000) at a reduced product cost. However, in certain areas such as during the processing of decimal numeric instructions a 25 considerable number of firmware steps were required to condition the resultant operand 3 for storage in memory, thereby reducing the system throughput during the processing of decimal numerical instructions. This invention has as its object the processing of operand 3 in accordance with its descriptor for storage in memory. 30 Accordingly one aspect of the product invention is to provide a microprogrammed data processing system with improved throughput when processing decimal numeric instructions. This improvement is provided when aligning and merging a long resultant operand during the processing of such instructions. An operand is defined herein as a long operand when it has between 16 and 64 characters. 35 Accordingly the invention provides a data processing system comprising: a cache memory for storing operands and instructions, each instruction including an operation code portion and also including descriptor information for describing characteristics of said operands; an execution control unit including means for storing microword signals, said data processing system being responsive to said microword signals for executing operations specified by said instructions; a control unit for generating control state signals coupled to said cache and to said execution control unit, said cache and said control unit being responsive to said microword signals for transferring one of said instructions having descriptor information specifying a decimal numeric operation to said control unit from said cache, said control unit being responsive to said microword signals for transferring said operation code portion of said one of said instructions to said execution control unit, said execution control unit including means for selecting a series of said microword signals in response to said operations code portion, said execution control unit being responsive to said series of said microword signals for executing the decimal numeric operation specified in the said instruction; a decimal unit coupled to said control unit and said cache and including means for storing said 50 descriptor information in response to said series of said microword signals, said decimal unit being responsive to signals indicative of said descriptor information to determine the lengths of said operands, including means for receiving and aligning said operands when said operands are transferred to said decimal unit from said cache; and an execution unit coupled to said decimal unit and, in response to said series of microword 55 signals, receiving said aligned operands from said decimal unit and performing said decimal numeric operation thereby generating a resultant long operand for transfer to said decimal unit, said decimal unit being responsive to said series of microword signals for generating start write signals and send data signals, said execution control unit having address generating means responsive to said start write signals and said send data signals for reading out said series of microword signals from said microword 60 storing means, said data processing system being responsive to said series of microword signals for storing said long operand in said cache.

A preferred embodiment of the present invention described in detail hereinafter includes a data processing system including a cache memory which stores instructions including descriptors and GB 2 115 586 A 2 1 operands, a control unit which receives the instructions and descriptors from cache, and an execution control unit which receives the operation code position of the instructions from the control unit to generate a series of microwords which enables the data processing system to execute the instructions. The system also includes a decimal unit which is operative during the processing of decimal memory instructions, and under microprogram control receives the descriptors and operands from cache and aligns the operands by interpreting the descriptor fields defining the operand, and an execution unit which receives the aligned operands from the decimal unit and performs the decimal arithmetic function specified by the instruction.

As disclosed, for example, in relation to application 7943118 filed on the 14th December 1979 and which discloses the identical apparatus, two long or short operands described by their respective 10 descriptors are aligned and transferred to an execution unit wherein the two operands are processed in accordance with a decimal numeric instruction to produce a resultant long or short operand.

The alignment and merging of a resultant long operand received by the decimal unit from the execution unit is described hereinafter, it being processed in the decimal unit in accordance with a descriptor stored in the decimal unit describing the characteristics of the resultant operand as it is to be 15 stored in cache memory.

The decimal unit responds to a firmware command by counting the number of significant words of the resultant operand and storing that count in an RWPC receive word count register. The decimal unit also calculates from the descriptor information the number of words the decimal unit will send to the cache and store the value in an RRWC send word register.

The long operand store operation starts with the execution control unit reading out of the execution control store, a microword which includes signals coded to specify a "store operand in the decimal unit operation". On the next cycle the execution control store reads a microword which results in the system testing the decimal unit start write signal line. The DSTRT- WRT start write signal line from register and switch control 730-91 indicates the relationship between the counts in the RWPC 25 register 730-84 and the RRWC register 730-88. The start write signal line is at logical ZERO when the count in the RWPC register is greater than the count in the RRWC register indicting that the number of operand words in the execution unit is greater than the number of operand words defined by the descriptor. This is normal since the execution unit stores 64 decimal digits or 8 words whereas the descriptor defining a long operand would indicate from three to eight words for the long operand. The 30 decimal unit forces words containing zeros to be processed by the decimal unit meanwhile decrementing the RWPC register until the RWPC register count equals the RRWC register count. This forces the start write signal line to logical ONE provided that a complete operand word can be assembled in the decimal unit. If a complete word cannot be assembled in the decimal unit, then the firmware initiates the transfer of the next word from the execution unit to the decimal unit, and on the 35 cycle that a complete word is assembled in the decimal unit, the start write signal line is forced to logical ONE and the operand word is aligned, merged and transferred to cache.

A DSEND-DATA send data signal is forced to logical ONE when the decimal unit requires the next word from the execution unit. If the descriptor describes a 9-bit decimal digit resultant operand for storage in cache, then the send data signal is at logical ONE on alternate cycles since two operand 40 words are generated in the decimal unit to each word received from the execution unit.

The decimal unit calculates the position of the most significant decimal digit within the operand word of the resultant operand received from the execution unit. The decimal unit also calculates the position of the most significant decimal digit within the operand word as it is to be stored in cache.

These calculations are combined to determine the number of decimal digits the resultant operand received from the execution unit is to be shifted in the decimal unit. This shift is stored in an, RDSC register 730-58. The direction of shift controls the sequence of the store operation. For a positive shift, RDSCO at logical ZERO, the sequence is as described supra. For a zerc shift or a negative shift, RDSCO at logical ONE, the above sequence must be delayed a cycle until both the most significant data word and the data word following the most significant data word are both stored in the decimal 50 unit.

The store operation is completed when the number of operand words specified by the descriptor is transferred from the execution unit, through the decimal unit where it is aligned and merged, and written into cache.

Other features of the apparatus described herein form the subject matter of copending applications divided out of the aforesaid application 7943118.

The above described embodiment is now described in further detail with reference to the accompanying drawings, wherein.

Figure 1 is an overall block diagram of the host processor. The cache unit and system integration unit are shown connected to the host processor.

Figure 2 is a block diagram of the execution unit and a portion of the character unit of the host processor.

Figure 3 is a detailed block diagram of the decimal unit.

Figure 4 is an overall block diagram of the decimal unit.

Figure 5 shows the instruction and descriptor formats for two decimal numeric instructions. 65 i 3 GB 2 115 586 A 3 Figure 6 is a logic diagram of the leading zero count circuits. Figure 7 is a logic diagram of the effective digit circuits. Figure 8 is a diagram of the vector branch logic.

General description of processor 700-Figure 1

Referring to Figure 1, it is seen that a host processor 700 includes an execution control unit 701, a control unit 704, an execution unit 714, a character unit 720, an auxiliary arithmetic and control unit (AACU) 722, a multiply-divide unit 728, and a decimal unit 730 which are interconnected as shown.

Additionally, the control unit 704 has a number of interconnections to the cache 750 as shown.

The execution control unit 701 includes an execution control store address preparation and branch unit 701 -1, and an execution control store 701-2. The store 701-2 and unit 710-1 are 10 interconnected via buses 701-3 and 701-6 as shown.

The control unit 704 includes a control logic unit 704-1, a control store 704-2, an address preparation unit 704-3, data and address output circuit 704-4, an XAQ register section 704-5 which interconnect as shown.

The control unit 704 provides the necessary control for performing address preparation operations, instruction fetch I ng/execution operations and the sequential control for various cycles of operation and/or machine states. The control is generated by logic circuits of block 704-1 and by the execution control unit 701 for the various portions of the control unit 704.

The XAQ register section 704-5 includes a number of program visible registers such as index registers, an accumUlator register, and quotient register. Other program visible registers such as the 20 instruction counter and address registers are Included within the address preparation unit 704-3.

As seen from Figure 1, the section 704-5 receives signals from unit 704-3 representative of the contents of the instruction counter via lines RIC 00-17. Also, lines ZRESA 00-35 apply output signals from the execution unit 714 corresponding to the results of operations performed upon various operands. The section 704-5 also receives an output signal from the auxiliary arithmetic and control 25 unit via lines RAAUO-8 The section 704-5 provides signals prep resentaitive of the contents of one of the registers included within the section as an input to the address preparation unit 704-3 via the lines ZXO-20 and ZXA 24-35. The address preparation unit 704-3 forwards the information through a switch to the execution unit 714 via the lines ZDO 0-35. Similarly, the contents of certain ones of the registers 30 contained within section 704-5 can be transferred to the execution unit 714 via the lines ZEB 00 35. Lastly, the contents of selected ones of these registers can be transferred from section 704-5 to the multiply/divide unit 728 via the lines ZAQ 00-35.

The address preparation unit 704-3 generates addresses from the contents of various registers contained therein and applies the resultant logical, effective and/or absolute addresses for distribution 35 to other units along the lines ASFA 00-35. The address preparation unit 704-3 receives the results of operations performed on a pair of operands by the execution unit 714 via the lines ZRESB 00-35.

The unit 704-3 receives signals representative of the contents of a pair of base pointer registers from the control logic unit 701 via the lines RBASA and RBASAO-1. Outputs from the multiply/divide unit 728 are applied to the address preparation unit 704-3. Lastly, the contents of a secondary instruction 40 register (RSIR) are applied as input to the unit 704-3 via the lines RSIR 00-35.

The data and address output circuits 704--4 generate the cache memory address signals which it applies to the cache unit 750 via the lines RADO/ZADO 00-35. These address signals correspond to the signals applied to one of the sets of input lines ZDI 00-35, ASFA 00- 35 and ZRESB 00-35 selected by switches included within the circuits of block 704-4. Also, a word address signals are 45 applied via the lines ASFA 32-33.

The control logic unit 704-1 provides data paths which have an interface with various units included within the cache unit 705. The lines ZIB 00-35 provide an interface with an instruction buffer included within the cache 750. The lines ZDI 00-35 are used to transfer data signals from the cache 750 to the control logic unit 704-1.

As seen from Figure 1, the control logic unit 704-1 provides a number of groups of output signals. These output signals include the contents of certain registers, as, for example, a basic instruction register (RBIR) whose contents are applied as an input to control store 704-2 via the lines RBIR 18-27. The control logic unit 704-1 receives certain control signals read out from control store 704-2 via the lines CCSDO 13-31.

The control logic unit 704-1 also includes a secondary instruction register (RSIR) which is loaded in parallel with the basic instruction register at the start of processing an instruction. The contents of the secondary instruction register RSIR 00-35, as previously mentioned, are applied as inputs to the address preparation unit 704-3. Additionally, a portion of the contents of the secondary instruction register are applied as inputs to the auxiliary arithmetic control unit 722 via the lines RSIR 60 1-9 and 24-35, and to the decimal unit 730 via the lines RSIR 21-35.

The control store 704-2 as explained herein provides for an initial decoding of program instruction op-codes and therefore is arranged to include a number of storage locations (1024), one for each possible instruction op-code.

4 GB 2 115 586 A 4 As mentioned, signals applied to lines RBIR 18-27 are applied as inputs to control store 7042. These signals select one of the possible 1024 storage locations. The contents of the selected storage location are applied to the lines CCSDO 13-31 and to CCSDO 00-12 as shown in Figure 1. The signals supplied to lines CCSDO 00-12 correspond to address signals which are used to address 5 the execution control unit 701 as explained herein.

The execution unit 714 provides for instruction execution wherein unit 714 performs arithmetic and/or shift operations upon operands selected from the various inputs. The results of such operations are applied to selected outputs. The execution unit 714 receives data from a data input bus which corresponds to lines RDI 00-35 which have as their source the control logic unit 704-1. The contents of the accumulator and quotient registers included within the section 704-6 are applied to 10 the execution unit 714 via the lines ZEB 00-35 as mentioned previously. The signals applied to the input bus lines ZDO 00-35 from the address preparation unit 704-3 are applied via switches included within the execution unit 714 as output signals to the lines ZRESA 00-35 and ZRESB 00 35, as shown in Figure 1. Additionally, execution unit 714 receives a set of scratch pad address signals from the auxiliary arithmetic and control unit 722 applied via the lines ZRESPA 00-06. Additionally, the unit 722 also provides shift information to the unit 714 via the lines ZRSC 00-35.

The character unit 720 is used to execute character type instructions which require such operations as translation and editing of data fields. As explained herein, these types of instructions are referred to as extended instruction set (EIS) instructions. Such instructions which the character unit 720 executes include the move, scan, compare type instructions. Signals representative of operands 20 are applied via lines ZRESA 00-35. Information as to the type of character position within a word and the number of bits is applied to the character unit 720 via the input lines ZOB 00-07.

Information representative of the results of certain data operations is applied to the unit 722 via the lines ZOC 00-08. Such information includes exponent data and data in hexadecimal form. The character unit 720 applies output operand data and control information to the unit 722, the unit 730 25 and the unit 728 via the lines RCHU 00-35.

The auxiliary arithmetic and control unit 722 performs arithmetic operations upon control information such as exponents used in floating point operations, calculates operand lengths and pointers and generates count information. The results of these operations are applied to execution unit 714 via the lines ZRSPA 00-06 and lines ZRSC 00-05 as mentioned previously. Information signals 30 corresponding to characters such as 9-bit characters, 4-bit characters, decimal data converted from input hexadecimal data, quotient information and sign information are applied to section 704-5 via the lines RAAU 00-08.

As seen from Figure 1, the unit 722 receives a number of inputs. Character pointer information is applied via the lines ASFA 33-36. EIS numeric scale factor information are applied to the unit 722 via 35 the lines RSIR 24-35. Other signals relating to fetching of specific instructions are applied via the lines RSIR 01 -09. Exponent signals for floating point data are applied to the unit 722 via the lines ZOC 00-08 while floating point exponent data signals from unit 704-1 are applied via the lines RDI 00--08. Shift count information signals for certain instructions (e.g. binary shift instructions) are applied to the unit via the lines RDI 11-17. As concerns the input signals applied to the lines RCHU 40 00-35, lines 24-35 apply signals corresponding to the length of EIS instruction fields while 18-23 apply address modification signals to the unit 722.

The multiply/divide unit 728 provides for high-speed execution of multiply and divide instructions. This unit may be considered conventional in design and may take the form of the multiply unit described in U.S. Patent 4,041,292 which is assigned to the same assignee as named herein. The unit 728 as seen from Figure 1 receives multiplier dividend and divisor input signals via the lines RCHU 00-35. The multiplicand input signal from register section 704-5 are applied via the lines ZAQ 00 35. The results of the calculations performed by the unit 728 are applied as;output signals to the lines ZMD 00-35.

The decimal unit 730 is operative under firmware control during the processing of decimal numeric instructions. The instruction format and its related descriptor words are described in greater detail with reference to Figure 5. The instruction word and the descriptor word information received by the decimal unit 730 via lines RSIR 21-35 and ASFA 33-36. They condition the decimal unit 730 to receive the operand described by the descriptor word from cache 750 via line Z_DI 0-35. The decimal unit 730 strips the sign character and exponent characters from the operand word, packs the data into 55 up to eight 4-bit characters per word, stores the data into 32-bit words, aligns and transfers the data words to the execution unit 714 via lines RDOD 00-35, ZMD 00-35 and ZDO 00-35. Data words stored in cache include up to four 9-bit characters of eight 4-bit characters in a 36 bit word. The 9-bit character includes five zone bits and four data bits. The zone bits are stripped from the 9-bit character and the remaining data bits are packed into a 32-bit register which may contain up to two cache data 60 words made up of 9-bit characters or one cache data word made up of 4-bit characters. The packed data words of the operands are assembled in the execution unit 714 and processed in accordance with the decimal numeric instruction. The operand representing the desired result of the numeric instruction is transferred to the decimal unit 730 via lines ZRESA 00-35 to the character unit 720 and then to the decimal unit 730 via lines RCHU 4-35. There, the operand is processed in accordance with the coded 65 !1,1 GB 2 115 586 A 5 information in a descriptor word. The operand is unpacked, required signs and exponents added, via lines ZADSP 3-11, EBCIDIC or ASC1 1 zone characters are added if 9-bit decimal characters are indicated by the descriptor word coded information, and stored back in cache 750 at an address specified by an address field in the descriptor word. The data is stored in cache 750 via lines RDOD 5 00-35, ZMD 00-35, ASFA 00-35 and RADO/ZADO 00-35. The decimal unit 730 is under firmware control via lines MEM-DO 88, 89, 94-97. PK-VCTR 0-3 signals from the decimal unit 730 indicate to the execution address and branch circuit 701-1 status information in response to firmware commands received by the decimal unit 730 via the lines MEM-DO 88, 89, 94-97. The PKVCTR 0-3 signals received by the execution address and branch 70 1 -1 results in the execution control store 701-2 branching to a particular microprogram subroutine. British Patent 2,009,470 10 described the branching logic associated with the execution control store 701-2.

Data and control signals are transferred between cache 750 and an SIU 100 via the data interface line 600 and between cache 750 and the processor 700 via the lines of interface 604. Lastly, the cache unit 750 receives address and data signals from the data and address output circuits 704 4 via the lines RADO/ZADO 00-35 and the lines ASFA 32-33.

Execution unit 714-Figure 2 The unit 714 includes as major units, addressable temporary register banks 714-10 and 714 12, an arithmetic logic unit (ALU) 714-20, a shifter 714-24 and a scratchpad memory 714-30.

Additionally, the unit 714 includes a number of multiposition data selected switches 714-15, 714 17, 714-22, 714-26, 714-28, 714-34, 714-36 and 714-38 to provide flexibility in selecting 20 operands and output results.

In operation, the operands are selected via the ZOPA switch 714-15 and ZOPI3 switch 714 17 from one of the registers of the banks 714-12 and 714-10 or from other input lines such as ZEBO-35 or RDIO-35 as shown. The ALU 714-20 and shifter 714-24 performs operations upon the selected operands and the results are selected via the switches 714- 24, 714-36 and 714-38 25 to be applied to the output bus lines ZRESA 0-35 and ZRES13 0-35. Similarly, the contents of a scratchpad location selected via signals applied to the ZRSPA 0-6 lines by the AACU unit 722 can be read out via the switches 714-34, 714-36 and 714-38.

The selected output results or other data are thereafter loaded into other registers within processor 700 including the temporary register banks 714-12 and 714-10 or the scratchpad 30 memory 714-30 of execution unit 714.

In greater detail, the sources of operands are identical for both the ZOPA and ZOPB switches 714-15 and 714-17. The selection of switch position for the ZOPA switch and ZOPB switch is under the control of the microinstruction word. The ALU 714-20 performs logical, decimal and binary operations upon the selected operand data under the control of the microinstruction word.

The shifter 714-24 is a combinational logic network used to align, shift or rotate binary data under micro-program control. The input data signals from the ZSHFOP and ZEIS switches 714-28 and 714-22 can be viewed as being concatenated to form a single double word input. The shifter 714-24 provides a 36-bit output shifted in accordance with the shift count. The ZSHFOP switch 714-28 is controlled by the microinstruction word while the shift count is established by the sequence control constant field of the microinstruction word which is appropriately selected via the auxiliary arithmetic control unit 722. For the purposes of the present invention, the ALU 714-20 and the shifter 714-24 may be considered conventional in design. The microinstruction fields controlling the operation of the execution unit 714 are described in related Application Serial No. 853,944 described supra.

The scratchpad memory 714-30 provides a working space for storing various data required for the execution of certain instructions as well as various constants and descriptor values. For example, octal locations 10-15 are used to store an edit instruction table value required for carrying out edit operations. Writing into the scratchpad memory 714-30 involves first loading the RSPB buffer register 714-32 with input data applied via the ZRESB switch 714-38. During a next cycle, the 50 contents of the register 714-32 are written into the location specified by the signals applied to the ZRSPA 0-6 lines by the AACU unit 722. Writing takes place when bit 22 of the microinstruction word (RSP field) is forced to a binary ONE.

As concerns the other switches, as mentioned, the results produced by the unit 714 are provided via the ZALU switch 714-26, the ZSPDI switch 714-34, the ZRESA switch 714- 36 and the ZRESB switch under microprogram control. The ZALU and ZSPDI switches provide a first level of selection to the ZRESA and ZRESB switches which provide a last level of selection. Since both the ZRESA and ZRESB switches have identical input sources, they can provide the same output data.

Operands from the decimal unit 730 are received via the ZDO 00-35 linesand stored in selected RTRL 0-3 registers 714-12 and RTRH registers 714-10 as are described supra.

Long operands are stored in scratchpad memory 714-30. The resultant operand is read through the ZRESA switch 714-36 into the RCHO register 720-10 of character unit 720 and to the decimal unit 730 via the RCHU 0-35 line.

6 GB 2 115 586 A Decimal unit 730---goneral description ystem

Referring to Figure 3, the decimal unit 730 is operative under firmware control processing of decimal numeric instructions and receives data words from cache 750 made up of 4-bit characters or 9-bit EBCDIC or ASCII characters. The data word may contain a trailing sign or a leading sign which may be part of an overpunched character and will also contain an exponent if the data word is a part of a floating point operand.

The decimal unit 730 strips the sign and/or exponent from the data word, compresses the data words from 36-bit words to 32-bit words, packs both the 4-bit and 9-bit decimal digits into data words made up of 4-bit decimal digits, and transfers the resulting 32-bit data words to the execution unit 714 for processing as defined by the instruction.

The most significant and least significant words of the operand received from cache 750 may contain information which is not a part of the operand. This rewrite information is stored in registers and added to the most significant and least significant words of the operand if required during the store operation.

The decimal unit 730 processes operands made up of decimal digits either as short operands or 15 long operands. Short operands are 15 decimal digits long or less. Long operands are from 16 to 64 decimal digits long. Operands having more than 64 decimal digits are not processed in the decimal unit 730 but are processed by the firmware.

Short operands comprising 1 or 2 data words are transferred to temporary registers RTRL 0-3 714-12 and RTRH 4-7 714-10 in the execution unit 714. Long operands comprising from 3 to 8 20 words are transferred to the scratchpad memory 714-30 in the execution unit 714.

Decimal numeric instructions include an instruction word defining the arithmetic operation to be performed, a descriptor 1 word defining the characteristics of an operand 1, a descriptor 2 word defining the characteristics of an operand 2 and a descriptor 3 word defining the characteristics of a resultant operand 3. Some instructions use descriptor 2 to define the characteristics of both operand 2 and operand 3. The instruction and descriptor formats are shown in Figure 5.

The decimal unit 730 under firmware control receives operands 1 and 2 from'cache 750, aligns them and transfers them to the execution unit 714. Both operands are checked for an illegal sign or illegal digits. The resultant operand 3 is transferred from the execution unit 714 to the decimal unit 730 where it is unpacked to 36-bit data words from 32-bit data words, ASCII or EBCDIC zone characters are added for 9-bit words. Exponent characters and signs are added if required. Operand 2 or operand 3 rewrite information previously stored may be added. The operand is checked for zero/overflow conditions, is rounded or truncated if required and stored back in cache 7 50.

Descriptors defining the operands are stored in the RSIR register (not shown in the drawings) of the control logic unit 704-1. The RSIR bit positions 21 through 35 corresponding to the bit positions 35 of the descriptors of Figure 5, are transferred to and stored in registers in the decimal unit 730. The RSIR bit positions 17-20 are transferred to the decimal unit as signals ASFA 33-36 which are also stored in a register in the decimal unit 730.

As shown in Figure 5, the descriptor fields are defined as follows:

ASFA 33 ASFA 34-36 RSIR 21 45 RSIR 22-23 is the least significant bit of the address of the most significant word of the operand 40 indicating an odd or even word address.

points to the digit position within the most significant word of the high order character of the operand.

indicates an operand of 4-bit characters if a ONE or 9-bit characters if a ZERO.

defines the operand type and sign position.

00 Leading sign floating point or overpunched sign leading.

01 Leading sign scaled.

Trailing sign scaled.

11 No sign scaled or overpunched sign trailing.

indicates the scale factor, i.e. the position of the decimal point. A negative number moves the decimal point to left of the least significant digit. A positive number moves the decimal point to the right of the least significant digit.

RSIR 30-35 indicates the number of characters in the operand. Characters include decimal digits, sign characters and exponents.

RSIR 24-29 The firmware controls the decimal unit with the signals RCSR 88-89, 94-97. The signals are 55 outputs from the execution control store 701-4. Except for the CLK, ZAM, MPYREG and DUCMD fields, the firmware word is described in detail in the specification of British Patent 2,008,817.

7 GB 2 115 586 A 7 Table 1

Logic name of RCSR Signals firmware controlled 88, 89, 94, 95 96, 97 Description signals 5

TYPEF CLK, ZAM, MPYREG 1 0 0 0 0 0 Set FMYDV if FPOP 1 D, otherwise NULL DUCMD-200 1 0 0 0 0 1 Select RESULT=ZERO indicator 1 DUCMD-201 1 0. 0 0 1 0 Select OP 1 =ZERO, OP2=ZERO DUCMD-202 indicators 10 1 0 0 0 1 1 Load STC MASK into RDOD DUCMD-203 1 0 0 1 0 0 Select DU OVERFLOW and DUCMD-204 TRUNCATION indicators 1 0 0 1 0 1 Reset ZERO/OVERFLOW CHECK logic DUCMD-205 1 0 0 1 1 0 Set FCMPN if FPOP 1 D DUCMD-206 15 1 0 0 1 1 "l Unused TYPE F DUCMD 1 1 0 0 0 0 Set FMVN if FPOP 1 D, otherwise NULL DUCMD-300 1 1 0 0 0 1 Read OPERAND through DU DUCMD-301 1 1 0 0 1 0 Force Load Complete Status DUCMD-302 20 1 1 0 0 1 1 Store Operand Through DU DUCMD-303 1 1 0 1 0 0 Check ZERO/OVERFLOW DUCMD-304 1 1 0 1 0 1 Transfer Data from RCHO to RPK DUCMD-305 1 1 0 1 1 0 Load Rewrite Data DUCMD-306 1 1 0 1 1 1 Load the DU Sign Register (RSGN) DUCMD-307 25 1 1 1 0 0 0 Load the DU Exponent Register (REXP) DUCMD-308 1 1 1 0 0 1 Put the Rounding Constant into RDOD DUCMD-309 1 1 1 0 1 0 Put Operand Leading Zero Count DUCMD-31 0 into RDOD 1 1 1 0 1 1 Put Operand Word Count into RDOD DUCMD-311 30 1 1 1 1 0 0 Unused 1 1 1 1 0 1 Select Descriptor Vector Indicators DUCMD-313 1 1 1 1 1 0 Select Store Op Vector Indicators DUCMD-314 1 1 1 1 1 1 Select Long Op Vector Indicators DUCMD-315 Note that the RSCR bit positions 88 and 89, the TYPE F field, define the fields identified by RSCR 35 bit positions 94-97. If the TYPE F field contains a - 1 W then microword fields CLK, ZAM, and MPYREG are selected. If the TYPE F field contains a---11" then microword field DUCMD is selected

DUCMD 200 sets the FMYDV flag during a multiply or divide decimal instruction.

DUCMD 201 selects the ADSZ conditional branch.

DUCMD 202 selects the RRLTRD conditional branch indicator if operand 1 equals zero and 40 selects the RREQRD conditional branch indicator if operand 2 equals zero.

DUCMD 203 transfers the RCHU 30-35 output signals storing the STC mask into the RDOD register 730-154.

DUCMD 204 selects the RRLTRD conditional branch indicator for an overflow and the RREQRD conditional branch indicator for a truncation operation. 45 DUCMD 205 resets the FCRD and FDIFK flags.

DUCMD 206 sets the FCMPN flag if the FPOP 1 D flag is at logical ONE.

DUCMD 300 sets the FMV flag if the FPOP 1 D flag is at logical ONE.

DUCMD 301 starts the operand load operation in the decimal unit 730.

DUCMD 302 forces completion of the load operation by setting the FLDCOMPL and the FRDP 1 50 flags.

DUCMD 303 starts the store result through the decimal unit 730 by setting the FOPSTR and FMSDRN flags.

DUCMD 304 sets the FCZO flag for a check zero/overflow of the word stored in the RCHO register 720-10. 55 DUCMD 305 sets the FCZO and FRPK flags.

DUCMD 306 sets the FLDREWR flag and selects the RREQRD condition branch indicator for a truncation operation.

DUCMD 307 conditions the loading of the sign register RSGN 730-134.

DUCMD 308 conditions the loading of the exponent register REXP 730-138. Also conditions 60 the loading of the RSF3 scale factor register of register bank 730-4 during a floating point FPOP3 cycle.

8 GB 2 115 586 A 8 controls the loading of the rounding constant stored in the ZPK switch 730-150 into the proper character position of the RDOD register 730-154 and sets the FRCM D flag. controls the loading of the operand leading zero count into the RDOD register 730-154. controls the loading of the operand word count into the RDOD register 730-154. unused. selects the descriptor 1 vector and descriptor 2 vector indicators and sets the FDVC1 flag. resets the FCRD flag and selects the store vector indicators. selects the long input vector indicators.

DUCMD 309 DUCMD 310 DUCMD 311 DUCMD 312 DUCMD 313 DUCMD 314 DUCMD 315 The Decimal Unit 730 responds to the firmware requests with the PK VCTR 0- 3 signals indicated below.

Table 2

Vector branch data 15 PK- VC TR 0 1 2 3 Type-length 0 0 0 0 Short Operand and 4-bit data 0 1 0 0 Short Operand and 9-bit data 20 1 0 0 0 Short Operand and (4 or 9 bit data) and overpunched sign 1 1 0 0 Long Operand Descriptor 1 vector 0 0 0 0 Execute Descriptor 2 vector 0 1 0 0 Descriptor 1 =floating point 25 1 0 0 0 Descriptor 1 =overpunched leading sign, scaled 1 1 0 0 Descriptor 1 =overpunched trailing sign, scaled Descriptor 2 vector 0 0 0 0 Descriptor 2#floating point or overpunched sign 0 1 0 0 Descriptor 2=floating point 30 1 0 0 0 Descriptor 2=overpunched leading sign, scaled 1 1 0 0 Descriptor 2=overpunched trailing sign, scaled Store vector 0 0 0 0 Check for RESULT=ZERO, OVERFLOW 0 1 0 0 Floating point result-Check for RESULT=0, Overflow 35 1 0 0 0 Overpunched leading sign output-check for RESULT=0, Overflow 1 1 0 0 Overpunched trailing sign output-Check for RESULT=0, Overflow 0 0 0 0 0 1 0 0 1 0 0 0 1 1 00 Long-input Both operands scaled and adjusted length descriptor 1:563 and adjustdd length descriptor 2:563 and overpunched sign Both operands scaled and adjusted length descriptor 1!5;63 and adjusted length descriptor 2:!63 and overpunched sign Both operands scaled and adjusted length descriptor 1 >63 or adjusted length descriptor 2<63 Execute descriptor 1 and descriptor 2 vectors J Table 2-continued Vector branch data Predicted number of cycles of delay for processing descriptor 1 or descriptor 2 operands PK-VCTR 0 1 2 3 Words of data Cycles of delay 50 0 0 0 0 1 0 0 0 0 1 2 0 0 0 1 0 1 0 0 1 1 2 0 1 0 0 1 2 55 0 1 0 1 2 2 9 GB 2 115 586 A 9 The following Boolean expressions show the firmware selection of the vector branch data:

[1 MVCTR=MACT (DUCMD 31 5+DUCMD 313. MCV1 +FRDP 1 (DUCMD 31. DUC-M-5-3114. DUCMD 315) -UCWFD-M [2 MVCTR=FDUACT (DUCMD 314+DUCMD 315+DUCMD 301 +DU D. FRDP 1) (4 MVCTR=FDUACT (DUCMD 3113+DUCMD 314+DUCMD 315) [PKVCTR=l selects the type length vector which indicates to the firmware whether the operand is a short or long operand, 4 bit characters or 9 bit characters and if a short operand whether there is an overpunched sign in the descriptor 1 or descriptor 2 operands.

[PKVCTR=2 or 3 selects for short operands the number of cycles of delay needed after the first read command is sent to cache 750 to the first data word being sent to the execution 10 unit 714. This prediction simplifies the firmware processing of short operands.

[PKVCTR=4 selects the descriptor 1 vector which defines descriptor 1 as a floating point operand, an overpunched leading or trailing sign scaled operand or indicates to the firmware to execute the descriptor 2 vector, [PKVCTR=5 selects the descriptor 2 vector which defines descriptor 2 as a floating point or 15 scaled operand with overpunched leading or trailing sign.

[PKVCTR=6 selects the store vector which indicates to the firmware to specific check for resulting operand equal to zero.

[PKVCTR=7 selects the long-input vector and indicates to the firmware the comparison between the operand lengths and 63 for scaled operands. The vector also indicates 20 to the firmware to execute the descriptor 1 and descriptor 2 vectors.

The decimal unit 730 supplies a number of conditional branch indicators to the execute address and branch circuits logic 701-1.

Conditional branch indicators Name Source 25 START-WRT R13LTRI) SEND-DATA IRREQRD OP1=ZERO RRLTRD OP2=ZERO RREQRD OVERFLOW RRLTRD 30 TRUNCATION RREM RESULT=ZERO ADSZ DATA-AVA ADSZ CK-STR-VECT ZAMO The RRTRD signal is generated:

1. during a DUCMD 202 command when the FOP 1 Z flag is set indicating that operand 1 is zero.

2. during a DUCMD 204 command when the FDOFL flag is set indicating that there was an operand overflow.

3. during a start write operation to indicate to the firmware to send write commands to cache 750.

The RREQRD signal is generated:

1. during a DUCMD 204 or DUCMD 306 command with the truncation signal at logical 1 indicating that least significant digits of an operand will be lost.

2. during a DUCMD 202 command when the F0P2Z flag is set indicating operand 2 is zero.

3. during a send data operation to indicate to the firmware to transfer data to the decimal unit 45 730 from the execution unit 714.

The ADSZ signal is generated:

1. during a DUCMD 201 command when the operand is equal to zero.

2. when data is not available except during a DUCMD 201 command.

The ZAMO signal is generated to indicate a check store vector function such as floating point, 50 overpunched character, overflow, result=0 operand.

The conditional branch indicators are called for by the firmware and results in an execution control store 701-2 branch.

Description of decimal unit status flags including the boolean expressions for setting and resetting the flags are:

GB 2 115 586 A 10 F3DESC Set for the processing of operand 3 which is defined by either descriptor 2 or descriptor 3. The boolean expression is:

F3DESC SET: (FPOP - RDESCO - RDESC1) F3DESC RESET: (FPOA) FALT Set during the store operation on alternate cycles. The decimal unit prepares a 5 word for the RDOD register 730-154 on one cycle and transfers the word to the Execution Unit 714 on the next cycle. FALT set enables the storing of a word in the RDOD register. The boolean expression is:

FALT SET: MUCMD 303+FOPSTR) - TATULT - TPOT) FALT RESET: (FOPSTR FALT+FPOA) 10 FCMPN Set for a DUCMD 206 firmware command for a compare numeric instruction. The boolean expression is:

FCMPN SET: (FPOP 1 D - DUCMD 206) FCMPN RESET: (FPOA) FCPCO Set when loading or storing 9-bit data words from odd addresses in Cache 750. 15 The boolean expression is:

FCPCO SET: ((ZCPAO - (FDUACT - FRD-O 1 +SFOP2 LD +FLDCOMPL - (DUCMU-30-9 +FOP STR)) +FCPC -(FOP1LD-9-F0= +FOP2LD) - (FDID+FDFD)+FCPC 20 (DUCMD 303+FOPSTR) - FPO-A) [tRDOD) FCRIP1 FCPO RESET: (Z-CP-Ak-0. WDUAI5T. F9M +SFOPM+FI-DCOMPI- FCRD FCZO FDADIS FDATA-AV F13FD DUCMD 303+FOPSTR +FCPCO (FOP 1 LD. SFOP21-13+170P2LD) WDID+MFM+FWC0 (DUCMD303+FOPSTR). [$RDOD +FPOA) Set during an operand load operation when one of the operands is long. This flag 30 lets the second load DU operand command (DUCMD 301) start a load process. A long operand causes the decimal unit to cancel the first load DU operand command (DUCMD 301) to enable the firmware to get set up to process a long operand. The firmware always assumes a short operand operation. The boolean expression is:

FCF1P1 SET: ((DUCMD 301. FRDPI. (D1 EQOVP +D2EQ0VP+LONW).

FCF1P1 RESET: (FPOA) Set by a DUCMD 305 firmware command or an FCZO flag on for a check zero/overflow operation and reset by a DUCMD 205 or 314 command. Remains set for the entire operation processing. The boolean expression is:

FCRD SET: ((DUCMD 305+FCZO). P-PM) FCRD RESET: (DUCMD 314+DUCMD 205+FPOA) Set by a DUCMD 304 or 305 firmware command for a cheek zero/overflow of the word stored in the RCHO register 720-10. The boolean expression is:

FCZO SET ((DUCMD 305+DUCMD 304)). FPOA) FCZO RESET: (SF=+FPOA) Set for 9-bit decimal digit operand loads on alternate cycles to allow two 4 digit words to be received from cache 750 and stored in the,RDOD register 730154 as one 8 digit word. The boolean p "res ion is:

FDADIS SET (ZTNSA10. FRDP +ZT FRDP2). DATA-AV. FPM. SFOP2LD FDADIS RESET: (SFDADIS. ([$RDI-PC+SMI7D +FDFD. RFIJiF +SFOP2LI3) Is set to load the RDOD register 730-154 by controlling the strobe signal [$RDODA.

The boolean expression is:

FDATA-AV SET: (DATA-AV. M-R FDATA-AV RESET: (9-F-D--A-T-A,--"+FPOA) Is set during a load operation to indicate that the complete operand has been received from cache 750 by the decimal unit 730. The boolean expression is: 60 FWD SET: (DFCO. MID. (RFDM. FPOA. (FOP 1 LD SFUP-=+FOP2LD)) FWD RESET: WPOA+DI7CO. MID. DTECO [$RDODA+1317CO. FDID. FDTED +DTECO. [$RDODA. FWD) -- - d ' -- 11 GB 2 115 586 A 11 MID FDOFL -10 FDTED FDUACT FIJIVIC1 FDZERO FFDI FFDO FFOSD FILLDIG FLDCOMPI- FLDGR Set when operand data is loaded into the RDID registers 730-158. The boolean expression is:

MID SET: ([$RDI-PC. FI-DREW. FRDPI) MID RESET:

Set when an operand overflow is detected during a check zero/overflow operation 5 and reset by a DUCIVID 205. The boolean expression is:

FDOFL SET ((DUCMD 305+FCZO). DOFL. -F-P-07 FDOFL RESET: (DUCIVID 205+FPOA) Set when all of the decimal digits of the operand were sent to the execution unit 714 but not all of the operand information has been received by the decimal unit; 10 exponent or sign information for example. The boolean expression is:

FDTED SET: (DTECO - [$RDODA - CR-F-D)-M - F7M - (FOP 1 LD - SFOP2LD+FOP21 D)) FDTED RESET: (FRDFD) Set during an FPOP control logic unit 704-1 cycle to indicate a decimal unit 730 15 operation. The boolean expression is:

FDUACT SET: (FPOP) FDUACT RESET: (FPOA) Is set when the firmware sends a DUCIVID 313 for descriptor 1 information so that descriptor 2 information is sent on the next DUCIVID 313. The boolean expression 20 is:

FDVC1 SET: (DUCIVID 313 - -F-P5A-l FDVC1'RESET- (FPOA) Is set if the operand check with the check zero/overflow commands DUCIVID 304 or 305 equal to zero. The boolean expression is:

FDZERO SET: QDUCIVID 305+FCZO) --b-ZER0 - FPOA) FDZERO RESET: (FPOA+(DUCMD 305+FCZO) -DZERO-FCRD) Is set when the first word of the operand from cache 750 is loaded into the decimal unit. The boolean expression is:

FFDI SET: ODID - ff-FCO - (FOP 1 LD+FOP2LD)) FPOT) FFDI RESET: (SFOP2LD+FPOA) Is set when the first word of the operand is stored in the RDOD register 730-154 prior to being transferred to the execution unit 714. The boolean expression is: 35 FFDO SET: (([$RDODA &(FOP 1 LD+FOP2LD) - DTECO -FPOA) FFDO RESET (SFOP2LD+FPOA) Is set when the first data word to be stored in cache 750 is loaded into the RDOD register 730-154. The boolean expression is:

FFOSD SET: ((FOPSTR+DUCMD 303).[$RDODA - FPOA) FFOSD RESET: (FPOA) Is set when an illegal digit or illegal length is received by the decimal unit 730. It signals a fault to the system and is reset one cycle later by the FLDGR flag. The boolean expression is:

FILLDIG SET: (([$RDODA - (FPOP 1 LD+FOP2LD) - DZIDEQIDALLEGALLENGTH (SFOPlLD+FCZO)).FLDG +F-P-OA)) FILLDIG RESM (FLDGR+FPOA) Is set when both operands have been transferred to the execution unit 714. The boolean expression is:

FLDCOMPL SET: (((FOP 1 LD - FMVN+FOP2LD -FIVV.(DFCO-FDID.DTECO [$RDODA+DFCO - FDID - FDTED +DTECO - [$RDODA - FDFD) +DUCMD 302) - FPOA) FLDCOMPL RESET: (FPOA) Is set at the same time as the FILLDIG flag, i.e., when an illegal digit or illegal length is received in the decimal unit 730. It resets the FILLDIG after one cycle. The boolean expression is:

FLDGR SET: (([$RDODA - (FOP 1 LD+FOP2LD) - DZIDEQID+ILLEGALLENGTH - (S FO P 1 LD + FCZO)) - F-P O-A-) FLDGR RESET: (FPOA) 12 GB 2 115 586 A 12 i FLDREWR FLIDREWRH FMSDRGTE FMSDRN FIVISEQ, FMVN WYDV FOP 1 LD Is set from the firmware by a DUCIVID 306 load rewrite data signal to start the sequence for storing the first or last words defined by descriptor 3 in the REWR 0 3 register bank 730-177. The boolean expression is:

FLDREWR SET: (DUCIVID 306) FLDREWR RESET: (DUCMU) 306) Is set one cycle after the FLDREWR flag is set to strobe the first or last word into the REWR2 or REWR3 register respectively of the REWR 0-3 register 730-177 during a descriptor 2 store operation. The boolean expression is:

FLDREWRH SET: (FILDREWR) FLDREWRH RESET: (FLDREWR) Is set during a store operation on a DUCIVID 303 firmware command if word count in the RRWC register is greater than or equal to the word count in the RWPC register at the time the DUCIVID 303 is used. The boolean expression is:

FMSDRGTE SET: (DMSDRGTE DUCIVID 303) - FALT - (DUCIVID 303 - RRWCO+FMSDRN) - FPOA FMSDRGTE RESET: (FPOA) Sets on the DUCMD 303 firmware command for a long operand store if the word count in the RRWC register is negative initially. The boolean expression is:

FIVISIDRN SET: (DUCIVID 303 - RRWCO - FIVISDRN RESET (FPOA) 20 Sets during a long operand store sequence when the word count in the RRWC register equals the word count in the RWPC register. The boolean expression is:

FIVISEQ SET: (DIVISEQ - (FSW - DMSDRGTE+FSWRT (ZTNSAO+2TNgA - FCPCO)) (DUCIVID 303+FOPSTR) - FACT (DUCIVID 303 - RRWCO+FMSDR-N-) - FPOA FIVISEQ RESET: (FPOA) Is set for a move numeric instruction. The boolean expression is:

FIVIVN SET: (DUCIVID 300 - FPOP1 D) FIVIVN RESET: (FPOA) Is set for multiply and divide instructions. This flag suppresses the scale factor alignment and right justifies the operands on a load operation. The boolean expression is:

FMYDV SET: (DUCIVID 200. FPOP1 D) FMYDV RESET: (FPOA) Is set for the operand one loaq operation. The boolean expression is:

FOP 1 LD SET: (DUCIVID 301 - FRDP 1 - F-POA - (D1 EQOVP - D1EQOVP LONG+FCRP 1)) FOP 1 LD RESET: (FPOA+FOP 1 LD - DFCO - DTECO - FDID [$RDODA+FOP 1 LID - DFCO -FDID - FDTED+FOP1 LD - DTECO [$RDODA. FDFD) FOP1Z Is set if operand 1 equals zero. The boolean expression is:

FOP 1 Z SET: (f$RDODA. FOP 1 LID. WIDEW. F-PORT FOP 1Z RESET: (FPOA) 45 FOPSTR Is set by the DUCIVID 303 store operand through decimal unit 730 firmware command. The boolean expression is:

FOPSTR SET: (DUCIVID 303. FPOA) FOPSTR RESET: (FPOA) F0P2F Is set for an operand 2 load and the first data word is received in the RDID register 50 730-155. The boolean expression is:

F0P2F SET: (FDID. F0P2LD - FFOA. 5-F-CO) F0P2F RESET: WPOA+WiCO. MID) F0P2LD Is set for the operand 2 lo;l oeration. The boolean expression is:

F0P2LD SET: ((FOP1LD. FIVIM (DUCIVID 301 55 +FRDP2). (DFCO. FIDID - DTECO [$RDODA+WCO. FIDID. FDTED F0P2S +DTECO. SRDODA. FDFD)+FOPTO. FMViR. DUCM D 301. FRDP 1). F0P2LD RESET: (PPOA+FOP2LIDi. (DFCO. MID DTECO. [$RIDODA+WCO. WID FIDTED+DTECO. [$RDOIDA. MM) Is set on an operand 2 load operation when the second word is stored in the RDID register 730-158. The boolean expression is:

13 GB 2 115 586 A 13 F0P2S SET: (F0P2F. MID. FPOA) F0P2S RESET: (FPOA) FOP2Z Is set if-operand 2 is equal to zero. The boolean expression is:

FOP2Z SET: ([$RDODA - FOP2LD - DZID E52TP-0-A) FOP2Z RESET (FPOA) 5 FPFL Is set if operand 1 or operand 2 are specified as floating point. The boolean expression is:

FPFL SET: ((DIEQFLT+D2EQFLP) FOP1LD-FPOA)) FPFL RESET: (FPOA) FRCIVID Is set by a DUCIVID 309 firmware command to read the rounding constant into the 10 RDOD register 730-154. The boolean expression is:

FRCMD SET: (DUCIVID 309 FRCIVID RESET: (FPOA) FRDIDH Is set to indicate that the requested information is not stored in cache 750 and cache must request if of backing store. When the data is received in cache and sent 15 to the decimal unit 730, the FRDIDH flag gates the recovery signal to strobe the data into the RDID register 730-158. The boolean expression is: FRDIDH SET: ([$RDI-PC) FRDIDH RESET: (FRDIDH) FRDP1 Is set by DUCIVID 301 or DUCIVID 302 firmware commands to indicate that the 20 command for reading the first operand has been issued to the decimal unit 730.

The boolean expression is:

FRDP 1 SET: ((DUCMD 301 - (51 EQOVP - D2EQOVP LON?3+FCRP 1) +DUCIVID 302) - -FROT) FRDP 1 RESET: (FPOA) 25 FRDP2 Set by a DUCIVID 301 firmware command when the FRDP 1 flag is set to indicate that the command for reading the second operand has been issued to the decimal unit 730. The boolean expression is:

FRDP2 SET: (DUCIVID 301 - FRDP 1 - _FP5A) FRDP2 RESET: (FPOA) 30 FREWR Is set by the FLDREWRH flag in the cycle following the setting of the FLDREWRH flag. The flag is used to force the rewrite data to be read from REWR2 and REWR3 during the operand store process. The boolean expression is:

FREWR SET: (FLDREWRH - FPTA FREWR RESET: (FPOA) 35 FREWR2 Is set by the FREWR and FLDREWRH flags both on. It causes the REWR3 register to be used to provide rewrite data for the last word of operand 3. The boolean expression is:

FREWR2 SET: (FLDREWRH - FREWR - FP FREWR2 RESET: (FPOA) 40 F3DESC Is set for the descriptor 3 operation. The boolean expression is:

F3DESC SET: (FPOP - RDESCO - fD__ESC1) F3DESC RESET: (FPOA) FPOP31) Is set for the cycle following FPOP3 cycle of the control logic unit 704-1. The boolean expression is: 45 FPOP3D SET: (FPOP - RDESCO - RDESC I FPOP3D RESET: (FPOA+FPOP3D - (DUC-M-D-3-0-6 +_FC_ZO)) FPTL Is set for the condition that the adjusted length, length plus scale factor difference is greater than 63 characters. The boolean expression is:

FPTL SET: (ALNSLTE6 - FOP 1 LD - F-POT) 50 FPTL RESET: (FPOA) FRPK Is set on a DUCIVID 305 transfer data from RCHO to RPK firmware command and is used for the short operation store. The boolean expression is:

FRPKSET-(DUCMD305.DIEQFL TP-W FRPK RESET: (FPOA+DUCMD 205) 55 FSND Is set when the SEND DATA bit is forced to a ONE. SEND DATA indicates to the firmware to load a new word into the RCHO register 720-10 during a long operand store. The FSND flag strobes the previous word stored in the RCHO register into the RPK register 730-162. The boolean expression is:

FSND SET: (FALT - SEND-DATA - FPOA) 60 FSND RESET: (FALT - SEND-D +FPOA) FSSFD Is set when the scale factor difference is negative. The boolean expression is:

FSSFD SET: (ASF2 - FDUACT - FRDP 1) FSSFD RESET: (AW-2 - FDUACT - T_R_DP 1 +FPOA) 14 GB 2 115 586 A 14 FSWRT FPOP 1 D FTD130 FTDB 1 FXF Is set when the STRT-WRT signal to the firmware is forced to ONE. STRT- WRT enables the firmware to start issuing write commands to the cache 750 during the long operand store procedure. FSWRT informs the DU hardware control that the firmware is is nwrite commands. The boolean expression is:

FSWRT SET: (FALT - STFIT-WRT. (DUCMD 303 +FOPSTR). FPOA) FSW11T RESET: (FPOA) Is set for the cycle following FPOP 1 cycle of the control logic unit 704- 1. The boolean expression is:

FPOP 1 D SET: (FPOP - RD-ESCO. -R-D-ES-C-1) FPOP 1 D RESET: (SFPOP 1 D) Are set as a 2-bit counter to count down the number of cycles of delay for strobing the operand word into the F1DOD register 730-154 for transfer to the execution unit 714. The boolean expression is: - FTD130 SET: (TDBO. DUCMD 301. FPOA FTD130 RESET: (T-D-B-O. DUCMD 301 +(FOP 1 LD +FOP2LD) DUCMD 301. [RDI-PC A-POA) FTD131 SET: (RD131. DUCMD 301 +FTDBO (FOP 1 LD+FOP2LD). DUCMD 301 [$RDI-PC). FPOA) FT131 RESET: (T--DBl. DUCMD 301 +FTDBl - (FOP 1 LD+ FOP2LM. DUCMD 301.[$RDI-PC+FPOA) Is set during the load operand procedure when the first non zero character is detected in the input data. It indicates the end of the number of leading zeros in the 25 operand. FWIF SET: ([$RDODA. (FOP 1 Ll)+ FOP21-13). LWO. RFOA7 MCF RESET: (SFOP21-D+FPOM The following are the boolean expressions fofunctions not previously described: SFM=MUCMD 305+DUCMD 304). FPOA SMADIS=(ZTNSA0 - RMP2+ZTNS130 - FRDP2) - DATA-AV. F-PM - grup-= SF13FD=WCO. MID. (RFDFD). FPOA SMATA-AV=DATA-AV. FPOA [$RDI-PC=ENABIZ+ FTRF+FMT. (SRAD01. (RDIN. EQ. 0-11 M +TYPE. (MISREG. EQ. M+TYPD. (IBUF. EQ. U+M. (013PIPE. EQ. 1). FE1 2+TYPI31) (2). (MSKD. NEQ - 0) +TYPBD (3). STU+FREWA. (RMEM. EQ. (8-10)) +FREQDI+FDIDBL MID=[$RDI-PC. FI-DRIEWR. FRDP 'I DOFL indicates an overflow condition DZIDEQID=(ZID4. (ZID5+ZID6))+(ZID8. (ZID9+ZID10)) +(ZID1 2. (ZID13+ZID14))+(ZID1 6. 01317 +Z]Dl 8))+ (ZID20. (M1)21 +Z[D22))+(Z]D24. (Z[D25+Z]D26))+(Z]D28. (ZID29+Z[D30)) + 01)32. (Z]D33+ZID34)) ILLEGALLENGTH=ALNDAO+ALNDBO+ALNDAZ+ALNDBZ DZERO indicates that the operand word contains all zeros.

Decimal unit-logic The scale factors for operands 1, 2 and 3 are received in the decimal unit 730 through a 4- 50 position switch ZSM 730-2 over signal lines RSIR 24-29 from the control logic unit 704-1 and are stored in registers RSFO, RSM, RSF2 respectively of register bank 730-4. ZADSP 3-11 signal lines apply the scale factor to position 0 of the switch when the scale factor is calculated by the firmware.

ALNDA signal lines apply the adjusted length of operands to position 2 of the switch during a floating point operation. The AEDC and ZEDC signals are applied to position 3 of the switch to store the number 55 of effective digits during a floating point operation. This is described in greater detail as part of the store operation description.

Control signals [1 ZSM and [2ZSFN select the switch 730-2 positions. The boolean expressions are:

[1ZSFN=((F3DESC+FMVN). FLDCOMPI- - FF00P. D1 EMP +DUCMD 305+FCZO)) [2ZSFN=((F3DESC+FMVN). FLDCOMPL. FPOP. D1 EWLP) For a non floating point operands the operand 2 scale factor is selected by the RSF1 position of a GB 2 115 586 A 15 ZSFB switch 730-8 and is applied to an input of an ASIF adder 730-10 where the operand 2 scale factor is subtracted from the operand 1 scale factor selected by the RSFO position of a ZSFA switch 730-6. If the operand 1 spale factor is larger than the operand 2 scale factor then the signals ASFO-9 represent a positive number and bit position ASIF2 is a logical ZERO. If the operand 2 scale factor is larger, then the signals ASIF0-9 represent a negative number and bit position ASIF2 is a logical ONE.

The length or number of numeric characters for operands 1, 2 and 3 is received over signal lines RSIR 30-35 from the control logic unit 704-1 and are stored in registers RI-NDO, RI-ND1 and RI-ND2 respectively of a register bank 730-12. An ALNIDA adder 730-18 and an ALNDB adder 730-20 calculate the number of decimal digits in operands 1 and 2 respectively. This is accomplished by subtracting the number of non digit characters in the operand such as sign and exponent from the 10 length. The output of a decode logic 730-38 and a decode logic 730-40 is applied to adders ALNIDA 730-18 and ALNDB 730-20 respectively to adjust the operand 1 and operand 2 lengths.

The sign and decimal type for operands 1, 2 and 3 are received over signal lines RSIR 21-23 from the control logic unit 704-1 and are loaded into registers RTNSO, RTNS 'I and RTNS2 respectively of register bank 730-32. A ZMSA switch 730-36 selects the operand 1 sign and 15 decimal type stored in register RTNSO and applies it to the decode logic 730-38. A scaled unsigned operand results in a ZERO output, a scaled signed operand results in a ONE output, a floating point operand having 9- bit decimal digits results in a TWO output and a floating point operand having 4-bit decimal digits results in a THREE output from decode logic 730-38 respectively. The output value is subtracted from the operand 1 length in the ALNIDA adder 730-18 to give as an output, signals ALNIDA 0-6 which indicate the number of decimal digits in operand 1. The number of decimal digits in operand 2 indicated by signals ALNDB 0-6 are calculated in a similar manner.

Signals DBITX. and DBITZ are logical ONE indicates that a binary ONE is subtracted from the ALNIDA adder 730-A 8 and the ALNDB adder 730-20 respectively. The boolean expressions are:

D131TX=((ZTNSA1. ZTNSA2)+(ZTNSAO. ZTNSA1. ZTNSAU 25 DBITZ=UTNS131 ZTNS-B2)+(ZTNSBO.ZTNSB1 ZTNSB2)) Signals D1 EOFLP and D2EMP at logical ONE indicates that a binary TWO is subtracted from the ALNDA adder 730-18 and the adder 730-20 respectively. The boolean expressions are: D1 EMP=(ZTNSA1 Z-TNSA-2. (ZTNSAO+RUP--f) D2EQ1FLIP=(-ZT- NW 1 -ZT-N-S-B-3'2. (ZTNSBO±ROP-1-) ROP 1 indicates an overpunched sign instruction.

A ZALNID switch 730-22 selects the adjusted length of the operand with the larger scale factor and applies the output to an ALNS adder 730-24 which adds to it the absolute value of the scale factor ASF 0-9 output of the ASF 730-10 adder. Bit position ASIF2 selects the operand with the larger scale factor. Bit position AM at a logical ONE indicates that the operand 2 scale factor is larger. 35 The output of a ZI-NAW switch 730-26 applies the adjusted length to an ARWC counter 730 and an ACPR counter 730-62. The inputs to the ZI-NAW switch 730-26 are described below.

If the operand 1 scale factor is larger, then the switch selects the ALNS 0-9 input signals for operand 1 and the ALNDB input signals for operand 2. If the operand 2 scale factor is larger, then the switch selects the ALNDA 0-6 input signals for operand 1 and the ALNS input signals for operand 2. 40 A floating point operand or a multiply or divide instruction does not require a scale factor alignment, therefore, the ALNIDA 0-6 and Al-NDB 0-6 input signals are selected for operand 1 and operand 2 respectively. The RILM input signals are selected during a floating point store operand and provide the number of leading zeros in the operand.

Control signals 41ZLNADJ and 42ZLNADJ select one of four positions of ZINAW switch 730- 45 26. The boolean expressions are:

PZI-NADJ=(FLIDCOMPL.FRI3P1. CF-SS-FD+FMYDV+D1EQFLP +D2EQFLP+ALNS2)+FLDCOMPL (F3DESC +FIVIVN). D 1 EWLP. FDOFL) [2ZI-NADJ=(EDOACT. F-RDP1.;S-F2+FRDP1. FSSM -M -YD V. 1511 E -QF L P. 52-E Q -FL P + A L N S. FL-D -GOWL +FLIDCOMPIL. (F3DESC+FiVIVN). D 1 EQ1FLIP +131 EMP. FDOFL) If the outputs of the ALNDA adder 730-18, the ALNDB adder 730-20 and the ALNS adder 730-24 are all 15 decimal digits or less, this indicates that the non floating point decimal instructions 55 are executed in the short operand mode. This mode provides for increased system throughput in processing decimal instructions over the prior art, since much of the operand manipulation is done using logic performing many of the operand setup functions in parallel. The prior art performed many of the functions serially. The boolean expression for the short operand is as follows: Short=(Al-NDA1. AL-N-DA-22) 7AL-NDBl - Al-ND132) (AL-NS3. ALNS4.7"L--NS5+ FMYDV) FD-l-r07W+D-2rWEM Note that the scale factor adjustment is not implemented for the multiply or divide instructions.

1 i 16 GB 2 115 586 A 16 The ARWC adder 730-60 calculates the number of words to be transferred to the execution unit 714 for both short and long operands. The signal [ONE/ARWCB is applied to the minus input to adder ARWC 730-60 and, when at logical ONE, is subtracted from the adjusted length ZI-NAW 0-9 for a load operation. This assures that if the adjusted length as indicated by the ZI-NAW 0-9 signals was 8-decimal digits, i.e. the ZI-NADJ6 signal was a ONE, then subtracting ONE would make bit position 5 ARWC6 a ZERO and 8 decimal digits will be loaded into the first word. Discarding bit positions ARWC 7-9 leaves bit position ARWC6 as indicating the number of words for the short operand. A ONE in bit position ARWC6 indicates a short operand of 2 words and a ZERO indicates a short operand of one word. The boolean expression for control signal [ONE/ARWCB is:

[ONE/ARWCB=FLDCOMPL+ZTNSA1 (ROP1+MSA0 10 :-Z--TNSA2))+TF-R-PK. ZLNADJ.2rN7Ti-8 - Zi-NADJ9. FLDCOMPQ) The ARM 0-6 output signals indicating the number of words in the operand is available to the firmware when the execution control store 701-4 sends a firmware word which is decoded in the decimal unit 730 as a DUCMD 311 "Put Operand Word Count into RDOD- signal and makes the word 15 count available through a ZUC switch 730-76, position 3 of a ZM switch 730-150, position 0 of a MOD switch 730-152 to a RDOD register 730-154 from which it is transferred to the execution unit 714.

The ACPR adder 730-62 subtracts the adjusted length in decimal digits decoded by the ZLNAW 0-9 signals from decimal 64. The quantity 64 is the maximum number of digits in an 20 operand that is processed by the decimal unit 730. The resulting output signals ACM 3-9 indicate the number of zero digits to the left of the high order digit position for a 64 decimal digit operand. This value is stored in an RLIVIP register 730-102. Bit positions RLIVIP 4-6 store a binary code indicating the number of high order positions in the first word of the operand received by the decimal unit 730 to be forced to ZERO. The RLIVIP 4-6 signals are applied to a MMU shifter 730-130. The number of 25 high order digits to the left of the most significant digit position to be forced to ZERO is indicated by the number of successive signals starting with the ZIDMU 0 signal which are forced to ZERO. The ZIDMU 0-7 signa!s are applied to a [EZID logic control 730-132. The output signals [EM 0-7 output signals suppress the Z11) switch 730-150 in zero to the left positions and enables the digit positions of a Z11) switch 730-150 starting with the most significant digit position. The portion of the RI-MP register 730-102 storing the RLIVIP 0-3 bit positions has the capability of being incremented for every operand word received by the decimal unit 730 by the [CNTUP-RLIVIPU signal. The boolean equation is: [CNTUPRLMPU=((F0P1 LD+FOP2LD). [$RDODA. SFOP2LD) The boolean expression for the siúLnal LONE/ACMBB is:

[ONE/ACPNBB=(27T-NSA1. (ROP 1 +ZTNSAO+ZTNSA2) ((FDUACT. F-R-DP 1) +FLDCOMPL - MR. ZLNADJ7. ZI-NADJ8. ZI-AND^) +(27M1P (ROP 1 +ZTNSBO+ZTNSBU. (FRDP 1. FILDCOMPU An ATIVIP adder 730-30 calculates the number of zeros to the right of the least significant digit of the operand with the larger scale factor. The ZASFB switch 730-28 selects the adjusted scale factor binary signals ASF 0-9 which are added to the quantity 63 if the operand 2 scale factor is larger or subtracted from the quantity 63 if the operand 1 scale factor is larger. The output signals ATIVIP 3-9 are loaded into an RTMP register 730-100. Bit positions RTMP 0- 3 store a binary count of the number of words of the operand to the left of the word containing the least significant digit position. Bit positions RTMP 4-6 store a binary number indicating the least significant bit position.

Signals RTMP 4-6 indicate the number of zeros to the right of the least significant digit.

A comparator 730-104 compares signals RTIMP 0-3 and RLIVIP 0-3. The difference equals the number of words of the operand to be received by the decimal unit 730 from cache 750. The binary 50 word count RLIVIP 0-3 is incremented each time a word of the operand is loaded into the RDOD register 730-154. The difference between binary signals RTIVIP 0-3 and RLIVIP 0-3 is zero when the last word of the operand is received in the decimal unit 730 thereby enabling the A=B output signal of the comparator 730-104. This enables the TMSC 0-3 output of TMSC logic control 730 106 which is a binary count of the number of zeros to the right of the least significant digit. This count 55 is applied to the TMSC logic control 730-106 by signals RTMP 4-6. The TMSC 0-3 count is applied to a Z1DIVIL shifter 730-120. The number of low order digit positions to the right of the least significant digit to be forced to ZERO is indicated by the number of successive signals starting with the ZIDML 7 signal which are forced to ZERO. The Z1DIVIL 0-7 signals are applied to the [EZID 0-7 logic control 730-132. The output signals [EZID 0-7 reflect the ZMIDIL 0-7 signal states and enable the 60 high order positions of the Z11) switch 730-150, forcing the low order positions to the right of the least significant digit to ZERO.

The ASFA 33-36 signals are received from the address preparation unit 7043 for operands 1, 2 and 3 and are stored in registers RCPO, RCP 1 and RCP2 respectively of a register bank 730-42.

17 GB 2 115 586 A 17 The ASFA 33 signal indicates the least significant bit of the cache 760 address of the high order word of the operand indicating whether this word isom an odd or even memory address location. This is used in the compacting of operands having 9-bit characters which are received in the decimal unit 730 as 4 decimal characters per word to 8-decimal digits per word, which is sent to the execution unit 714.

For 9-bit character operands, signals ASFA 34 and 35 indicate the position of the leading character in the high order word of the operand. For 4-bit character operand words, signals ASFA 3436 indicate the position of the leading character in the high order word of the operand.

The operand pointer stored in register RCPO is selected through the IRCP0 position of a WPA switch 730-44 and applied to a ZCPNB switch 730-48. The MPA 0-2 position of the ZWNB 10 switch 730-48 is selected if operand 1 comprises 9-bit characters and the WPA 1-3 position is selected if operand 1 comprises 4-bit characters. Signal [ONE/ACPNBB is applied to an input of the AWNB adder 730-50 and is added to the ZCPNB 0-2 withals if operand 1 has a leading sign. This is indicated by the 1 -bit of the RTNSO register being a ZERO. The AWNB 1-3 output of the adder points to the most significant decimal digit position of the high order word of operand 1 as it is received 15 in the decimal unit 730 from cache 750.

An AWDF adder 730-52 subtracts the high order digit position from the ACPR 7-9 signal output of the ACPR adder 730-62. The ACPR 7-9 binary signal indicates the number of ZER0s to the left of the most significant digit in the operand high order word to be transferred to the execution unit 714. Subtracting binary signals ACPNB 1-3 from ACPR 7-9 in the AMF adder 730-52 gives an output binary value signal AMF 0-3 which is the amount the operand being received from cache 750 is shifted to be properly aligned for transfer to the execution unit 714. This shift value is stored in an RDSC register 730-58 through a switch 730-56. The output of the RDSC register 730-58 is applied to a shifter 730-156 through a MSC switch 730-72. The AMF adder 730 52 calculation is made separately for operand 1 and operand 2 and aligns the operands relative to each 25 other for numeric processing in the execution unit 714.

A WPM switch 730---46selects the operand character pointer for 4-bit and 9-bit character operands and applies it to an ACPWC adder 730-66 where a quantity ONE is subtracted to give an output signal ACPWC 0-3. A ZLNT switch 730-64 selects the operand 1 length for the operand 1 load and the operand 2 length for the operand 2 load for input to an ASWC adder 730-68 where it is 30 added to the ACPWC 0-3 binary signal. A ZSM switch 730-70 selects an ASM 0-4 switch position for a 9-bit character operand and an ASM 0-3 switch position for a 4-bit character operand and applies the ZSM 0---4binary output for storage in an RSWC register 730-110.

The RSWC register 730-110 stores a binary count of the number of words in the operand to be transferred from cache 750 to the decimal unit 730. The count in the RSWC register 730-110 is 35 decremented by a [CNTDWN-RSWC signal each time a word is received in the RIDID register 730 158. The boolean expression for the signal is:

[CNTDWN-RSWC=((L-DR-RV7M(FDID. (FOP 1 LID+FOP2LID) DECU+[$1RIDODA. (DUCIVID 303+FOPST13M [LDRRWC=(FDUACT. FRIDP j +SFOP2LID +FLIDCOMPIL. (-FUOP-STR+DUCMD 30-51) DFCO=_RSWUM. RUW. RUW-W. RSWC3. R5W% [$RDODA=(FDATA-AV+DUCMD 203+DUCIVID 310 +DUCIVID 309+FRPK. DUCIVID 303+9-RP-K.'9-A-LT FSWIRT). 50-CMD 311 The RSWC register 730-110 at zero indicates that all the words of the operand have been received by the decimal unit and the DFCO signal output sets the FIDFID flag in status flag control logic 730-202.

The ARWC adder 730-60 output signals ARWC 0-6 are stored in an RRWC register 730---88 when the [LDRRWC signal is at logical ONE. The RRWC register 730-110 stores the number of words 50 in the operand to be transferred to the execution unit 714 during the load operation. Each time a word of an operand is loaded into the RDOD register 730-154, the RRWC register 730- 110 is decremented by one when the [CUTDWN-RRWC signal is at logical ONE. The boolean expression is:

[CNTDWNRRWC=(DTECO. (FOP 1 LID+FOP2LID). [$RDODA +(WOPSTR+DUCIVID 303. (DMSDRGTE +MD-MSEQ. RIDSCOM. FALT. (-F-SWRT DIVISDRUE+(ZTNSA0. FCIPCO+ MSA0) FSWIRT)). FR-PR+WK. DUCIVID 303 WT1NWA-0. FCPCO+MSAM) IDTECO=RIRMO. RRWC 1. HIRWU2. 1IT-R-WC3. RRM4. RR-W-U59. RRWC The RRWC register 730-110 at ZERO indicates that all the decimal digits of the operand have been sent to the execution unit 714 by the DTECO output signal setting the FIDTED flag in status flag control logic 730- 202.

GB 2 115 586 A 18 The FOP 1 LD flag is set by the firmware initiating a DUCMD 301 signal indicating a "READ Operand through Decimal Unitoperation. The FOP 1 LD flag is reset when the DFCO and DTECO output signals indicate that both the RSWC register 730-110 and the RRWC register 730-88 respectively have decremented to ZERO during the operand 1 load operation. The FRDP 1 flag set indicates that the 5 DUCMD 301 has been issued to read operand 1 through the decimal unit 730.

The F0P2LD flag is set by the firmware to read operand 2 when the DUCMD 301 has been issued with the FRDP 1 flag set. The F0P2LD flag is reset and the RLDCOMP flag is set indicating that the load operation is complete when both the RRWC and RSWC registers have decremented to ZERO during the operand 2 operation, i.e., both operands 1 and 2 have been processed in the decimal unit 730 and transferred to the execution unit 714.

An RI-M register 730-96 and an RLZC2 register 730-98 are used to indicate to the firmware the number of zeros to the left of the most significant non-zero digit in operand 1 and operand 2 respectively. Rpq:ister positions RLW 1 1-3 and RLX2 1-3 are loaded with the ARWC 4-6 output signals of the ARWC counter 730-60. This essentially preblases the word count portion of the R] 7C1 and RLW2 registers, bit positions RI-M and RLW2 0-3 with the value of 7 words minus the number of words to be sent to the execution unit (binary value of the ARWC counter 730-60 bit positions ARWC 4-6) and equals the number of words not being sent to the execution unit 714. The number of leading zeros to the left of each operand is sensed at the output of the Z0 730-150. The TI-D- 04-35 signals are applied to the load zero count logic 730-182 and the output LW 0-3 indicates the number of leading zeros in the word. Signal LWO being a ONE indicates that all the decimal digits of the word are zero, a ONE is added to the RI-M or RI-M2 registers at the bit 3 position and the next word is received from cache 750. Again, if the word contains all zeros then signal LCZO is a ONE, a ONE is again added to the bit 3 position and the next word is received from cache 750. Assume that the next word received from cache 750 does not contain all zeros, then the signals LW 1-3 indicate the number of zeros to the left of the first non-zero decimal digit. This sets an FZW 25 flag indicating to the logic that the ZERO to the left count is completed for this operand. This count is transferred through a ZEDC switch 730-82 to the RI-M and RLW2 registers and stored in bit positions RLW 14-6 and FILW2 4-6 for their respective operands.

The binary values stored in the RILM register 730-96 and RLX2 register 730-98 are the count of the number of decimal digit positions to the left of operands 1 and 2 respectively to fill the 64 decimal digit positions set aside in the execution unit 714 for each operand.

The output of the RI-M and RLW2 registers are transferred under firmware control through a ZLZC switch 730-76 position 3 of the Z0 switch 730-150, through the MOD switch 730-152 to the RDOD register 730-154. The ARWC signal input to the MC switch 730-76 provides the number of words transferred for a long operand. The ATIVIP signal input provides the word location to which the rounding constant is added. The boolean expressions controlling the RWC1 register 730 96 and the RWC2 register 730-98 for loading the low order positions of the registers are:

[$RLWIL=([$RDODA. FOP 1 LD. F21a+(DUCIVID 305 +FCZO). D-RIMM [$RLX2L=([$RDODA. F0P2LD T-ZC-F+(DUCMD 305 +FCZO). DEDCZ) The boolean expressions for loading the high order positions of the registers are.

[LDRLZC1 U=SIFOP 1 L13+(DUCIVID 305+FCZO). UE-DW [LDRLZC2U=SFOP2LD+(DUCMD 305+FCZO). D= DEUC-MED-M. -ED-C-T. E5MC2. E-DET The registers are incremented by:

[CNTUPRI-M U=[$RDODA. FOP 1 LD. FZW - LWO [CNTUPRI-M2U=[$RDODA. F0P2LD. FECT. LWO SFOP 1 LD=(DUCMD 301. FRDP 1. FPGA. (D1 EGOW. D2E GOVP 50. LONG+FWP M 50 SFOP21-13=WOP 1 LD. TM-M (DUCMD 301 +FRDP2) (DFCO MID. DETECO. [$RDODA+DI7CO. 17DID. FDTED +DTECQ. [$RDODA - FWD)+FOP1 LD. F DUCMD 301. FRDP 1) FPOA) D1 EQ0VP=WBITR. ROP1. fT-N9AO-) 55 D2EQ0VP=WBITZ. ROP 1. S130) LONG=ALWAGTE1 6+Al-NDI3GTE1 6+ALNSGTE1 6 FM---YDV+Dl EWLP+132EMP ALNDAGTE1 6=ALWA1 +Al-NDA2 ALNDI3GTE1 6=ALNDB 'I +ALNDB2 60 ALNSGTE l 6=ALNS3+ALNS4+ALNS5 Decimal unit-load operation Operands are transferred from cache 750 to the decimal unit 730 over signal bus ZDl 0-35 and are loaded into an RDID register 730-158 under firmware control. The firmware initiates a DUCMD i 1 19 GB 2 115 586 A 19 301---ReadOperand Through Decimal Unit- command. This sets the FRDP1 andtheFOP1LDflagsto condition the decimal unit 730 logic to receive operand 1 from cache 750.

The FISM register 730-110 is loaded with the number of words to be received from cache 750. The RRWC register 730-88 is loaded with the number of words to be sent to the execution unit 5 714. The RSWC register 730-110 is decremented by ONE for each word received from cache 750. The RRWC register 730-88 is decremented by ONE for each word sent to the execution unit 714. The boolean expressions for the loading and decrementing the RSWC and RIRM registers 730-110 and 730-88 respectively are:

[LDRSWC=((FDUACT. FRDP 1 +WILDCOMPIL. DUCMD 30 - FOPSTR+SFOP2LD) [CNTDWNRSWC=(-(L-DR-R-W---C, (FDID (FOP 1 ILD+FOP2LM 7. - DFCOA$RDODA..MUCIVID 303+17OPSTRffi [LDRRWC=(FDUAdt. FR5P' +SFOP2LD+ FLDCOMPL (FOPSTR+DUCIV1 [CNTDWN-RRWC=(-D-TECO - (FOP 1 LD+FOP2LD) - [$RDODA 15 +((FOPSTR+(DUCMD 303 (DMSDRGT +(DMSE RDSCOM)-FT_L_T-FF-9W_RT DMSDRGTE+(ZTNSA -FCPCO+ZTNSAO) FSWRT)) - FRFK+FRPK - DUCIVID 303 (ZTNSAO - FCPCO+ZNT SAO)) 20 The FOP 1 LD flag is reset on the cycle following the RSWC and RRWC registers counting down to zero by the DFCO and DTECO outputs at logical ONE. The boolean equations are listed supra. This indicates that all of the operand 1 words have been received by the decimal unit 730 and sent to the execution unit 714. The firmware initiates another DUCIVID 301 command which sets the FOP2LD flag since the FRDP 1 flag is still set conditioning the decimal unit 730 to receive operand 2 words. Again 25 the RSWC register 730-110 and the RRWC register 730-88 are loaded with number of words received from cache 750 and sent to the execution unit 714 respectively and counted down to zero indicating to the decimal unit 730 that operand 2 was received, processed, and transferred to the execution unit 714. The FOP2LD flop is then reset.

The operand may conta in 4-bit or 9-bit decimal digits. Operands containing 4-bit decimal digits 30 are processed through the decimal unit 730 differently from operands containing 9-bit decimal digits.

Assuming that the operands contain words with 4-bit decimal digits and the first word is stored in the R-DID register 730-158. Control signal [1 ZPK is forced to a ONE selecting the 1 position of a ZPK switch 730-160. The RDID 0-35 output signal is compacted from a 36 bit word to a 32 bit word in the selected position 1 of the ZPK730-1 60 switch and outputs as sig.Lal bus ZPK 0-31 which may 35 indicate up to eight 4-bit decimal digits. The negated output signal bus ZPK 0-31 is stored in an RPK register 730-162. The decimal digits of this data word are the high order digits of the operand. If the decimal digits of the first word of the operand outputting the ZPK switch 730-160 have a sufficient number of decimal digits to be sent to the execution unit 714 as specified by the decimal unit 730 logic then the necessary switches are conditioned by their respective control signals -to load the RDOD 40 register 730-154. In this case the ZPK 0-31 output signals are selected through a ZPKR switch 730-164. The output signals ZPKR 0-31 are applied to the shifter 730-156 where they are shifted to the right an amount specified by the ZDSC 1-3 binary shift count output of the RDSC register 730-58. The ZDS 0-31 output signals are applied to a ZID switch 730-150 where non decimal digit characters such as signs and exponents and also non-operand replacement characters are 45 replaced by zero under control of the [EZID 0-3 ZID switch enable signal output of the [EZID control logitc 730-132. Thp output signals ZID 4-36 are selected by position 0 of the MOD switch 730-152. MOD 4-35 output signals are stored in the RDOD register 730-154.

If the data word made up of 4-bit digits will not fill a sufficient portion of the RDOD regi ster 730-154 for transfer to the execution unit 714, then the first word remains stored in the RPK register 50 730-162 and the next data word of 4-bit digits is transferred from cache 750 to the RDID register 730-158 under firmware control. The second data word is applied to the shifter 730-156 through the ZPK switch 730-160 and the ZPKR switch 730-164. The first data word stored in the RPK register 730-162 is applied to the shifter 730-156 through a ZPKL switch 730-166. The shift count signal ZDSC 1-3 selects 32 of the 60 inputs to the shifter 730-156. The ZDS 0-31 output 55 signals are stored in the RDOD register 730-154 through the ZID switch 730-150 and the MOD switch 730-152. Necessary zeros to the left and right are added to the ZDS 0-31 shifter output under control of the [EZID 0-7 enable signals while the operand word is switched through the ZID switch 730-150.

If the operand from cache 750 to the decimal unit 730 consists of a 9-bit decimal digit the first 60 data word containing a maximum of 4 decimal digits is stored in the RDID register 730-158. The 9 bit decimal digits are stripped of the 5 high order bits of each decimal digit and compacted as the word is switched through the selected 2 position of the ZPK switch 730-160 and are stored in either the GB 2 115 586 A 20 left 16-bits of the RP K 0-15 register 730-162 if from an even address in cache 750 or are stored in the right 1 6-bits of the RK 16-31 register 730-162 if from an odd address in cache 750.

If a data word may be made up to send to the execution unit 714 then it inputs the shifter 730156 through the M switch 730-160 and the MR switch 730-164. Note that the decimal digits are repeated in ZPK 0-15 and WK 1631 switch position 2 as the digits pass through the SPK 031 switch. The extraneous digits, the sign, exponent and rewrite digits are stripped from the data word in the Z11) 730-150 switch. The MS 0-31 output of the shifter 730-156 is stored in the RDOD register 730-154 through positions 0 of the Z11) switch 730-150 and the MOD switch 730-150 and the MOD switch 730-152.

Assuming that the first data word comprising 9bit characters was received from an even cache 10 750 address and stored in RK 0-15 register 730-162, the second data word would be received from an odd cache 750 address and would be stored in the RK 16-31 register 730-162.

The second data word is applied to the shifter 730-156 through the ZM switch 730-160 and the ZPI(F1 switch 730-164 after being stripped of the high order 5-bits of each 9-bit decimal digit and packed into both halves of the WK 0-31 data word. The first data word stored in either the odd address or even address half of the RK register 730-162 is applied to the shifter 730-156 through the ZPKL switch 730-166.

Control signals [1 ZPK and [2ZM select one of four positions of the ZPK switch 730-160. Position 0 is selected for the store operation, position 1 for the 4-bit digit operand, position 2 for the 9- bit digit operand and position 3 for the rounding operations. The boolean expression, are:

[1 ZM=ZTNSA0. FOP 1 LID+ZTNS130. FOP21-13+DUCIVID 309 [2 ZPK=MSA0. FOP 1 LID+fTT-NS15-0. FOP2LID+DUCIVID 309 Control signal [$RPKU enables the loading of the RPK register 730-162, positions RK 0-15 for 9-bit operandsfrom an even cache 750 address, and 4-bit operands. Control signal [$RPKL enables loading of RK register 730-162, positions RK 16-31 for 9-bit operands from an odd cache 750 25 address, and 4-bit operands.

The boolean equations are:

[$RPKU=DUCMD 305+FIDID. (ZTNSAO FOP 1 LD +ZTNS13O.FOP2LID+MSA FOP1LD FCPCO +ZTN59-0-. F0P2LD. FC-P-CO) +FRPK. FOPSTR. rFALT. FSWRT+FALT FSWU - FSW) [$RPKL=DUCMD 305+FIDID. (ZTNSAO. FOP 1 LD +ZTNSBO.FOP2LD+ZTNSAO.FOP1LD FCPCO+ZTNSBO.FOP2LD.FCPCO) -;F-WRP-K. FOPSTR. (-FALT. FSWRT +FALT. FSWRT. FSI\IM) Controlsignals [OZPKLand [0ZMR enable respectively the ZM switch 730- 166andthe ZKR switch 730-164. Control signal [1 ZPKL, at logical ONE selects the ZM 4-31 bit positions from ZPKL switch 730-166 and the F112K 16-3 1 bit position from ZMR switch 730-164. Control 40 signal [1ZPKRU, at logical ONE,seiectstheRM0-15 bit positions of the ZPKR switch 730-164.

* [OZPKA=FOP 1 LID+FOP21-13+(FOPSTR+DUCIVID 303) - (FRPK. (DMSDREQJ 0. RIDSCO+LMSDREWM 1.f-DSCO)+F PKFMSDRN.(DMSDRLTMI + FMSDRGTE. DIVISDRUM2). FIVISEW) [WKR=FOP1 Ll)+FOP2 LD +(FOP STR+DUCIVID 303) (FRPK. (DIVISDREQ21. RIDSCO+DIVISIDREQ1 0 RIDSCO)+FR-R - F-A SDRM. (FMSDRGTE DiVISDRI-TNI1 +fFR-W--M. DIVISEQ)+DUCIVID 309 FRPK+Dl EUFLF+ (ATIVIP 0-0). FRCIVID +(ATMP 0 - 1. 2. j. 4. 5. 6). FRCIVIM) 11 ZKR=WIVISIDRQEQ1. FIDSCO+13TECO. RDSCO). FRPK. (FOPSTR+DUCIVID 303) [1ZPK13U=WOP1 LD. Z-f NSA0+FOP21-1). ZTNSBO) RDSC1 +WOPSTR+DUCIVICID 303). FR12K (DMSDRWEG1. RIDSCO+DTECO. FIDSM DIVISIDREQ1 O=DTECO+DIVISIDRWEG1 DM SID13WEQ1V1 1 =RRWCO. FFWC 1. RRWC2. RRWC3. RRWC4. RRWC5. RRWC6 DIVISDREGOM 1 =DTECO+DMSDRWEQM2 DIVISDRI-TIV1 1 =RRWCO. DiVISDRWEGM 1 DMSDRLTM2=RRWCO. (RRWC1. RRWC2. RRWC3. RRWC4. RRWC5) DMSDREQ21 =DMSDRWEQ2+ DMSDRWEQ1 DTECO =RRWCO. RRWC 1. RRWC2. RRWC3. RRWC4. RRWC5. RRWC6 21 GB 2 115 586 A 21 DIVIS RWEQ1=RRWCO."R--WCl.RRWC --RWC3.RRWC4.RRWC5.RRWC6 DMSDRWEQ2=RRWCO. RRWC1.RRWCY.RRWC3.RRWC RRWC5. WC6 The boolean expressions for the control signals that condition the operand words during both the load and store operation are as follows: [1 Z1 D=DUCIVID 203+DUCIVID 31 0+ DUCIVID 311 +FRPR. FRCMD. DUCIVID 309 [M D 0-7=DUCIVID 31 0+DUCIVID 311 + (FRPK. FRCIVID. DUCMD 309)+WRIDG-MASK [1ZDODO=([STRPKD=[UNPKDLWR+ [UNPKDUPR USIVIRO+[2ZSIVIR0) [1ZDOD1=([STRPKD+[UNPKDLWR+[UNPKDUPR ([1ZSMR2+[2ZSMR2) [1ZDOD2=([STRPKD+[UNPKDLWR+[UNPKDUPR ([1ZSMR4+[2ZSMR4) [1ZDOD3=([STRPKD+[UNPKDLWR+[UNPKDUPR ([1ZSMR6+[2ZSMR6) [2ZDODO=(4STRPKD+ [UNPKDUPR+[UNPKDLWR ([1ZSMRO+[2ZSMRO)) [2ZDOD1=(4STRPKD+[UNPKDUPR+ [UNPKDLWR ([1ZSMR2 +[USMR2)) [2ZDOD2=(4STRPKD+[UNPKDUPR+[UNPKDLWR ([1ZSMR4+[2ZSMR4)) [2ZDOD3=(4STRPKD+[UNPKDUPR+[UNPKDLWR ([1ZSMR6+[2ZSMR6) [USIVIR 0-7=SIGNIVIASK+REWUM 0-7+REWLIV1 0-7 [MIVIR 0-7=EXMASK+REWUM 0-7+ REW1-M 0-7 [STRPI(D=(ZTNSA0 (DUCIVID 303+FOPSTM) [UNPKDLWR=CZ-TfN-SAO (DUCIVID 303+FOPSTR). FCPCO) [UNMDUPR=(2TIMSA (DUCMD 303+FOPSTR). FCPC) An ACPR adder 730-62 calculates the number of zeros digits to the left of the operand necessary to fill a 64 digit block of storage. The adjusted length ZI-NAW 0-9 output of switch 730 26 is subtracted from 64, the maximum number of digits that will be transferred between the decimal unit 730 and the execution unit 714. The output of the ACM adder 730-62 is stored in the RLIVIP 25 register 730-102. The RLIVIP 4-6 output signals, the low order 3-bits, store the number of 4-bit decimal digit positions to the left in the high order word to be forced to zero and is applied to the shift count input of a MMU shifter 730-130. Those output signals ZIDMU 0-7, which indicate zero digits to the left, are forced to ZERO.'This forces the indicated outputs of [EZID logic control 730-132, signals [EZID 0-7 to ZERO thereby forcing the selected digit positions of the ZID switch 730-150 to 30 ZERO of the first word of the operand received by the decimal unit 730. If the operand had a leading sign, it would have been replaced by ZERO in the ZID 730-150 switch since the sign character position count was subtracted from each operand length in adderr, ALNIDA 730-18 and ALNDB 730-20 respectively. Also, rewrite characters in the operand word would be replaced by ZERO's.

An ATMP adder 730-30 calculates the number of zeros to the right of the least significant digit 35 position of the operand having the larger scale factor. Switch ZA5F13 730- 28 selects the number of zeros to the right for operand 1 or operand 2 during that cycle in which the operand transfers from cache 750 to the decimal unit 730.

If the operand 1 scale factor is larger than the operand 2 scale factor than the ASF 0-9 input to switch ZASIF13 730-28 is a positive number which is subtracted from 63 in the ATIVIP adder 730-30 40 and the difference, output signals ATMP 3-9, are stored in an RTIVIP register 730-100. The low order positions RTIVIP 4-6 input a TMSC logic control 730-106 and output as signals TMSCO-3 which are applied to the shift count input of a MMIshifter 730-128. This forces the ZIM 0-7 output signals to indicate the number of digit zeros to the right of the operands. The ZI1DIVIL 0-7 output signals are applied to the [EZID logic control 730-132. The [WID 07 output signals condition the indicatgd low order digit positions of the Z11) switch 730- 150 to ZERO thereby stripping trailing sign, exponent, and rewrite characters from the operand word.

Signals RTIVIP 0-3 the output of register 730-100 and signals RLIVIP 0-3 the output of register 730-102 indicate the cycle on which the operand word which requires the ZER0s to the right is transferred from the decimal unit 730 to the execution unit 714. The 64 decimal digit maximum transfer is made up of eight words of 8-decimal digits per word. Signals RLMP 0-3 are a binary representation of the number of words to the left of the word containing the most significant digit that contains all zeros. Signals RTMP 0-3 are a binary representation of the number of words in the maximum transfer minus the word in which ZER0s to the right are forced. Plus 1 is added to binary signals RLIVIP 0-3 each time register RDOD 730-154 is loaded. Signals RTIVIP 0-3 and RI-MP 0 3 are compared in a comparator 730-104. Signals TMSC 1-3 are forced to ZERO on the cycles where binary signals RTIVIP 0-3 is greater than binary signals RLW 0-3 ZER0s to the right are forced in the ZID switch 730-150 on the transfer cycle where comparator 730-104 indicates that the binary values of RLIVIP 0-3 and RTMP 0-3 are equal.

Control signal [$RTMP enables the input loading of RTIVIP register 730100, and the RLIVIP 4- 60 6 bit positions of the RLW register 730-102. Control signal [$RTIVIP enables the output of the RI-MP 0-3 bit positions of the RLMP register 730-102.

22 GB 2 115 586 A 22 Control signal [ZERO/RLIVIPIL enables the output of the RILIVIP 4-6 bit positions. Control signal [CNTUP-RLIVIP1) increments the RILIVIP 0-3 bit positions. The boolean equations are:

[$RTMP=(FDUACT. FIRD9-1 +SFOP21-M [ZERO/RLIVIP L=(FFDO+ (FOP 1 ILD+FOP2LM. [2-Z--IDA)) [CNTUP-RLIVIPU=(WOP 1 W+FOP2LM. [$RDODA. SFOP2LD) Decimal unit-Figure 3--store operation The FPOP3 cycle loads descriptor 3 information into register RSIR 704-154 for a 3 descriptor instruction. In decimal arithmetic instructions, descriptor 3 defines the field into which the results of the calculation of the descriptor 1 and descriptor 2 operands are stored. Some instructions store the result of the descriptor 1 and descriptor 2 operand calculations in the field defined by descriptor 2. In 10 either case the RSIR register 704-154 stores the descriptor information and transfers it to the decimal unit 730 for the store operand 3 operation. The decimal unit 730 receives operand 3 from the character unit 720 over the RCHU 0-35 signal bus. The decimal unit unpacks it, adds the sign and exponent if required, positions the operand 3 digits within the word, places the proper number of zeros to the left and right of the operand, adds required ASCII or EBCDIC zone bits and reinstates the portion of the first and last words of the operand that are not defined as part of the operand. The decimal unit 730 sets up the necessary controls in the logic to receive operand 3, manipulate it and store it in cache 750 in conformance with its descriptor information.

The operand 3 scale factor signals RSIR 24-29 inputs switch ZSFN 730-2 and are stored in register RSF2 of register bank 730--4. For the case where the input operands were such that the decimal unit 730 did the scale factor alignments, the ZSFA switch 730-6 selects the contents of the RSF2 register, and the ZSFB switch selects the contents of either the RSFO or RSF1 register of register bank 730-4. The register selected is the one storing the smaller scale factor of operand 1 or 2. The FSSFD flag which is set by the scale factor comparison during the load operation makes the selection.

Control signals 4WRRSF1 and 4WRRSF2 select 1 of the RSF 0-4 registers 304 in which the 25 scale factor is stored. The boolean expressions are:

[WRRSF1 =((F3DESC+FMVN) FLI)COMPL - FWP - D1 EQFLP) CMD 305 - FCZO)+RDESC1 - FPOP+(FMYDV +FPTL+FPFL) DUCIVID 308 - D 1 EQFLP (F VN+F31)ESC) - FPOP FILDCO PL [WRRSF2=((FMYDV+FPTL+FPFL) DUCIVID 308. FPOP. FILDCOMPIL UT-E-WLP (FMVN+F3DESC)+RDESCO. FPOP+ (F3DESC+FMVN) FILDCOMPL. FPOP. D 1 E0FILP) The ZSFB switch 730-8 ouiPut is subtracted from the ZSFA switch 730-6 output in the ASF adder 730-10. The ASFO-9 output signal inputs the ALNS adder 730-24 and is also stored in the 35 RSCLM register 730-144 where it serves as a pointer to the least significant end of the data to be actually stored.

For a floating point store operation, the RSF3 register of register bank 730-4 stores the adjusted length output of the AI-NDA adder 730-18 and the RSF2 register holds the effective digit counts of the internal results the first time the count is taken, i.e., the output of the AEDC adder 73086 and the ZEDC 1 -3 output of the ZEDC switch 730-82 inputting the ZWN switch 730-2. In this case the contents of the RSF3 register is selected through the ZSFA switch 730-6 and the contents of the RSF2 register is selected through the ZSR switch 730-8 and are subtracted from each other in the ASF adder 730-10. Again the ASFO-9 output is applied to the input of the ALNS adder 730-24 and the RSCILM register 730-144. However, for the purposes of obtaining the zero or 45 effective digit count, the first time the operand is examined, the contents of the RSCLM register 730 144 are over written in forming up the inputs to the output zero and overflow detection logic 730-80.

After the first count, if the number of effective digits is greater than the adjusted length of operand 3, the decimal overflow flag FDOFL will be set and the calculation of the effective digit count from RSF2 register contents minus the adjusted length from the contents of the RSF3 register will be enabled at 50 the output of the RSCLM register 730-144 for a subsequent zero and overflow examination.

The length field signals RSIR 30-35 are stored in register RI-ND2 of register bank 730-12 and are switched through the RI-ND2 position of the ZI-NDA switch 730-16 to input the Al-NDA adder 730-18.

Control signals [1 ZSFA and [MFA select the outputs of the RSF 0-3 registers 730-4 for 55 application to the plus input of ASF adder 730-10. Control signals 1 ZSFB and MM select the RSF 0-3 outputs for application to the minus input of ASF adder 730-10.

The boolean expressio s are:

;1!:"

1 [1 ZSFA=F3DIESC. FILDCOMPL. (FMVN. D1 E0FILP) [=FA=F3DESC. FILDCOMPL+ FIVIVN. FILDCOMPIL. F J E0FI-P [1ZSFB=FMVN. FLDCOMPL+FMVN.,FSSFD. FLDCOMPL. (F3DESC+FIVIVN) 23 GB 2 115 586 A 23 - D1 EMP. (FMYDV+FPTL+FPFL) +FILDCOMPL. (F3DESC+FMVN). D1 EMP +FLIDCOMPL. (F3DESC+FMVN). D1 EMP. (FMYDV+FPTL+FPFL)+FLDCOMPL. T-WESC +FM-VN) [MF13=FLDCOMPL. (F3DESC+FIVIVN). D1 EQ171-P 5 +FLIDCOMPL. (F3DESC+FIVIVN). D1 E&LIP (FMYDV+FPTL+FPFL) The sign and decimal type signals RSIR 21-23 are stored in register RTNS2 of register bank 730-32 and are transferred through the RTNS2 switch position of the ZTNSA switch 730-36 to the decode logic 730-38 where the correction factors to the length are determined. If operand 3 is a 10 nine-bit floating point number then 2 digits are subtracted from the length. If operand 3 is scaled with a leading or trailing sign then 1 digit is subtracted from the length. A four-bit floating point number will have 3 digits subtracted from the length. The boolean expressions for signals DBITX and IDLEOFI-P which are applied to the ALNIDA adder 730-18 and the ALNDB adder 730-20 were described supra.

The output of decode logic 730-38 is applied to the other inputs of the ALNIDA adder 730-18 and subtracts from signals ZI-NDA 0-5. The output of the ALNIDA adder, signals ALNIDA 0-6, adjusts the length to indicate the number of decimal digits in operand 3. The ALNIDA 0-6 output signals are applied through the ZAI-ND switch 730-22 to the input of the ALNS adder 730-24. The scale factor signals ASF 0-9 are added to the ALNIDA length and the output signals ALNS 0-9 is the adjusted 20 length of operand 3. The output ALNS 0-9 is applied through the zero position of the ZI-NAW switch 730-24 to input adders ARWC 730-60 and ACPR 730-62 and is stored in an RSCUM register 730-78. Adder ACPR subtracts the adjusted length ZLNAW 3-9 from 64 and its output signals ACPR 3-9 indicates the position of the most significant digit to be stored within the internal result field. Signals ACP13 7-9 indicate the position of the most significant digit within the word of the operand containing the most significant decimal digit. The signals ACPR 7- 9 are applied to the input -of the ACPSC adder 730-54.

The output of the ARWC adder 730-76, signals ARWC 0-6 are applied to the RRWC register 730-88 and indicates the location of the operand word containing the most significant digit to be transferred from the decimal unit 730 to cache 750. A ONE is added to the ARWC adder in the case of 30 operand 3 having a leading sign which would result in another word being transferred to cache 750.

For the floating point operation during the first examination for zero or overflow, i.e., the DUCIVID 304 check zero overflow command and for any subsequent examinations for which the overflow flag FDOFL has not been set then the ALNDA adder 730-18 output is selected through the ZINADJ switch 730-26. If on a floating point output result the decimal overflow flag FDOFL had been set then the 35 ALNS adder 730-24 output is selected through the ZI-NAW switch 730-26. The ALNS adder 731-24 forms the difference between the adjusted length output of the ALNIDA adder 730-18 and the effective digit count minus the adjusted length from the ASF adder 730-10 output.

The starting character pointer signals ASFA 33-36 are stored in register RCP2 of register bank ' 730-42 and are selected by the RCP2 switch position of the MPA switch 730-44. Signal WIPA 40 0-3 inputs the ZCPNB switch 730-48. If operand 3 is made up of 4-bit characters then signals WPA 1-3 are selected and if operand 3 is made up of 9-bit characters then signals WIPA 0-2 are selected as the output signals ZCPNB 0-2 to input the ACPNB adder 730-50. A ONE is added to the ACPNB adder if the operand has a leading sign. The output signals ACPNB 0- 3 are applied to the input of an ACPSC adder 730-54. Switch 730-56 by means of the FLIDCOMPI- status flag selects 45 signals ACPSC 0-3 for storage in register RDSC 730-58. The ACPSC adder 730-54 subtracts the most significant digit position within the internal operand word as indicated by the ACPR 7-9 signals from the digit position within the in storage word of the most significant digit as indicated by the ACPNB signal to give the value of the number of digit positions the operand to be stored is shifted. This value represented by signals ACPSC 0-3 stored in register RDSC 730-58 is the shift count for the 50 MS shifter 730-156.

The ASWC adder 730-68 output signals ASWC 0-6 provides input signals to ZSM switch 730-70, Z1RLIVIP switch 730-112, ZSW switch 730-116 and the ZEMP switch 730-120. The outputs of the switches are applied to shifters 730-114, 730-118 and 730- 122. The shifter outputs are applied to control [USIVIR logic 730-142 and control [2ZSMR logic 730-146 for generating the [1 ZSMR 0-7 and [MIVIR 0-7 signals. These signals are applied to the ZSMR switch 730-180 for loading the sign, exponent and rewrite characters into the operand 3 words. The starting character pointer signals MPA 0-3 are applied to the input of switch 730- 46 whose output, signals ZCPWC 0-2 are derived from signals WIPA 1-2 for a 9-bit character operand and signals WPA 1 3 fora 4-bit character operand. Signals ZCPWC 0-3 are applied to the input of adder ACPWC 730- 60 66. The decimal digit ONE is subtracted and the output, signals ACPWC 0-3 are applied to the input the ASWC adder 730-68. The length field of operand 3, signals ZI-NDA 0-5, are added to the starting character pointer minus ONE to indicate the character pointer for the last decimal character in the operand.

24 GB 2 115 586 A 24 The first word of operand 3 is received from the character unit 720 over signal lines RCHU 435, through buffer 730-168 which generates the assertion signals RCHU 4-35 and the negation signals RCHU 4-35.

Control signals [UPK and [2ZM select the zero position of the ZM switch 730-160 and RCHU 5 4-35 appear at the output of the switch as signals ZPK 0-31 and ZM 0-31.

For the long operand, that is operands greater than 15 decimal digits, the operand is transferred from the RCHU 720-10 a word at a time with the word containing the most significant decimal digits being transferred to the decimal unit 730 first.

If a sign is required for the operand, the firmware loads the RSGN register 720-134 over the ZADSP 3-11 signal lines from the auxiliary arithmetic and control unit 722 in response to a DUCMD 10 307 command---Loadthe DU Sign Register---. The output of the RSGN register 730-14 is applied to selected position 1 of the ZSIVIR switch 730-180. The character location in ZSMR switch position 1 is selected as follows. The output of the ASM adder 730-68 points to the low order character position of a trailing sign. The output of the XPA switch 730- 44 points to the leading sign character position.

A ZSIVIP switch 730-116 selects a trailing or leading sign for 4-bit or 9bit operands. The ZSIVIP 1-315 shift count is applied to an SIGNM shifter 730-118. The logical ZERO input to the SIGNM shifter 730-118 selects the one of the SIGNM 0-7 output signals for 4-bit operands. The logical ZERO and the ZTNSAO signals select two adjacent signals of the SIGNM 0-7 output signals for 9-bit operands.

The signal SIGNM 0-7 output of the shifter selects the [1ZSMR 0-7 output signal of control PZSIVIR 730-142 which selects 1 of 8 of the switch 1 positions of the ZSIVIR switch 730-180 for the 4-bit 20 decimal digit operand sign or 2 adjacent positions for the 9-bit character operand sign.

The exponent is added to the operand in response to the DUCMD 308 "Load the DU Exponent Register' command. An REXP register 730-138 is loaded from the ZADSP 3-11 signal bus. A ZEXP switch 730-140 selects the exponent bit configuration for an operand having 4-bit decimal characters and storing the least significant 4-bit character in an even digit location in cache 750 25 through the ONE position of the ZEXP switch. All other exponents are selected through the 0 position of the switch. The signal ZEXP 0-8 output is applied to the 2 position of the ZSMR switch ZSMR 730-180. The exponent character positions are selected by the [2ZSMR 0-7 signal outputs from a control logic [2ZSMR 730-146. The signal is generated as follows. The boolean expressions for control signals [1ZSMR 0-7 and [2ZSMR 0-7 are shown supra.

The ASM 5-6 output signals of the ASM adder 730-68 indicate the location in the low order word of the operand of the low order character for 9-bit characters. Binary ONE is subtracted from this value in an ACIPE adder 730-74 to give the location of the high order digit of the exponent for an operand made up of 4-bit characters. A ZEMP switch 730-120 selects the character position and the output signals ZEMP 1-3 are applied to an EXPM shifter 730-122. The EXPM 0-7 output 35 signals are applied to the control logic [2ZSMR 730-146. The output signals MIVIR 0-7 select the two adjacent character positions in the ZSIVIR switch 730-180 to enable the exponent to be written into the low order word.

For a 4-bit operand it is possible for the most significant digit position for the exponent character to be in digit position 7 and the least significant position to be in digit position 0 of the next word. In 40 this case the EXPM mask 730-122 generates a ONE output on the EXPM7 signal line when the ZEMP switch 730-120 pointer is at decimal 7 during the next to the last word received. When the last word is received the ZEMP switch pointer remains at 7, the DBITS input signal is forced to a ONE resulting in the EXPMO line being forced to ONE thereby activating the 0 character position of the least significant word.

The boolean expression for the DBITS signal is:

DBITS=MO (DUCIVID 303+FOPSTR) (ACPE1 - ACPE2. ACM) D 1 EMP Signals RDESCO and RDESC 'I are applied to the write select inputs of RI- NDO-21 register 730 12, RTNSO-3 register 730-32 and RCPO-3 registers 730-42. Signals RDESCO and RDESC1 are binary coded 00, 01 and 10 to identify operands 1, 2 and 3 respectively.

Control signals [1ZLNDA and [2ZI-NDA are applied to the ZI-NDA switch 73016 and the ZTNSA switch 730-36. Status flag ffl-VN is appfied to the ZI-NDB switch 730-20 and the MSB switch 730-34.

Control signals [ 1 XPA and [=PA are applied to the XPA switch 730-44. The boolean expressions describing the signals are:

[Ul-NDA=F3DESC. FLDCOMPI [=NDA=F3DESC. FLDCOMPI [1ZCPAFRDP1 FM0WPI+F3DES -FLDCOMPI [=PA=F3DESC. FLDCOMPI The ZSIVIR 0-35 output including decimal digits, exponents and sign are applied to the MOD 60 switch 730-152 and are loaded into the RDOD register 730-154 for transfer to the cache 750.

In the short operand store the words are received from the execution unit 714 with the last significant word first and the most significant word last. A DUCMD 305 - Transfer Data from RCHO to RK- command is initiated by the firmware. The least significant word is received from the character unit 720 over the RCHU 4-35 signal bus and is stored in the RK register 730-162 through a buffer 65 1 GB 2 115 586 A 25 730-168 and position 0 of the ZM 730-160 switch. If the short operand comprises 2 words then the most significant word is placed in the RCHU register on the same cycle and appears over the RCHU 4-35 signal bus on the following cycle through the buffer 730-168 position 0 of the ZIPK 730160 switch and is applied to the input of a ZPKR switch 730-164 and a ZIPKI- switch 730-166 as signals ZIPK 0-3 1. If the short operand was only one word long, zeros are placed on the RCHU bus to serve as the most significant word.

The negated output of the buffer 730-168, signals RCHU 4-35 is applied to the input of an output zero and overflow detection logic 730-80 and the effective digit logic 730-81. During the cycle in which the DUCMD 305 is present the least significant word is tested for zero or overflow and the most significant word is tested for zero or overflow on the following cycle which is marked by the 10 FCZO flag being at logical ONE.

An RSCUM register 730-78 stores the operand 3 length plus scale factor output of the ZI-NAW switch 730-26. An RSCLM register 730-144 stores the operand 3 scale factor output of the ASIF adder 730-10. The outputs of the RSCUM and IRSCILM registers input the logic unit 730-80.

The zero and overflow detection logic 730-80 masks out the non operand 3 field and indicates 15 to the firmware if the operand 3 field is zero since the DZERO output signal of detection logic 730-80 is at logical ONE in that case and also masks out the operand 3 field and the scale factor field and indicates to the firmware if there was a non zero decimal digit in the character positions to the left of the most significant character of operand 3 in the most significant word that is the DOFL output signal of detection logic 730-80 is at logical ONE. The RSCILM and RESCUM register outputs are used to 20 mask out the non operand 3 character positions and, in addition the RSCUM register outputs are used to the operand 3 and scale factor character positions thereby enabling the overflow check.

The boolean expression for loading the RSCUM register 730-78 and the IRSCILM register 730 144 is:

[I-DIRSCIVI=(FLDCOMPIL (F-CRD+DUCIVID 3114+DUCIVID 205) (DUCIVID 305+FCZO) The boolean expression for decrementing bit position RSCUM 0-6 and RSCLM 0-6 is:

[CNTDWNRSCM=(DUCMD 305+FCZO) A DUCMD 303 "Store Operand through Decimal UniV command is initiated by the firmware.

Since this is a short operand operation, 2 words are sent from the execution unit 714 to the decimal 30 unit 730 over the RCHU 4-35 bus. The least significant word remains stored in the RPK register 730-162 and the most significant word remains on the RCHU 4-35 bus for the processing of the instruction.

The RRWC register 730-88 stores the internal location of the most significant data word to be transferred from the decimal unit 730 to cache 750. The register is decremented each time a word made up of 4-bit characters is sent to cache 750. The register is also decremented each time a word made up of 9-bit characters is sent to an odd address in cache 750. The boolean expression for the decrementing signal [CNTDWN-RRWC are described supra.

The RDSC register 730-58 stores the shift count which is applied to the MS shifter 730-156 through the MSC switch 730-72. - 40 Assuming the shift count is positive, i.e. the RDSCO bit is a zero and the RRWC register indicates a word count of greater than 1, then the zero outputs of the ZIPKIL switch 730-166 and ZIPKIR 730 164 are applied to the shifter 730-156. The MS 0-31 output signals are zero and are applied to the ZID switch 730-150. The ZID 0-35 output signals are applied to the ZSIVIR switch 730-180 where the rewrite characters and leading sign may be added to the most significant word. The ZSMR 45 0-35 output is applied to the MOD switch where for 9-bit character words, EBCDIC or AS 11 zone characters are added and the MOD 0-35 output signals loaded into the RDOD register 730-154 for transfer to cache 750. Control signal [$1RDODA at logical ONE loads the RDOD register 730-154. The boolean expression is:

[$RDODA=((FDATA-AV+DUCMD 203+DUCIVID 310 +DUCIVID 309+FRIPK, DUCMD 303+ FR-PK. FALT. FSWRT). DUCMD 311) When the count in the RRWC register 730-88 equals ONE then the most significant word stored in the RCHO register 720-10 and appearing on the RCHU 4-35 signal bus is applied through the buffer 730-168 through position 0 of the ZIPK switch 730-160, through position 0 of the ZIPKIR 55 switch 730-164, through the MS shifter 730-156 where it is shifted to the right the number of digit positions equal to the MSC 1-3 binary shift count. Zeros equal in number to the shift count are inserted to the left of the most significant digit position. The MS 0-31 output signals are switched through position 0 of the ZID switch 730-150. The output signals ZID 4-35 are applied to the ZSIVIR switch for 4-bit characters where the word is expanded from 32 to 36 bit positions. The ZSIVIR 60 0-35 output signals are switched through position 3 of the MOD switch 730- 152 to the RDOD register 730-154 from which the word is transferred to cache 750.

If the word comprises 9-bit characters, then the ZID 0-35 output signals are applied to position 2 of the MOD switch 730-152 if the word is written in an even address in cache 750 or applied to position 1 of the MOD switch 730-152 if the word is written in an odd address in cache 750 through 65 26 GB 2 115 586 A 26 the RDOD register 730-154. Assuming a word to an even address in cache 750. Then the Z11) 4-35 is switched through position 2 of the MOD switch 730-152 where the 4 characters indicated by ZID 4-19 are expanded to 36 bits by adding the E13CIDIC or ASCII zone characters. On the next cycle the Z11) 4-35 signals are switched through position 1 of the MOD switch where the Z11) 20-35 signals are expanded to 36 bits by adding the E13CIDIC or ASCII zone characters. The RRWC register 730-88 is decremented each time a 4-bit character word

is transferred to cache 750 or each time a 9-bit character word is transferred to an odd address in cache 750. The RRWC counter 730-88 is decremented to zero with the shift count MSC 1-3 a positive binary number. In this case the ZPK 4-31 output signals are applied through the ZPKIL switch 730-166 and the RPK 0-3 output signals are applied through the ZPKR switch 730- 164 and the second 10 word is processed as before.

The RRWC register 730-88 is decremented to binary -1 with the shift count MSC 1-3 a positive number. The RK register 730-162 storing the least significant word has its RK 0-31 output signals applied through the ZPKIL switch 730-166 to the MS shifter 730-156. Zeros were applied to the MS shifter 730-156 through the ZPKI1 switch. The MS 0-31 output signals are applied through the switches to load the RDOD register 730-154 for transfer to cache 750.

If required the RRWC register 730-88 is decremented to binary -2. Zeros are applied to the MS shifter 730-156 inputs. This cycle of operation enables the exponent of trailing sign and also replacement characters to be stored in the RDOD register 730-154 after being switched through the ZEWR switch 730-180 and the MOD switch 730-152.

Each of the above store operations is enabled by the DUCMD 303 signal set by a firmware command to load the word in the RDOD regi ster 730-154 on a first firmware cycle and to write the word in cache 750 on a second firmware cycle. The first and second firmware cycles are repeated until all of the words containing operand 3 information are transferred to cache 750.

The sequence of steps for loading cache 750 for a negative shift count, i. e., the RDSCO output 25 signal is equal to ONE, is the same as for the positive shift count with the exception the binary value in the RRWC register 730-88 at each step is one more than its corresponding value or the positive shift count.

As a part of the long operand store operation the firmware initiates a DUCMD 304---Check Zero/OverfloW' operation. Operand 3 information is sent from the execution unit 714 to the decimal 30 unit 730 under firmware control a word at a time starting with the least significant word. A DUCMD 304 command is issued for each significant word to be checked and the word is put into the RCHO register 720-10, Figure 2, at the same time. The last DUCMD 304 command is issued by the firmware for the most significant word of the long operand. The decimal unit 730 scans each word received on the cycle following the DUCIVID 304 command which is marked by the FCZO flag being set from the least significant word to most significant word, counting the number of digits to the right of, and including the most significant digit. This count is stored in the RWPC register 730-84, RLZC 'I register 730-96, and RUC2 730-98. The output of these registers is available to the firmware in response to a DUCMD 311 "Put Operand Word Count into RDOD- command.

Effective digit logic 730-8 1, Figure 7, examines the resultant operand word RCHU 4-35, 40 received from the character unit 730. The resultant operand word was generated in the execution unit 714 and is the result of the decimal numeric operation performed on operand 1 and operand 2.

The negated signals RCHU 4-35 are applied to the inputs of NAND gates 812 through 81 of NAND gate 81-2. Decimal digit 1 16. Decimal digit 0 signals WC5RU -4-7 are applied to the inpu t signals MFMF---fl are applied to the input of NAND gate 81-4. In a similar manner the decimal 45 digit 2-7 signals are applied to the inputs of NAND gates 81-6 through 81- 16, If the inputs to NAND gate 81-2 indicate that digit position 0 signals RCHU M7 indicates a digit which is not zero, then the DGZ-0 output signal of NAND gate 81-2, at logical ONE, is applied to the input of a NAND gate 81-42. The output signal EDC-0 at logical ONE indicates that the word contains eight significant digits. The output signal DGM, at logical ZERO, is applied to the inputs of 50 NAND gates 81-44, 81-46 and 81-48 thereby forcing the output signals EDC1 -3 to logical ZERO.

If the digit 0 signal RCHU 4-7 indicates a decimal zero, then the output of NAND gate 81-42 is disabled and the output of NAND gates 81-44, 81-46 and 81-48, which indicates the position of the most significant digit of the operand word, is enabled. Assume that the most significant digit is in position 5 of the 8 position operand word positions 0 through 7. Therefore the DGZ5 output of NAND gate 81-12 is at logical ZERO and the DGZ 0-4 outputs of NAND gates 81-2, 81-4, 81-6, 81-8 and 81-10 are at logical ONE.

Digit 5 signal, a logical ZERO, is applied to the input of NAND gates 8122 and 81-32. The output signals DZR56 and 52-RG77- at logical ONE are applied to the inputs of NAND gates 81-28, 60 and 81-40 respectively. The other inputs, signals DZR 34 and DGZ4 at logical ONE are applied to the other inputs of NAND gates 81-28 and 81-40 respectively. The output signal DM3/ atiogical ONE is applied to the input of a NAND gate 81-36. The other input, signal M1 2 at logical ONE forces the output signal MR1 -4 of NAND gate 8-34 to logical ZERO, thereby forcing the output of NAND gate 81-44, signal EDC-1 to logical ZERO. The output of NAND gate 81- 36, signal DZR1/6 is65 27 GB 2 115 586 A 27 at logical ZERO since the input signal DZR34 of NAND gate 81-28 is at logical ONE. This forces the output signal M17-6to logical ONE forcing the output of NAND gate 81-46, signal EDC-2 to logical ONE. - The output of NAND gate 81-40 signal 5-Z-R4-/7- at logical ZERO is applied to the input of NAND gate 81-24. The output signal DZR3/7 at logical ONE is applied to the inputs of a NAND gate 81- 5 30. The other input signal DGZ-2 at logical ONE forces the output signal - DZ-R-22777 to logical ZERO thereby forcing the output of a NAND gate 81-38, signal DZR1/7 to logical ONE. This forces the output of NAND gate 81-48, signal EDC-3 to logical ONE.

Signals EDC-1, at logical ZERO, EDC-2 and EDC-3 at logical ONE, indicate that there are 3 significant digits in the operand word.

The least significant word is received by the decimal unit 730 over the RCHU 4-35 signal bus into the buffer 730-168. The negated output signals RCHU 4-35 are applied to the effective digit logic 730-81. The effective digit logic 730-81 output signals EDC 0-3 are applied to the input of the ZEDC switch 730-82. The ZEDC 1-3 output signals represent a binary count of the significant digits in the word starting from the most significant digits and counting to and including the low order digits position 7. The ZEDC 0 output signal at a logical ONE, indicating that the most significant position of the word, position zero, contains a decimal digit which is not a zero, is loaded into the AEDC adder 730-96 after the first word is received and the RWPC register 730- 84 is incremented by ONE each time a subsequent word is received from the execution unit 714 by control signals [ENRWPC, [CNTUP-RWPC and [LDRWPC being applied to the input terminals of the RWPC register 730-84. 20 Boolean expressions for control signals LDRWPC which loads the RWPC register 730-84 and ENRWPC which enables the outRut of the register are as follows:

[ENRMC((DUCIVID 305+FCZO)+FCRD - DUCIVID 314 - DUCIVID 205) [LDRWPC=((DUCMD 305+FCZO) (F-CRD+DUCMD 314 +DUCIVID 205)) The RWPC 0-3 output signals are applied to one terminal of an AEDC adder 730-86. The 25 ZEDCO signal is applied to another terminal of the AEDC adder 0-3 whose output is switched through the ZEDD switch 730-94 and stored in positions 0-3 of RLZC1 register 730- 96 and RLZC2 register 730-98 whenever the received word has a non zero decimal digit stored. The ZEDC 1-3 binary output signals of the ZEDC switch 730-82 which indicates the number of significant digits in the word are stored in positions 4-6 of the RLZC1 register 730-96 and the RLZC2 register 730- 30 98. The register outputs signals RLZC1 0-6 and RLZC2 0-6 are applied to the ZLZC switch 730-7, whose output is available to the firmware through position 3 of the ZID switch 730-150.

The RLZC1 and RLZC2 registers both store the number of significant digits in operand 3. When the first word is received from the execution unit 714, assuming position 0 contains a decimal digit, not zero, the binary quantity 8 is stored in the RLZC1 and RLZC2 registers. The ZEDCO signal input to the ZEDC 35 adder 730-84 is a logical ONE. When the second word is received again assuming position 0 contains a decimal digit, then the ZECDO signal input to the ZEDC adder is at a ONE and the RWPC3 signal input is at a one. This forces the ZEDC 0-3 output to a binary 2 and the quantity binary 16 is stored in the RLZC1 and RLZC2 registers, Assuming the third word contains only 3 decimal digits with the most significant digit in position 5 then the ZEDC 0-3 will store a binary 011 in the RLZC1 and 40 RLZC2 registers 730-96 and 730-98 respectively which will now have the quantity 19 stored in the registers.

The RLZC 1 -2 and RLZC2-2 bits (binary 16 bit) are again set since the AEDC 0-3 output is at binary 2. The RWPC 730-84 register was incremented from binary ONE to binary TWO. The RRWC register 730-88 stores the adjusted length of the operand which is calculated from length and scale 45 factor values, as designated by the descriptor. The RWPC register 730-84 stores the number of words examined by the firmware as the result of the DUCIVID 304 on a long operand.

In the long operand store operation it is necessary to compare operand 3 which is the result of the operand 1 and operand 2 calculations, as it exists internally in the execution unit 714 with the operand 3 as it is to be stored in cache 750, and to do so with a simplified firmware procedure. 50 Initially, the firmware issues the DUCIVID 303 "Store Operand Thru DUcommand. This command initiates the actual store sequence in the decimal unit 730. Unlike the short operand store procedure, the firmware will not prepare a write address and send a write command to cache 750 until it is permitted to do so by the decimal unit 730. The decimal unit 730 makes this decision based on the information stored in the RRWC register 730-88, the RWPC register 730-84 and the position of the 55 most significant digit within the word when the operand is received by the decimal unit 730 from the execution unit 714 as indicated by the output of the ACPNB adder 730-50. As in the short operand case the output of the ACPR adder 730-62 is subtracted from the output of the ACPNB adder 730 in the ACPSC adder 730-54 to generate the shift count which is stored in the RDSC register 730-58.

It should be noted that every word stored in cache 750 requires 2 firmware cycles minimum for the store operation. The address in cache 750 in which the operand word is written is sent to cache 750 on the first cycle and the data to cache 750 is sent on the second cycle. The firmware therefore is organized in 2 step loops, the first step generates the address and the write command and the next step passes the data through from the decimal unit 730 to cache 750. The process starts on the cycle 65.

28 GB 2 115 586 A 28 the firmware sends the DUCMD 303 command to the decimal unit 730. The firmware examines the start write signal RRI-TRD to the execution address and branch circuits 701 -1, Figure 4, for logical ONE which indicates that a write command should be generated and issued to the cache 750.

The FSW13T flag is set to indicate to the decimal unit 730 that the firmware is sending write commands to cache 750. If the start write line 13RLTRD is at logical ZERO then the firmware controls the loading of the RCHO register 720-10 of the character unit 720 with words from the execution unit 714 until the most significant word is stored. This is the case where the count in the RWPC register 730-84 would be greater than the count in the RRWC register 730-88. The RWPC register 730-84 is decremented each time a word is placed in the RCHO register 720-10 until the count in the RWPC register equals the count in the FIRWC register if the RDSC register 730-58 indicates a positive shift or until the count in the F[WPC register is less than the count in the RRWC register if the RDSC register indicates a negative shift. For a positive shift the most significant word is stored in the RCHO register 720-10. For a negative shift the most significant word is stored in the FIPK register 730-162 and the second word is stored in the RCHO register 720-10.

For the positive shift operation, the start write line RRLTRD is forced to logical ONE and the firmware initiates a write into cache 750 loop when the RIRWC register 730-88 count equals the RWPC register 730-86 count. This sets the FSND flag which strobes the previous word stored in the RCHO register 720-10 into the RP K register 730-162 and indicates to the firmware to load the next word into the RCHO register 720-10 from the execution unit 714 by forcing the send data signal RREQRD to logical ONE.

The boolean expressions for the start write signal RRLTRI) and the send data signal RREQRD for long operand store operations are as follows- DSEND DATA(FCPCO - ZTNSAO+ZTNSAO) - DMSEQ - FSWRT - FMSDRN DSTRTWRT=FM-SEQ DMSDRGTE - RDSCO+DMSDRGTE - RDSCO+DUCMD 303 - RRWCO RREQRD=FDUACT - DSEND DATA - DUCIVID 202 - DUCIVID 204. DUCIVID 306 RRLTRD=FDUACT - DSTRT-WRT DUCIVID 202. DUCIVID 204 DMSDRGTE=(RWPC 0-3 - MINUS - 1) > (RRWCO - (RRWC1 +RRWC2) - RRWC3 - RRWC4- RRWC5- RRWC6 DMSEQ=(RWPC 0-3 - MINUS - 1) = (RRWCO - (RRWC 1 +RRWC2) - RRWC3 - RRWC4- RRWC5 - RRWC6 DMSDRGT=(RWPC 0-3 - MINUS - 1) > (RRWCO - (RRWC1 +RRWC2) - RRWC3 - RRWC4- RRWC5 - RRWC6) The boolean expressions for the count down of the RWPC register 730-84 are as follows:

[CNTDWN-RQPC=FRPK - DUCIVID 303. (ZTNSAO - FCPCO +ZTNSAO)+FRPK - (FOPSTR+ DUCIVID 303 - DMSDRGTE) - FA-L-T - (FSWRT DMSDRGT+(ZTNSAO - FCPCO+ZTNSAO) FSWRT - DMSDRGT) [$RDOD=FDATA-AV+DUCMD 203+DUCMD 310+ DUCIVID 311 +DUCMD 309+FRPK - DUCIVID 303+FRPK - FALT - FSWRT The decimal unit 730 compares the RKVVC 0-6 output signals with the RWPC 0-3 output signals in a comparator 730-90. The comparator output signals DMSEQ, DMSDRGT and DMSDRGTE condition the register and switch control 730-91 for generating the RRLTRD and RREQRD signals and 50 the various signals controlling the ZPK switch 730-160, the RPK register 730-162, the ZPKL switch 730-166 and the ZPKR switch 730-164. The signals also condition the status flag control logic 730-202 for setting the FSND, FSWRT, FMSDRGTE and FMSEQ flags as well as decrementing the RRWC register 730-88 and the RWPC register 730-84. When the number of words stored in the RRWC register 730-88 is greater than the number of words stored in the RWPC register 730-84 then the cache write flag FSWRT is set but the FSND flag is not set. This results in the RDOD register 73-154 outputting words containing all zeros to cache 750 and decrementing the RRWC register 730. When the comparator 730-90 indicates an equal condition, the FSND flag is set and under firmware control the most significant word is sent from the execution unit 714 to the decimal unit 730 60 over the RCHU 4-35 signal bus thereby inputting the buffer 730-168. The buffer 730- 168 output 60 is applied to the 0 position of the ZPK switch 730-160. The most significant word is stored in the RPK register 730-162 from the ZPK switch 730-164. Control logic, not shown, enables the ZPKR switch if a data word can be assembled and sent to cache 750. In that case, the ZPKR 0-31 output signals are applied to the ZDS shifter 730-156 and the word shifted by a number of digit positions 65 equal to the binary value of the ZDSC 1-3 signals. Zeros are applied on the ZPKL 4-31 signal bus. 65 1 i 29 GB 2 115 586 A 29 The MS 0-31 output signal is switched through position 0 of the ZID switch 730-150 to position 0 of the ZSMR switch 730-180 if the operand comprises 4-bit characters. If the operand comprises 9bit characters then the ZDS. 0-31 output signal is switched through position 0 of the ZID switch 730-150 to position 1 of the MOD switch 730-152 if the word is to be written in an odd address in 5 cache 750 orto position 2 of the MOD switch if the word isto be written in an even address in cache 750.

Position 0 of the ZSIVIR switch expands the word containing 4-bit digits from 32 bits to 36 bits after which the word is switched through position 3 of the WOO switch 730-152 to the RDOD register 730-154 where it is stored and sent to cache 7 50 on the next cycle.

Position 2 of the MOD switch 730-152 expands words of operands to be made up of 9-bit 10 digits by expanding the Z11) 4-19 output signals to generate the 36-bit word by adding the ACS11 or E13WIC zone characters. Position 1 of the MOD switch 730-152 expands the Z11) 20-35 output signals to the 36-bit MOD 0-35 signal bus. The MOD 0-35 output signals from position 2 of the MOD switch are stored in the RDOD register 730-154 and transferred to an even cache 750 address. The position 1 outputs of the MOD switch are transferred to odd cache 750 addresses. 15 In the event that the comparator 730-90 output indicates that the RRWC 0- 6 binary count of the RRM register 730-88 is less than the RMC 0-3 binary count of the RMC register 730-84 then data words are neither received from the execution unit 714 nor sent to cache 750 by the decimal unit, and the RWPC register 730-88 counts down until the output of the comparator 730-90 indicates that the RWPC 0-3 binary count equals the RRWC 0-6 binary count. This sets the FIVISEG 20 and FSWRT flags and the data words are clocked into the RDOD register 730- 154 and transferred to cache 750.

Operands having 9-bit characters transfer 2 words to cache 750 for every word received from the execution unit 714 during normal operation. The word received from the execution unit 714 has up to eight decimal digits of 4-bits each and is expanded to 2 words, each containing up to 4 decimal digits 25 of 9-bits each. The FCP120 flag cycling on and off controls the transferring of words to odd addresses and to even addresses in cache 750.

Cycle delay The processing of short operands is speeded up by predicting, as the processing of the instruction is starting, the number of words sent from the decimal unit 730 to the execution unit 714 and the number of cycles between the time the first read command is sent to the cache 750 and the first data word is sent to the execution unit 714. The number of words and cycles of delay are calculated in the decimal unit 730 and sensed by the firmware in the execution control unit 701. The decimal unit 730 output signals, PK-VCTR 0-3, Figure 4, are applied to the execution address and branch circuits 701-1 and cause the firmware to branch to a particular address in the execution control store 701- 35 4 which results in the firmware executing a subroutine to process the operand. The particular subroutine selected is designed to process the exact number of words of the operand with the exact number of cycles of delay thereby processing the operand with minimum of number of microwords.

The calculation for the number of delay cycles is a function of the type of data, that is, whether the incoming operand is made up of 4-bit or 9-bit characters, the location of the most significant character in the operand coming from cache 750 and the location of the most significant digit in the operand being transferred to the execution unit 714. As an example, assume an 8-decimal digit operand made up of 9-bit characters with a leading sign. Also assume the sign was in the third character position of the first word of the operand. The second word from cache 760 contains 4 decimal characters and the third word from cache 750 contains 4-decimal characters. The decimal unit 45 730 would not load any decimal digits upon receiving the first word since the first word only contained the sign. Four decimal digits were received from the second word, still not enough to fill the ROOD 730-154 register. Four decimal digits were received from the third word and the ROOD register was loaded with 8-decimal digits.

This load operation took 3 cycles to assemble and 0-3 transfer the word to the execution unit 50 714. The PK-VCTR 0-3 signals lines would indicate a one word transfer with a 2 cycle delay to the firmware. The firmware by using the information indicating the number of words transferred and the number of cycles of delay performs the control of transferring data words from one register to another on a specific cycle rather than to halt or loop waiting for the data word.

The delays are a function of the data type, 4-bit or 9-bit decimal characters as indicated by the 55 condition of the output of the ZTNSA switch 730-36 and the ZTNS13 switch 730-34, ZTNSAO or ZTNSBO signals. The ACPNB adder 730-50 gives as an output the digit position of the most significant digit of the word received from cache 750. The ACPDF adder 730-52 gives the difference in positioning between the first character position for the high order digit in the first word from cache 750 and the digit position of the most significant digit as it is transferred to the execution unit 714. The 60 output of the ZCPA switch 730-44 signal SCPAO identifies the word from cache 750 as being from an odd or even word address.

The Boolean equations for the number of words and cycle delay calculations are readily interpreted into functional hardware by one of ordinary skill in the art and are as follows:

GB 2 115 586 A 30 P K-VCTR 0=0 PK-VCTR l=TD130 P K-VCTR 2=MB 1 M-VCTR 3=ARM6 TD130=[(ZTNSA0. FDUACT. -RDP 1 +Z-TN-S-W. FRDP 1) 5 (ACI'DFO Z-C-PA50+ACPD170 - =PA0 R5-PDFM TD131=[(ZTNSA0. FDUACT- FRDPi+ZTNSBO. FRDIP1) (ACPDFO) +(ZTNSA0. FDUACT. F-R-DP 'I +ZT-N-U"B-0. FRDP1) [ (A C P D F Z. Z-C-P-AO) + (A-C P-D i O. -ZC-P A50 (A-C]5]q-BO. ACPN - Bl.ACPN 2.ACPNB3+ 10 ACP1)1=1. ACMB0 - AZ-P-NBl)+ACPDFO. ZCPAQ). ACP1)F1)11 The PK-VCTR 1 signal forced to binary ONE indicates a 2 cycle delay. The PK-VCTR 2 signal forced to binary ONE indicates a 1 cycle delay. The PK-VCTR 3 signal forced to binary ZERO indicates that 1 data word will be transferred to the execution unit 714 from the decimal unit. The PK-VCTR 3 signal forced to binary ONE indicates that 2 data words will be transferred to the execution unit 714. 15 For the PK-VCTR 1 calculation the 2TNSA0 - FDUACT - FRDP 1 Boolean expression indicates a 9 bit operand 1 word from cache 750. The 2TNS90 - FRDP 1 indicates a 9-bit operand 2 word from cache 750. The ACPDFO - ACPAO expression indicates a left shift through the shifter 730-156 of the word from an even cache 750 address. The ACPDFRO - ZCPA0 - ZCPDF1 expression indicates a left shift of from 1-3 decimal digits of a word from an odd cache 750 address.

For the PK-VCTR 2 calculation ZTNSAO - FDUACT - FRDP 1 - ACPDFO indicates a 4-bit operand 1 word from cache 750 requiring a left shift through the shifter 730-156. ZTNSBO - FRDP 1 - ACPDFO indicates a 4-bit operand 2 word requiring a left shift. TT--NSAO - FDUACT - FRDP 1 +2TNSW - FRDP 1 indicates a 9-bit operand 1 word and a 9-bit operand 2 word.

ACPDFZ - MPT0+Z-c-PM - ZMP-A0 indicates either a zero shift or a right shift of the word from 25 the even cache address. ACPNBO - ACPNB1 - ACPNB2 - ACPNB3 indicates that the high order decimal digit is in position 4 of the 4-bit character word or position zero of the 9-bit character word from odd cache address. AC-PDF 1 - AC---PNBO - ACPNB1 indicates that the high order decimal digit received from cache 750 is in locations 1-3 and the shift count is less than 4 digits. ACPDFO - ZCPA0 - ACPDF1 indicates a left shift of greater than 3 digit positions from the odd cache address word. Note 30 that the ACPDFZ signals at binary ONE indicates that the adder 730-52 is set a binary ZERO. For the PK-VCTR 3 calculation, ARWC6 indicates a one word transfer from the decimal unit 730 and the execution unit 714 when at binary ZERO and a two word transfer when at binary ONE.

Decimal unit 730-Figure 3-rewrite operation Operand 3 may start and end in character positions within the most significant word and the least 35 significant word. It may be necessary to retain the information stored in the most and least significant words of operand 3 that are not part of operand 3. In this case, the firmware initiates a DUCIVID 306 "Load Rewrite Data" command in the decimal unit 730 to load the most significant word into the REWR2 register of register bank 730-177 through the ZDI 0-35 bus from cache 750, the RDI5 register 730-158 and the RDID buffer 730-176. The firmware initiates a second DUCIVID 306 to 40 load the least significant word in the REWR3 register of the REWR 0-3 register bank 730-177.

When the firmware initiates a DUCIVID 303 "Store Operand Through Decimal Unit" command the most significant word appears on the ZID 0-35 signal bus. Assuming 4-bit decimal characters for the operand the RCP2 register of register bank 730-42 stores the starting character position of the operand 3. Since this is a descriptor 3 operation the RCP2 position of switch 730-44 is selected and the ZCPA 0-3 output signal is applied to a ZRUMP switch 730-148. Position 1 of the ZRUMP switch is activated and the ZRUMP 0-2 output signal is applied to a REWUM shifter 730-149. The REWUM 0-7 output signals are applied to control [1 ZSMR logic 730-142 and control [2ZSMR 0 7 output signals select the digit positions of the ZSIVIR switch that will be selected. For example, for processing the most significant word of the 4-bit digit operand, digit positions in position 0 of the ZSIVIR 5o switch 730-180 would be selected for the operand digit data. The sign position in position 1 of the ZSMR switch 730-180 would be selected if the operand had a leading sign and the digit positions to the left of the operand would be selected in position 3 of the ZSIVIR switch for the rewrite data. The REWUM 0-7 signal output of the shifter 730-149 is a zero for those digit positions requiring write data. The ZSMR 0-35 output bus is switched through position 0 of the MOD switch 730-154to the RDOD register 730-154.

If the operand contains 9-bit decimal digits then the [ 1 ZSMR 0, 2, 4 and 6 logic signals and [2ZSMR 0, 2, 4 and 6 logic signals are applied to the unpack MOD logic 730-184. The [1ZDOD 0-3 and [2ZDOD 0-3 output signals enable the rewrite and leading sign digit positions of switch position 3 and the operand decimal digit positions of either position 1 or position 2 of the MOD switch 60 730-152.

During the load operation for a 2 descriptor operation the most significant word of operand 2 which could contain rewrite information is written into the REWRO register of the register bank 730- 1 z 31 GB 2 115 586 A 31 177 and all subsequent words are written into the REWR1 register replacing the previous word. This results in the most significant word of operand 2 stored in the REWRO register and the least significant word of operand 2 stored in the REWR 'I register. The loading of these registers into the RDOD register 730-154 is as described supra.

The REWR register bank 730-177 is enabled by the control signal [$REWR. The boolean 5 expression is [$REWR=(FDID+FLDREWRH).

Control signal [WRRIEWR 1 is applied to terminal 1 and status flag FIDREWRI-1 is applied to terminal 2 of the register select input terminals to select one of four registers REWR 0-3. The boolean expression control signal WRREWR1 is:

[WRREWR1=FOP2LD. FOP2F+FI-DREWRI-11. FREWR The output of registers REWR 0-3 is selected through the ZEWR switch 730- 178. Signal [1ZEWR is applied to output select terminal land status flag FREWR is applied to the output select terminal 2 of ZEWR switch 730-178. The boolean expression for control signal [1 ZEWR is:

[11ZEWR=(FREWR. FREWR2. FFOS13+FOP2S. FFOSI). FREWR).

Decimal unit 730-Figure 3-rounding constant Two DUCMD 309---Putthe Rounding Constant into RDOW commands are initiated by the firmware. For short operands the roundOg constant is sent to the execution unit 714 in response to the first DUCIVID 309 if the constant is to be inserted in the least significant word. The rounding constant is sent to the execution unit in response to the second DUCIVID 309 if the constant is to be inserted in the most significant word. For either case, a word of allzeros is sent to the execution unit for the other DUCIVID 309 command. The other rounding constant, binary 5, is added to the position to the right of the scale factor pointer (decimal point). The rounding constant is stored in bit positions 4-7 of switch position 3 of the ZM switch 730-160.

The ATIVIP adder 730-30 subtracts a ONE from the operand 3 scale factor stored in the RS172 register of register bank 730-4 and is applied to the ATIVIP adder 730-20 through the 25 ZASH switch 730-28. If the ATIVIP6 output signal is a ZERO then the rounding constant is applied to the least significant word in response to the DUCMD 309 command. If the ATMP6 output signal is a ONE then the rounding constant is applied to the most significant word in response to the second DUCMD 309 command.

The ATIVIP 7-9 output signals are inverted by inverter 730-147. The ATIVIP 7-9 output 30 signals are selected by the MSC switch 732 and provide the binary shift count to the shifter 730 156.

The ZPKR switch 730-164 is enabled in response to the first DUCMD 309 command if the rounding character is added to the least significant word and enabled in response to the second DUCMD 309 command if the rounding character is added to the most significant word. In either case 35 the binary 5 output from position 3 of the ZPK 730-160 switch is transferred to the execution unit 714 through the ZKR switch 730-164, the MS shifter 730-156, position 0 of the Z11) switch 730-150, position 0 of MOD switch 730-152 and the RDOD register 730-154.

In the long operand store operation the decimal unit 730 responds to the first DUCMD 309 command with a pointer to the word in scratchpad to which the rounding constant is added and responds to the second DUCMD 309 command with the rounding constant. The ATIVIP 0-6 output signals which indicate the word to which the rounding constant is added are selected through position 3 of the ZI-M switch 730-76, position 3 of the ZID switch 730-156, position 0 of the MOD switch 730, the RDOD register 730-154 to the execution unit 714. The rounding constant, binary 5, is transferred to the execution unit 714 during the second DUCIVID 309 operation as in the short 45 operand above.

Sign extraction As each operand is received by the decimal unit 730 during the load operation the sign character is examined if it is not an overpunched sign character. The decimal unit 730 verifies that it is a legal sign character.

An RCPS 0-2 register 730-126 stores the character location within the word of the sign character. A ZCPS switch 730-124 selects the position of the sign character. The ZCPS switch position 0 identifies the leading sign position for 9 bit character operands. Switch position 1 identifies the leading sign position for 4-bit character operands. Switch position 2 identifies the trailing sign position for 9-bit character operands. Switch position 3 identifies the trailing sign position for 4-bit 55 operands.

The RCPS 0-1 output signals select the position of a ZCH switch 730-170 that could contain the sign character. No attempt is made to select the trailing or leading vord of the operand in the ZCH switch 730-170. An operand word received from cache 750 over the W1 0-35 signal bus is stored in the RDID register 730-158 and is applied to the ZCH switch 730-170. The ZCH 1-8 output 60 signal is applied to a WHIL switch 730-172 and to sign extraction logic 730-174. Position 1 of the ZCHL switch is selected for 9-bit operands and 4-bit operands having an odd character pointer.

The sign extraction logic 730-174 selects either the sign character from the trailing word or 32 GB 2 115 586 A from the leading word. If the sign character is coded as an illegal character then a SET ILLEGAL logic signal forces a fault indication for the software. If the sign character is coded as a correct sign then the SET SIGN logic signal sets an indication for the software. The ZCH 1 -8 output signals to the sign extraction logic indicate 8-bit E13CD1C sign characters. The ZCH 1-8 output signals to the ZCHL switch indicate 4-bit sign characters in the lower half of the 9-bit character (bit position 4-8) position 5 for 9-bit character operands. For 4-bit operand words, even pointers indicate the left 4-bits (bit positions 1-4) and odd pointers indicate the right 4bits (bit positions 5- 8).

Control signals [ 1 ZCPS and [2ZCPS are applied to the terminals 1 and 2 select inputs of ZCPS switch 730-124. The boolean expressions are:

[1 ZCPS=(ZTNSA0. FDUACT. FRDP 1 +ZTNS130. FRDP 1) [=1PS=(ZTNSA1. ZTNSA2. FIDUACT. FRDP 1 + ZTNS13 1. ZTNS132. FRDP 1) The RCPS register is enabled by a [SRCPS control signal whose boolean expression is:

[$RCPS'--(FDUACT. P-R-DPl)+SIFOP2LD) Overpunch digit correction-Figure 3 Operands made up of words having 9-bit characters may have separate signs in either a leading or trailing character position or the operand may have a sign included in the decimal digit code in a single character position. This requires that a correction be made to the decimal digit to include the overpunched sign. Assume that operand 1 requires an overpunched sign correction. An ROP 1 logic signal is sent from the control store 704-2 to the decode logic 730-38. If the ZTNSA 0-2 output 20 signal from the RTNS2 register of register bank 730-32 and the ZTNSA switch 730-36 is coded to a binary 000 or 011 indicating 9-bit characters with leading sign or trailing sign, a D l E0OVIP logic signal output of decode logic 730-38 is forced high. The D 1 EQOVP logic signal selects the 1 position of a ZSSC switch 730-108 for a trailing sign operand. The 0 position of the ZSSC switch is selected for the leading sign. The FILIVIP 4-6 signals are coded to point to the character position of the leading 25 sign and the RTIVIP 4-6 signals are coded to point to the character position of the trlign.

The ZSSC 0-2 shift count signals are applied to a shifter 730-145 to shift a DBITT logic signal the number of bits specified by the ZSSC 0-2 count. The 5-BI1T logic signal is forced to a ZERO for the overpunched sign operations during the cycle in which the most significant word or the least significant word is read from cache 750 for the leading sign or trailing sign correction respectively. The shifter 30 730-145 output signals ZCREGM 0-7 are applied to the Z11) switch control logic 730-188 to select po ition 2 of the ZM switch for the character position that is indicated by the one signal of the ZCIRDGM 0-7 signals that is at a ZERO which points to the overpunched sign position.

The FISGN register 730-1134!s loaded with the corrected overpunched sign character for operand 1 under firmware control. The REXP register 730-138 is loaded with the corrected overpunched sign character for operand 1 under firmware control. A ZURDE-G switch 730-136 selects the FISGN 5-8 output signals for the operand 1 overpunched sign correction character. The ZCRDG 0-3 signals are inverted by an inverter 730-186 and are applied to position 2 of the ZID switch 730-150. When the word to which the corrected overpunched sign is added is received from cache 750, it is switched through the decimal unit 730 to be stored in the RDOD register 730-154. The character in the sign position is replaced by the ZCR13G 0-3 corrected overpunched sign character.

The boolean expression for the DBITT lis:

DBITT=WOP1 LD. D1 ECIOVIP. (ZTNSA1 FF-55+ZTNSA(1) DIVIPEW+FOP2LID D2EQ0VIP (_ZT-NS-BR1. P-FD5-01 +ZTNSAM. DIVIPEM 45 where DIVIPEO. is at logical one when the contents of the RLIVIP register 730-102 equals the contents of the RTMP register 730-100.

The above equation indicates that the DBITT signal is set to logical ZERO when operand 1 or operand 2 requires an overpunched sign correction during the load operation. ZTNSA1. FFDO indicates a leading overpunched sign and ZTNSA1. DIVIPEG indicates a trailing overpunched sign. D1 EQ0VIP=DI31TX. ROP 1 ZTNSA6) D2EQ0VIP=55-ITZ. ROP 1 ZTNSBO) During the store operation the sign character is placed in the RSGN register 730-134 and inserted in the operand word through position 1 of the ZSMR switch 730-180 as previously described.

Decimal unit 730-Figure 3-Load STC Mask into RDOD The firmware initiates a DUCMD 203 Load STC Mask into RDOD command during the Store Character in Accumulator and Quotient Register Instructions (STCA and STCQ). The decimal unit 730 receives the RCHU 30-35 output signals from the character unit 720 which are applied to position 1 of the ZID switch 730-150 through the buffer 730-168. Each of the RCHU 30- 35 output signals 60 at a ONE results in the corresponding 6 bits of position 1 of the ZID switch 730-150 being forced to a ONE. These groups of 6 bits are stored in the RDOD register 730-154 through the ZDOD switch 730-152.

i 33 GB 2 115 586 A 33 Figure 4 shows the relationship between the decimal unit 730 hardware and the firmware in the execution control store 701-2. The execution address and branch circuits 701 -1 send the control store address locations ZECSA 0-12 to the execution control store 701-2. The microword at that address location is read out and bit positions RSCR 88, 89, 94-97 input a decimal unit 730 decode logic 730-204 which consists of conventional decode logic circuitry. Table 1 shows the RSCR 88, 89, 94-97 bit configurations for the respective DUCMD 200-206, 300-315 commands.

The DUCMD 200-206 300-315 commands input a status flag control logic 730202. This unit is made up of conventional flops set and reset in a conventional manne-r.

The I cycle control state circuits 704-102 described in the aforementioned British Patent 2,008,817 generates the FPOA [POP HOLDN and the [HOLDE signals to time the decimal unit 730 to 10 the pipeline operations of the control unit 704. These signals also input the decimal unit control logic 730-200 and the status flag control logic 730-202 whose output inputs a decimal unit control logic 730-200 as well as inputting the status flag control logic 730-202. Also applied to the decimal unit control logic 730-200 are the DUCIVID outputs of the decimal unit decode logic 730-204 and the descriptor information received from control unit 704-1 over signal lines RSIR 21-35 and ASFA 15 33-36 in the registers shown in Figure 3.

Operands stored in cache 750 are transferred to the operand processing unit 730-206 a word at a time over signal lines ZDI 0-35. The operand processing unit 730-206 is conditioned by the descriptor information, the status flag signals and the register and switch control signals, receiving the operand word from cache 750 to strip non-operand an non-decimal digit characters from the word, 20 converting the word into 4-bit decimal digits, aligning the four 4-bit decimal digits into words of up to eight 4-bit decimal digits and transferring the completed word to the execution unit 714 over signal lines RDOD 0-35. Outputting the logic 730-200 unit are the PK-VCTR 0-3 signals and the RRLTRD, RREQRD, ADSZ and ZAMO conditional branch signals which generate branch addresses in the execution address and branch circuits 701 -1.

A clock signal times the relationships between the logic units of Figure 4.

Figure 4 shows the flow of logic through the system. Where the portions of the logic blocks of Figure 4 relate to the inventions, they are shown in further detail in Figure 3.

Figure 5 shows two typical instructions processed through the decimal unit 730. The AD21) instruction-add using two decimal operands, adds the operand from the address location and in the 30 format defined by descriptor 1 to the operand from the address location and in the format defined by descriptor 2 and places the resulting operand in the format and address location defined by descriptor 2.

The AD31) instructions-add using 3 decimal operands adds the operand from the address location and in the format defined by descriptor 1 to the operand from the address location and in the format defined by descriptor 2 and places the resulting operand in the format and address locations 35 defined by descriptor 3. The instruction word is made up of 36 bit positions 00-35.

The instruction format includes a P bit defining EBCDIC data when a ZERO, and ASC1 1 data when a ONE.

Fields MF1, IVIF2 and IVIF3 describe the address modifications to be performed on descriptor 1, 2 and 3 respectively.

The T bit enables the truncation fault.

The RD bit enables the rounding operation.

The OP CODE specifies the operation to be performed. In Figure 5 the OP CODE 202-1 specifies the AD21) instruction and OP CODE 222-1 specifies the AD31) instruction.

1 is the interrupt inhibit bit.

For the descriptor formats, Y1, Y2 and Y3 are the main memory word locations of the most significant character of the operand specified by descriptors 1, 2 and 3 respectively.

The O/E bit identifies the main memory word address as being either an odd address or an even address.

CN 1, CN2 and CN3 are codes that define the position of the most significant character within the 50 main memory word of the operand specified by descriptors 1, 2 and 3 respectively. Codes depend on the data type as shown below:

Codes Character Numbers 9 bit characters 000 0 55 010 1 2 3 4 bit characters 000 0 OG1 1 010 2 60 011 3 4 101 5 6 111 7 65 1 34 GB 2 115 586 A 34 TN1,TN2 and TN3 are codes that define the numeric data type for descriptors 1,2 and 3 respectively. A ZERO specifies 9-bit data and a ONE specifies 4-bit data.

The S1, S2 and S3 fields identify the sign and decimal type of descriptor 1, 2 and 3 respectively.

Unpacked data Packed data M= 1 M=0 OW allowed or 0 VP not allowed 5 i S 00 LS, OW, scaled 00 Floating point, LS 01 LS, scaled 01 LS scaled TS, scaled 10 TS scaled 11 TS, OVIP, scaled -11 Nosigns,scaled 10 LS=Leading TS=Trailing Sign OW=Overpunched sign SF1, SF2 and S173 specify the scale factors of descriptors 1, 2 and 3 respectively. The decimal point is located after the least significant digit. A positive scale factor moves the decimal point that 15 many positions to the right. A negative scale factor moves the decimal point that many positions to the left.

N 1, N2 and N3 are the number of characters in the operand defined by descriptors 1, 2 and 3 respectively. N 1, N2 and N3 may be 4-bit codes which specify registers that contain the length of the respective operand. However, for describing the invention N1, N2 and N3 are the number of characters 20 in the operand.

Decimal unit 730-Figure 3-vector branch data Referring to Figure 3, the decimal unit control logic 730-20 generates control signals [1 MCTR, [2MVCTR and [41PI(VCTR in response to decimal unit 730 DLICMD command signals as described supra. The vector branch logic 730-15 has applied to it signals indicative of the characteristics of the operand. The output signals of decode logic 730-38 and 730-40 which are described infra define the operand as a floating point or overpunched sign and as a scaled operand if made up of 4-bit or 9-bit decimal characters. The ZTNSA1 and ZTNSB 1 signals indicate an operand with a trailing sign if at logical ONE and an operand with a leading sign if a logical ZERO. The ALNS 3 5 and the ALNDA 0-3 and the ALNDB 0-3 signals identify the operand as having an adjusted length of greater than 63 decimal digits or a length of less than or equal to 63 decimal digits. The detailed logic is shown in Figure 8.

The vector branch logic 730-15 output signals M-VCTR 0-3 are applied to the execution address and branch circuits 701-1 in response to the [1 MCTR, [2MCTR and [4MCTR control signals to indicate to the execution control store 701-2, Figure 1, the next microword to be processed 35 by the system.

Referring to Figure 8, a M-VCTR switch 15-72 a-d generates vector branch signals M-VCTR 0-3 in response to microword signals which are applied to the decimal unit 730. The microword signals generate DUCIVID command signals, which when combined with status flag signals generate control signals [1 MVCTR, [2KVCTIZI and [4MCTR. These control signals are applied to the 1, 2 and 40 4 input select terminals of switch 15-72 and select 1 of 8 input signals from each of 4 sections of the switch 15-72 a--d.

During the processing of non-decimal numeric instructions the decimal unit 730 is inoperative thereby activating input terminal 0 of switch 15-72 a--d. J The type length vector signals are applied to input terminal 1 of switch 15-72 a-d. The 45 DSHORT signal is applied to input terminal 1 of switch 15-72 a. If the ALNS adder 730-24 indicates the adjusted length of the operand as greater than or equal to binary 16 then one or more of the input signals ALNS 3-5 to AND/NAND gates 15-32, 15-34 and 15-36 respectively is at logical ONE. One or more of the output signals at logical ZERO is applied to the inputs of a AND/NAND gate 15-38. The output signal ALNSGTE 16 is applied to the input of an AND/NAND gate 15-50. If this is not a decimal multiply/divide instruction then the output signal DLNSCLDGTE-1-6 is forced to logical ZERO. This signal, applied to the input of an AND/NAND gate 15-74 forces the DE-LORN-G output signal to logical zero. Signals A-LNDA1, Al-NDA2, ALNDB 'I and Al-ND132 are applied to the inputs of AND/NAND gates 15-40, 15---42,15-44 and 15---46respectively. Logical ONE is applied to the other input terminals. The output signals of AND/NAND gates 15-40 and 15- 42 are applied to the inputs of an AND/NAND gate 15-52 and the output signals of AND/NAND gates 15---44and 15-46 are applied to the inputs of an AND/NAND gate 15-54. The output signals Al-NDAGTE 16 and Al-ND13GTE 16 at logical ONE indicate the length of operands 1 and 2 are less than 16 decimal digits. If the operands are not floating point operands and the adjusted length including scale factor adjustment are less than 16 decimal digits then signal DLONG, the output of AND/NAND gate 15-74, at logical 60 t t GB 2 115 586 A 35 ONE indicates that both operands are processed as short operands. The DLONG signal is applied to the input of an AND/NAND gate 15-56. The output signal DSHO T, at logical ONE, indicates that the operand being processed is-a long operand. Signal D1 2EQOVP is applied to the other input of AND/NAND gate 15-56 and when at logical ONE indicates that neither operand 1 nor operand 2 has an overpunched sign character which is the requirement for a short operand.

The DSHORT signal at logical ONE indicating a short operand is applied to the input of a AND/NAND gate 15-58. Signal UNSAID at logical ONE indicating a 9-bit pe character operand is applied to the other input of NAND gate 15-58. The output signal DSHORT 9 at logical ZERO is applied to an input of an AND/NAND gate 15-62. The output signal DLNGORST 9 at logical ONE is applied to the input terminal 1 of switch 15-72 b indicating a short 9- bit per character operand. 10 Logical ZERO is applied to input terminal 1 of switches 15-72 c and d.

Signals TDBO and TDB 1 are applied to input terminals 2 and 3 of switch 15-72 b and 15-72 c respectively. The boolean expressions are described supra and indicate the number of cycles of delay between the cycle on which the read request is made of cache 750 and a complete word is received by the execution unit 714. The ARWC adder 730-60 signal ARWC 6 is applied to input terminals 2 and 15 3 of switch 15-72 d and indicates a one word operand if at logical ZERO and a two word operand if at logical ONE.

Input terminals 4 and 6 of switch 15-72 a-d are selected for the descriptor 1 vector and store vector operations, respectively. Signal ROP-1 from control store 704-2 at logical ONE indicating an overpunched sign operand is applied to an input of an AND/NAND gate 15-2. The ZTNSAO signal 20 indicating a 9-bit per character operand when at logical ONE, is applied to the other input of AND/NAND gate 15-2. Either input at logical ZERO forces the signal D1 NEW 9 which is applied to an input of an AND/NAND gate 15-14, to logical ONE. Signals'7 NSA1 and ZTNSA2, at logical ONE, are applied to the other inputs of AND/NAND gate 15-14. Output signal D1 EQFLP at logical ZERO, indicating a floating point operand, is applied to the input of an AND/NAND gate 15-64. The output 25 signal D1 FLPORTSO at logical ONE is forced to logical ONE indicating a floating point operand.

If signals ROP-1 and ZTNSAO are at logical ONE, the Di NEW9 signal output of ANDMAND -gate 15-2 is at logical ONE. If signal FBfl-TX is at logical ONE then the output signal D1 EQOV ofan ANDMAND gate 1B-22 is at logical ZERO. This forces the output, signal D12EQOVP, of an ANDMAND gate 15-30 to logical ONE. If signal ZTNSA1 is at logical ONE indicating a trailing sign 30 then the output signal -D-1-EUTS-0 of a NAND gate 15-26 at logical ZERO forces the D1 FLPORTSO signal output of ANDMAND gate 15-64 to logical ONE. Signal D1 FLPORTSO at logical ONE is applied to input terminals 4 and 6 of switch 15-72 b indicating a floating point or overpunched trailing sign operand.

Signal D1 EQOVP, the output of AND/NAND gate 15-22 is applied to input terminals 4 and 6 of 35 switch 15-72 a indicating an overpunched sign operand.

Signal DBITX is at logical ONE if signals ZTNSA1 and ZTNSA2 at logical ONE are applied to an ANDMAID g ate 15-4 indicating an operand with no sign or an overpunched trailing sign or signals ZTNSAO, ZTNSA1 and TrNSA2 are applied to an ANDMAND gate 15-6 irdicatlng a 9-bit per character floating point or overpunched leading sign operand. Output signal D 1 EQFLP 9 of an ANDMAND gate 15-6 at logical ZERO forces signal DBITX, the output of AND/NAND GATE 15-16 to logical ONE.

Logical ZEROs are selected from terminals 4 and 6 of switches 15-72 c and d The firmware generates a result equals zero and an overflow check during the store vector operation. The descriptor 2 vector selects the input terminal 5 of switch 15-72 a-d. Signal D2EQOVP is applied to terminal 5 45 of switch 15-72 a and when at logical ONE indicates an operand with an overpunched sign. The D2EQOVP signal is generated in a similar manner as the D1 EQOVP signal which indicates an operand 1 with an overpunched sign.

Signal D2FLPORTSO generated in a similar manner as signal D1 FLPORTSO through AND/NAND gates 15-28 and 15-66 and is applied to terminal 5 of switch 17-72 b indicating a floating point 50 operand or an operand with an overpunched trailing sign.

Switch 15-72 c, d input terminals 5 are at logical ZERO.

The long input vector selects input terminal 7 of switch 15-72 a-d. Signals D 1 EQFLP and D2EQFLF are applied to the inputs of an ANDMAND gate 15-48. The output signal D 1 2EQFLP is applied to the inputs of AND/NAND gates 15-60 and 15-70 and when at logical ZERO, indicating a 55 floating point operand, forces signals D 1 2FLPOREL and D1 2FLPOROVP to logical ONE. The input terminal 7 of switch 15-72 a and 15-72 b at logical ONE indicates to the firmware to execute the descriptor 1 and descriptor 2 vectors.

If signal U-1 -2EQFLP is at logical ONE indicating scaled operands, then signal ALNSLTE63 at logical ZERO indicating a length of less than or equal to 63 decimal digits is applied to the input of AND/NAND gates 15-60 and 15-68. The output signals D1 2FLPOREL at logical ONE indicates both operands having a length of less than or equal to 63 decimal digits. Signal D1 2EQOVP is applied to the other input of AND/NAND gate 15-68. The output signal D1 20VPL63 at logical ZERO is applied to the input of ANDMAND gate 15-70. The output signal D1 2FLPOROVP at logical ONE indicates that 36 GB 2 115 586 A 36 both operands are scaled with an overpunched sign and the lengths are less than or equal to 63 decimal characters.

Signal ALNSLTE63 at logical ZERO is generated as the output of an AND/NAND gite 15-8. The input signal ALNS3 at logical ONE indicates a length of gLeater than 63 decimal digits. WYDV is at logical ONE since this is not a multiply/divide operation. D12EQFLP is at logical ONE since neither operand is a floating point operand.

Claims

1. A data processing system comprising: a cache memory for storing operands and instructions, each instruction including an operation code portion and also including descriptor information for describing characteristics of said operands; 10 an execution control unit including means for storing microword signals, said data processing system being responsive to said microword signals for executing operations specified by said instructions; a control unit for generating control state signals coupled to said cache and to said execution control unit, said cache and said control unit being responsive to said microword signals for transferring one of said instructions having descriptor information specifying a decimal numeric operation to said control unit from said cache, said control unit being responsive to said microword signals for transferring said operation code portion of said one of said instructions to said execution control unit, said execution control unit including means for selecting a series of said microword signals in response to said operations code portion, said execution control unit being responsive to said series 20 of said microword signals for executing the decimal numeric operation specified in the said instruction; a decimal unit coupled to said control unit and said cache and including means for storing said descriptor information in response to said series of said microword signals, said decimal unit being responsive to signals indicative of said descriptor information to determine the lengths of said operands, including means for receiving and aligning said operands when said operands are transferred to said decimal unit from said cache; and an execution unit coupled to said decimal unit and, in response to said series of microword signals, receiving said aligned operands from said decimal unit and performing said decimal numeric operation thereby generating a resultant long operand for transfer to said decimal unit, said decimal unit being responsive to said series of microword signals for generating start write signals and send 30 data signals, said execution control unit having address gbnerating means responsive to said start write signals and said send data signals for reading out said series of microword signals from said microword storing means, said data processing system being responsive to said series of microword signals for storing said long operand in said cache.

2. The system of claim 1 wherein said decimal unit comprises:

decimal unit control means coupled to said execution control unit and to said control unit, and being responsive to a plurality of selected signals from said microwords from said execution control unit and saiddescriptor information signals for generating said start write signals, said send data signals and register alid switch control signals; and operand processing means coupled to said execution unit and said cache and responsive to said 40 series of said microwords for receiving said long operand from said execution unit and responsive to said register and switch control signals for aligning and merging said long operand for transfer to said cache.

3. The system of Claim 2 wherein said decimal unit control means comprises:

decode means coupled to said execution control unit and responsive to said plurality 6f selected 45 signals from said microwords for generating a plurality of command signals; status means coupled to said decode means and responsive to sai plurality of command signals, said status means being further coupled to said control unit and responsive, to a plurality of control state signals for generating a first plurality of status flag signals; control means coupled to said control unit, said status means and said decode means, and 50 responsive to said plurality of control state signals, said first plurality of status flag signals, said plurality of command signals and said descriptor signals, for generating said start write signals, said send data signals, and said switch and register control signals; said status means further including means coupled to said control means, and responsive to a plurality of logic signals and responsive to said first plurality of status flag signals, for generating a 55 second plurality of status flag signals.

4. The system of Claim 3 wherein said control means comprises:

said storing means coupled to said control unit and responsive to said plurality of control state signals for storing said descriptor information signals; adder means coupled to said storing means and responsive to said descriptor signals, selected 60 ones of said plurality of command signals and said status flag signals for generating said start write signals, said send data signals and said switch and register control signals.

5. The system of Claim 4 wherein said adder means includes:

shift count means coupled to said- storing means and responsive to said descriptor signals for 37 GB 2 115 586 A 37 generating said shift signals representative of the number of decimal digit positions said operand is shifted in said operand processing means.

6. The system of Claim 5 wherein said adder means includes:

receive word count register means coupled to said decode means and said status means and responsive to said command signals and said status flag signals for generating and storing signals 5 representative of the number of significant words said decimal unit will receive from said execution unit.

7. The system of Claim 6 wherein said adder means further includes:

send word count register means coupled to said storage means and responsive to said descriptor signals for generating and storing signals representative of the number of words said decimal unit will 10 send to said cache.

8. The system of Claim 7 wherein said adder means further includes:

comparison means coupled to said receive word count register means and said send word count register means and responsive to a first plurality of signals representative of the number of significant words said decimal unit will receive from said execution unit, a second plurality of signals representative of the number of words said decimal unit will transfer to said cache, and said shift signals, for generating said register and switch control signals; said comparison means being further coupled to said status means and responsive to said status signals, said shift signals and said first and second signals for generating said start write signals and said send data signal when said first and second signals are in a predetermined relationship with each 20 other.

9. The system of Claim 8 wherein said comparison means is responsive to said first and second plurality of signals for generating comparison signals indicative of the relationship between the binary numbers represented by said first and second plurality of signals.

10. The system of Claim 2 or any claim appendant thereto wherein said operand processing means comprises:

receiving means coupled to said execution unit for receiving signals indicative of said long operand words in response to a first series of microwords, said execution control unit being responsive to said send data signals for generating said first series of microwords; merging means coupled to said receiving means and responsive to said register and switch 30 control signals for aligning and merging said long operand words for transfer to said cache in response to a second series of microwords, said execution control unit being responsive to said start write signal for generating said second series of microwords.

11. The system of Claim 6 or any claim appendant thereto wherein said receive word count register means includes receive countdown means responsive to said status flag signals for decrementing said signals stored in said receive word count register means each time said operand word is received by said decimal unit.

12. The system of Claim 9 or any claim appendant thereto wherein said send word count register means includes send count down means responsive to said descriptor signals, said status flag signals, said comparison signals, for decrementing said send word count register means each time said 40 operand word is transferred to said cache.

New claims or amendments to claims filed on 25th April 1983. Superseded claim 1.

Amended claim:- 1. A data processing system comprising:

a cache memory for storing operands and instructions, each instruction including an operation code portion and also storing descriptor information for describing characteristics of said operands; an execution control unit including means for storing microword signals, said data processing systems being responsive to said microword signals for executing operations specified by said instructions; a control unit for generating control state signals coupled to said cache and to said execution control unit, said cache and said control unit being responsive to said microword signals for transferring one of said instructions having descriptor information specifying a decimal numeric operation to said control unit from said cache, said control unit being responsive to said microword signals for transferring said operation code portion of said one of said instructions to said execution 55 control unit, said execution control unit including means for selecting a series of said microword signals in response to said operations code portion, said execution control unit being responsive to said series of said microword signals for controlling the decimal numeric operation specified in the said instruction; a decimal unit coupled to said control unit and said cache and including means for storing descriptor information signals in response to said series of said microword signals, said decimal unit 60 being responsive to said signals indicative of the descriptor information to determine the lengths of said operands, including means for receiving and aligning said operands when said operands are transferred to said decimal unit from said cache; and z 38 GB 2 115 586 A 38 an execution unit coupled to said decimal unit and, in response to said series of microword signals, receiving said aligned operands from said decimal unit and performing said decimal numeric operation thereby generating a resultant long operand for transfer to said decimal unit, said decimal unit being responsive to said series of microword signals for generating start write signals and send data signals, said execution control unit having address generating means responsive to said start write 5 signals and said send data signals for reading out said series of microword signals from said microword storing means, said data processing system being responsive to said series of microword signals for storing said long operand in said cache.

Printed for Her Majesty's Stationery Office by the Courier Press, Leamington Spa. 1983. Published by the Patent Office, Southampton Buildings, London, WC2A lAY, from which copies may be obtained 1 t 1