CA1145054A - Data processing system with means to align operands - Google Patents

Abstract

Abstract of the Disclosure In a microprogrammed data processing system the throughput of the sys-tem is increased during the processing of decimal numeric instructions by appara-tus which is conditioned by the instruction descriptors in advance of receiving the operands to align the decimal digits of the operand words as the words are received by the apparatus from memory. The descriptor information for each oper-and includes the scale factor, the position of the sign, the position of the most significant character within the word, whether it is a floating point or scaled operand, the number of bits in each decimal character, either 4 or 9 bits and the length of the operand. The apparatus is conditioned by the descriptor informa-tion to align the two operands for processing. The apparatus indicates to the microprogram the characteristics of the operand being processed thereby enabling the proper microprogram subroutine, that is, if the operand is a floating point or a scaled number, has 4-bit decimal digits or 9-bit decimal digits, has an over-punched leading sign or trailing sign, has an adjusted length less than or equal to 63 decimal digits, whether the operand is a long or short operand, and whether the resulting operand is equal to zero or has an overflow. The apparatus receives a long operand, greater than a predetermined number of words, which is the result of the calculation, assembles the resultant operand in accordance with an instruc-tion descriptor, and transfers the resultant operand to memory. In response to a microword indicating that the result of the decimal numeric calculation is a short operand, that is, a predetermined number of words or less, and in accord-ance with an instruction descriptor, the apparatus generates a count of the number of words of the resultant operand, the decimal unit will transfer to memory.

Description

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The apparatus strips zone bits, sign, e~ponent and non-operand characters from the operand when the operand is received from memory and appends the zone bits, sign, e~ponent and non-operand characters to the resultant operand when stored into memory. The control signals for stripping and appending information is enabled by shifter logical elements.
The apparatus receives a long operand, greater than a -predetermined number of words, which is the result of the calculation, assembles the resultant operànd in accordance with an instruction descriptor, and transfers the resultant operand to memory.
The apparatus predicts and indicates to the firmware during the processing of short operands, i.e., 15 decimal digits or less, ~the number of aligned words in the operand that will be received by the execution unit which performs the decimal instruction operation and the number of cycles ~f delay between the time a read request is made of cache memory for the first word of the operand stored in cache and time that the first word is aligned and assembled in the apparatus for transfer to an execution unit.
In response to a microword indicating that the result of the decimal numeric calculation i3 a short operand, that is, a predetermined num~er of words or less, and in accordance with an instruction descriptor, the apparatus generates a count of the number o~ words of the resultant operand, the ~

decimal unit will transfer to memory. ~ -50~

This invention relates generally to the processing of decimal numeric instructions by a microprogrammed data processing system.
Microprogrammed data processing systems include a main memory and a central memory. The main memory stores operands and instructions. The operands may be stored in various forms including decimal numeric characteristics.
The instructions for de~ining the processing of the decimal numeric instructions include descriptors for defining the characteristics o~ the operands which include the decimal numeric characters.
The control memory stores a plurality of microwords.
Each microword made up of a predetermined number of bits enables particular functions in the data processing system.
A series of microwords called a microprogram subroutine when processed in sequence enable the data processing system to perIorm a particular operation.
When the data processing system reads a decimal numeric instruction from memory, a field in the instruction defining the type of decimal numeric operation, for example, add two operands and store the resultant operand, selects from the control store the first microword of a subroutine which starts the addition process.
ID the prior art systems when the subroutine completes

2~ its process, another subroutine is called to determine what ~ 1~5~5~

process the system will ~er~orm next. This next process selected will depend upon the characteristics of the operand. If the operand is a 4~bit decimal character then one microprogrammed subroutine is selected, if the operand is a 9-bit decimal character then another micro-programmed subroutine is selected. The continuous testing of the characteristics oi' the operand as each subroutine is completed reduces the overall throughput of the sys-tem considerably, During the processing of a particular decimal numeric instruction many decisions are made. Each decision point requires a subroutine to test the operand to determine the location of the first microword oi the ne~t subroutine used in the processing sequence thereby enabling the control store to branch to that first microword.
U.S. Patent 3,570,006 issued to G.S. Hoff and M. .~liu, ~larch 9,1971, entitled "Multiple Branch Technique" discloses an apparatus i'or ef~ecting a multiple branching operation wherein a multiplicity`of branch addresses with corresponding test conditions arepre-established and the results stored ~0 pending the detection o-~ a "branch and stored test" signal.
Branch address registers store digital representations corresponding to an address or a portion of an address within ,an associated memory. Associated with each of the branch adders registers is a flop which is set as a result of the successful satisfaction of conditions existing within .

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-the system and`upon which the branching operation is conditioned.
A prior art system such as described in the Hoff patent contains considerable hardware to implement.
Digital computer systems execute instructions calling for the processing o~ decimal operands. The decimal operands are made up of a plurality of words with each word containing a plurality of decimal characters. A word may also contain information that is not included in the operand. The decimal characters include decimal digits being in the form of 4-bit decimal digits packed up to eight decimal digits per word, or 9-bit ASCII or EBCDIC decimal digits packed up to four decimal digits per word. The decimal characters also include sign characters and, for floating point instructions, e~ponent characters.
The operands are stored in memory and, in the prior art, are transferred to an arithmetic unit where the words are stripped of sign characters, exponent characters and non-operand characters. In addition, the 9-bit decimal digits `are stripped of the zone bits and pac~ed into words of up to ~0 eight decimal digits per word. This readily permits decimal arithmetic wherein operands containing 9-bit decimal digits are processed with 4-bit decimal digits in response to the instruction calling for a decimal arithmetic operation of the two operands.
Before the resulting operand is stored back in memory, 35~

however, the necessary si~n, exponent and non-operand characters must be added, as-well as the zone bits i~ the resulting operand is made up of 9-bit characters.
The Honeywell 6000 computing s~stem performed the merging of sign, zone bits, exponent and non-operand characters along with the decirnal digits into the words of the resulting operand using considerable combinational logic.
Microprogra~med computers perform this merging operation by microprogrammed subroutines shifting the decimal digits of the arithmetic result lnto the proper posi~ion within the word for and adding the sign, exponent, zone bits and non-operand information. Since the microprogrammed sub-routines per~ormed in a serial fashion, the system throughput was degraded.
Data processlng systems process data stored in memory in the form of decimal digits Computer instructions are also stored in memory. ~ome of the instructions when processed by the data processing system result in arithmetic operations being performed on the decimal digit~s. For example, a decimal numeric instruction may be processed by the computing system to add one set of decimal digits -opèrand 1, from one group of memory locations to another set of decimal digits ~rom another group o~ memory locations -operand 2, and place the result - operand 3, into a third group~of memory locations.

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Descriptors associated with the instruction define the characteristics of each of the operands. An operand may be a floating point number or a scaled number. Each decimal digit may have 4-bits or 9-bits. The descriptor also defines the number of decimal digits in the operand, the location of the decimal point, i.e., the scale factor, the character position within a word of the most significant character of the operand, and the location of the sign if the operand contains a sign, either in the most significant character position - leading sign, or the least significant character position in a scaled operand - trailing sign.
The instruction will indicate if the operand is ASCII or EBCDIC and if the sign is part of an overpunched character.
Prior art computing systems, for example, the ~oneywell 6000 family of computers brings the operands into the arithmetic unit right justified, then goes through a sequence of logic operations for aligning the operands so that arith-metic operations may be performed.
Data processing systems that are controlled through firmware were used to provide systems with less hardware to perform the same functions. However these microprogrammed systems required large numbers of firmware steps including branching to firmware routines to align the operands in order to perform arithmetic operations.
The above approaches to performing the operand alignment ~s~s~

resulted in limiting the performance of the computing system when performing decimal arithmetic instructions due to the large number of computer cycles required to align the operands.
This invention processes operand 3 in accordance with its descriptor for storage in memory.
Prior art systems, ~or example, Honeywell 6000 family of computers, stored operand 3 in a bank of registers with combinational logic setting up the pointers to identify the number and positions o~ leading and trailing zeros as well as the character si2e, 4-bits or 9-bits, and the position of the sign, trailing or ieading.
- Microprogrammed systems were developed to perform the same ~unctions as the hardware systems such as the Honeywell 6000 and at a reduced product cost; however, in certain areas, such as during the processing of decimal numeric instructions, a considerable number of firmware steps were required to condition the resultant operand 3 for storage in memory thereby reducing the system throughput during the processing of decimal numeric instructions.
For normal processing the maximum number of decimal characters in an operand is 64 characters. The Honeywell 6000'used hardware registers which were capable of storing the 64 characters. Ve~ rarely are operands 6a characters long. A large portion of the operands will require 15 decimal digits or less during normal business processing.

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Microprogrammed computing systems are developed to reduce the amount o~ hardwar~ requlred in systems like the Honeywell 6000 by processing the words of the operands under firmware control through the use of firmware sub-routines in a serial ~ashion. The microprogrammed systemwould only require hardware register to store a maximum of 15 decimal digits with the remainder stored in a scratch pad memory. Operands comprising from 1 to 5 words stored in main memory may have less than 16 decimal digits (up to four nine-bit decimal digits or eight four-bit decimal digits are stored in a word). The firmware therefore requires a considerable number o~ fixmware steps to load the maximum of 16 decimal digits into the register for processing.
Considerable time is spènt by the firmware in just looping, 1~ waiting for the words from main mbmory.
` Accordingly, it is a primary object of the present invention to provide a data processing system with improved ~hroughput.
It is another primary object of the present invention ~0 to provide a data processing system with improved throughput when processing decimal numeric instructions.
According to the present invention, there is provided a data processing system comp~rising:
a cache memory i'or storing operands and instxuctions, ~5 each instruction including an operation code portion and `;

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also including'descriptor informa-tion for describing characteristics of said operands;
' an execution control unit for storing microwords~
said data processing system being'responsive to said micro-words for executing operations specified by said operationcode portion of said instructions;
a control unit coupled to said cache and to said execution control unit, said cac~e and said control unit being responsive to said microwords for transferring one of . 10 said instructions and.said descriptor information specifying a decimal numeric operation to said control unit from said cache, said execution control unit being responsive to said microwords for transi'erring said operation code portion of said one of said instructions to said execution control lS unit, said execution control unit'being responsive to said operation code portion of said instruction for selecting a series of said microwords, said data processing system being responsive to said series of said microwords for `'executing said decimal numeric operation;
a decimal unit coupled to said control unit and said cac~e, said decimal unit storing signals indicative of said descriptor in~ormat'ion in response to said series of said microwords, said descriptor information signals conditioning said decimai unit in advance o-~ receiving said operands to ali~n said operands when said operands are transferred to said decimal unit from said cache; and ~45~

an execution unit coupled to said decimal unit for receiving said aligned operands from said decimal unit in response to said series of microwords and performing said decimal arithmetic operations.
The invention also provides a data processing system comprising:
a cache memory for storing operands and instructions, each instruction includlng an operation code portion and also including descriptor information ~or describing characteristics o~ said operands;
an execution control unit ~or storing microwords, said data processing system being responsive to said microwords for execution operations specified by said instructions;
a control unit coupled to said cache and to said execution control unit, said cache and said control unit being responsive to said microwords for transferring one of said instructions and said descriptor information specifying a decimal numeric operation to said control unit from said cache, said control unit being responsive to said microwords for transferring said operation code portion of said one of said instructions to said execution control unit, said execution control unit ~eing responsive ~o ~aid operation .code portion of said instruction for selecting a series of said microwords, said data processing system being responsive to sa'id series of said microwords for executing said decimal numeric operation;

~5~54 a decimal unit coupled to said control unit and said cache and storing said descriptor information in response to said series of said microwords, said descriptor information conditioning said decimal unit to align said operands when said operands are transferred to said decimal unit from said cac~e;
an execution uni~ coupled to said decimal unit and.
in response to said series of microwords, receiving said aligned operands ~rom said decimal unit, and performing sa1d decimal arithmetic operations thereby generating a resultant short operand for transfer to said decimal unit;
said decimal unit receiYing said resultant short operand, and in response to said microword, assembling said short operand into data word , in response to said descriptor signals, for transfer to said cache.
The invention further provides a data processing system comprising:
a cache memory for storing operands and instructions, `each instruction including an operation code portion and also including descriptor information for describing characteristics of said operands;
an execution control unit for storing microwords, said data processing system being responsive to said microwords for execution operations specified by said instructions;
a control unit coupled to said cache and to said ~ 5~35~

1~ ~

execution control unit, said cache and said control unit being responsive to said microwords for trans~erring one of said instructions and said descriptor in~ormation speci~ylng a decimal numeric operation to said control unit ~rom sald cache, said control uni~ betng responsive to said microwords for transferring said operation code portion of said one of said instructions to said execution control unit, said execution control unit being responsive to said operation code portion of said instruction for selecting a series of said microwords, said data processing system being responsi~e to said series of said microwords for executing said decimal numeric operation;
a decimal unit coupled to said control unit and said cache and storing said descriptor iniormation in response to said series of said microwords, said descriptor information conditioning said decimal uni~ to align said operands when said operands are transferred to said decimal unit from said cache; and an execution unit coupled to said decimal unit and in ~0 response to said series o~ microwords, receiving said aligned operands from said decimal unit and performing said decimal arithmetic operations thereby generating a resultant long operand for transier to said decimal unit, said decimal unit being responsive to said series o~-:~5 microwords for generating start write signals and send datasignàls, , 5~S~

said execution control unit being responsive to said start write signals and said send data signals for generating said series of microwords ior storing said long operand in said cache.
The invention ~urther provides a data processing system comprising:
a cache memory ~or storing operands and instructions, each of said instruction including an operation code portion and also including descriptor in~ormation for describing 0 characteristics of said operands;
an execution control unit for storing microwords, said data processing system being responsive to said microwords for executing operations speci~ied by said instructions;
a control unit coupled to sa1d cache and to said execution control unit, said cache and said control unit being responsive to said microwords for transferring one of .
said instruc.tion~ and said descriptor information specifying a decimal numeric operation to said control unit from said cache, said control unit being responsive to said microwords for trans~erring'said operation code portion of said one o~
said instructions to said execution control unit, said e~ecution control unit being responsive to said operation code portion o'i.said instruction for selecting a series of said microwords, said data,processing system being responsive to said series of said microwords ~or executing said decimal numeric operation;

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a decimal unit coupled to said control unit said location control unit and said cache for storing said descriptor information and reeeiving said operands in response to said series oi said microwords, said decimal unit further aligning said operands in response to said descriptor information signals;
an execution unit eoupled to said decimal unit for reeeiving said aligned operands in response to said series of mierowords and performing said decimal arithmetic operations, lO wherein said deeimal unit is further eonditioned by said descriptor information and a plurality of status flag signals generated in response to a selected field of said mieroword of said series of microwords for generating a plurality of vector branch signals for indicating to said execution eontrol unit, eharacteristics of said operands;
said exeeution eontrol unit being responsive to said plurality of vector branch signals for branching to a subroutine of said series of said microwords for processing said operands.
The invention further provides a data processing system eomprising:
a eache memory for storing operand words and instructions, eaeh of said operand words being coded to specify a number of types of information, said number o~ types of information ~5 ineluding decimal digits, sign eharacters, exponent characters 5~

and non-operand in~`ormation, each of said instructions including an operation co..e por-tion specifying a decimal numeric operation per~ormed by said system and also including descriptor informatlon ~or describing characteristics of said operand words;
~ an execution control unit for storing microwords~ said data processing system being responsive to said microwords for executing operations specified by said operation code portion of said instructions;
a control unit coupled to said cache and to said execution control unit, said cac~e and said control unit being responsive to said microwords for transferring one of said instructions and said descriptor information specifying a decimal numeric operation to said control unit from said cache, said control unit being responsive to said microwords for transferring said operation code portion of said one of said instructions to said execution control uni~, said execution control unit being responsive to said operation code portion of said instruction for selecting a series of said microwords, said data processing system being responsive to said series o~ said microwords for executing said decimal numeric operation;
~ decimal unit coupled to said control unit and to said cache, said decimal unit storing said descriptor information received from said control unit and storing ~45~5~

said operand words received from said cache, said descrlptor information conditioning said decimal unit to select said decimal digits of said operand words when said operand words are transferred to said decimal unit from said cache;
an execution unit coupled to said decimal unit for receiving said decimal digits in response to said series of microwords and per~orming said decimal numeric instruction thereby generating and transferring decimal digits specifying an arithmetic result to said decimal unit for forming resultant operand words for transfer to said cache;
wherein said decimal unit includes shi~ter means.for generating register and switch control signals for selecting said decimal digits of said operand words received from said cache, and also forming said resultant operand lS words received from said execution unit on the cycle said operand words are processed by said decimal unit.
A preferred embodiment of the present invention which includes a data processing system including a cache memory ~hich stores instructions including descriptors and operands, a control unit which receives the instructions and descriptors from cache, an execution control unit which receives the instructions from the control unit to generate a series of microwords whi.ch enables the data processing system to execute the instructions. Ths system also includes a decimal unit which is operative during the processing of decimal arithmetic.

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operations, and unaer microprogram control receives the descriptors and operands from cache and aligns the operands by interpreting the descriptor ~ields defining the operand, and anexecution unit which receives the aligned operands from the decimal unit and performs the decimal arithmetic function specified by the instruction.
The decimal unit receives a descriptor defining operand 1 and a descriptor defining operand 2 at the start of the load operation. The decimal unit stores the scale factors for operand l`and operand 2, The scale factor is the loaation of the decimal point. A scale factor of zero locates the decimal point to the right o~ the least significant position. A scale factor of plus two ~oves the decimal point 2 positions to the right thereby adding two zeros to the operand. A scale factor of minus three moves the decimal point 3 positions to the left, the thousandth's position. The decimal unit also stores the descriptor 1 and descriptor 2 information containing the operand lengths, the data type, sign type bits, location of the character pointer, i.e., the character location within the word of the most sîgnificant character into registers in the decimal unit.

The decimal unit calculates the number of words of operand 1 that will be received by the decimal unit, and the number of words of operand 1 that will be sent for ~ 5~54 e~ecution. This allows the decimal unit to determine when operand l has been processed through the decimal unit to allow the a~ove calculations to be made for operand 2 before it is received.
The firmware con~rols the loading of the descriptor information defining the operands into the decimal unit.
The firmware indicates to the decimal unit to read each operand through the decimal unit, The decimal unit indicates to the firmware the number of words of each operand to be transferred out of the decimal unit for execution.
The decimal unit as described in the preferred embodiment increases the throughput considerably by setting up the logic in the decimal unit in parallel in advance of receiving the operand, then aligning each operand "on the fly" as it passes through the decimal unit. This is to be compared to one form of the prlor art wh~reby the operand was stored in a register right justified and manipulations made to the operand to properly align it. The firmware approach tested the operand, branched to different microprogram subroutines and serially controlled the hardware to manipulate the operand to properly align it.
In the decimal unit the operand characters are stripped of zone bits, sign characters i~ applicable, and exponent characters if applicable and packed into words with a 25; maximum of 8-decimal digits packed into one word.

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Operands are de~ined and processed as short operands if each operand involved in the decimal arithmetic load operation has 15 decimal digits or less. Operands are defined and processed as long operands if each operand involved in the decimal arithmetic load operation has more than 15 and less than 64 decimàl digits.
inter alia This invention pertains/to the processing of short operands. Short operands are stored in cache in from one to five ~ords. For example) operands having fifteen decimal digits and a leading sign and made up of 9-bit A~CII or EBCDIC characters are stored 4-decimal digits to a word.
If the sign character is stored in the second, third or fourth character position of the most significant word, then the operand, 15 decimal digits and the leading sign character is stored in ~ive word~; In the decimal unit, the five word operand is compressed into 2 words of 8 and 7 decimal digits each and sent to the execution unit for processing.
Apparatus in the decimal unit calculates the number of words that will be sent to the execution unit. If both operands received by the decimal unit from cache are short operands then the decimal unit calculates the number of cycles between the time the first read command is sent to cache and the first data word is sent to the execution unit.
25` Assuming the first word received from cache contains 1~5~5~

the sign character in the 4th word position. I~ that word could ~ill a register ior transier to the execution unit, the firmwa~e would require a zèro cycle delay. The second word received ~rom cac~e contains ~our 9-bit characters. I~
- 5 the ~irst and second words could fill a register for transfer to the execution unit, the ~irmware would require a one cycle delay. In the above example the i'irst and second ords would not ~ill the register since they contain only 4 characters. The third word received from cache contains ~our 9-bit characters and i~ the ~irst, second and third ~ords will fill the register then the firmware would require a two cycle delay, as is the case.
Apparatus in the decimal unit predicts, for the short operand, the n~mber o~ words to be sent to the execution unit and the number o~ cycles o~ the delay required by the firmware. This prediction in~ormation is sent to the e~ecution control unit by means of thePK VCTR signals to cause a branch o~ a microprogram subroutine which has the exact ~irmware steps required to process the operand thereby eliminating unnecessary looping and branching.
The ARWC adder 730-60 indicates the number of words o~ the operand the decimal unit will send to the execution unit. For the short operand the ARWC 6 bit position at logical ONE indicates that the decimal unit is storing a - 25 short~ operand. The ACPNB adder 730-52 and the ACPDF adder , ~4S~5~

730-52 indicate the number of cycles of delay for 4-bit and 9-bit per character operands. The information of the number of words in the short operand and the number of cycles of delay required of the ~irmware is available to the firmware in response to firmware commands.
This invention discloses the alignment and merging of the resultant short operand received by the decimal unit from the execution unit. The resultant operand is processed in the decimal unit ln accordance with a descriptor stored in the decimal unit describing the characteristics of the resultant operand as it is to be stored in memory.
If the resultant operand stored in the registers of the execution unit contains 15 decimal digits or less~ firmware signals indicate that the resultant operand is to be treated as a short operand even though the descriptor describing the resultant operand indicates a length of greater than 15 decimal digits.
The decimal unit responds to a firmware command indicating a store operand operation by delivering words in the proper format to the cache. The execution unit and control unit, under firmware control, prepare the write address and write commands for cache to write the words transferred from the decimal unit into cac~e. Once started the transfer of words between the de¢imal unit and cache continues without further firmware inter~ention of the decimal unit.

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The execution unit under firmware control first sends the least significant digit to the decimal unit where it is sbored in a RPK register 730-162 and then sends the most significant word to buf~er 730-168 of the decimal unit. If the short resultant operand was only one word in length then the most significant word would contain all zeros.
A send word count RRWC register 730-88 in the decimal unit stores the internal location of the most significant data word to be transferred from the decimal unit to cache memory. The second word count register is decremented each time a word made up of 4-bit characters is sent to cache.
The send word count register is also decremented each time a word made up of ~-bit characters is sent to an odd address in cache in response to a firmware command.
The contents of the send word count register is generated by the descriptor information stored in the decimal unit.
A shift count RDSC register 730-58 stores information indicating the number of decimal digit positions the resultant operand is shifted inthe decimal unit. A negative shift count indicates a left shi~t and a positive shift count indicates a right shift.
The decimal unit sends words containing all zeros to cache in response to firn~are commands until the send count register stores signals lndicating that the operand word contàining the most significant character is to be transferred 5~35~

to cache. The'word may include decimal digits or the opérand word, or may contain'only a leading sign character.
Data words are aligned and merged in the decimal u~it and transferred to cache. When the number of words of the operand defined by the descriptor equals the number of words transferred to cache as indicated by an RWPC register 730-84 then the firmware completes ~he store operation and the system starts the processing of the nex~ instruction.
The relationship between the counts stored in the R~C
register and the RRWC register initiates register and switch control signals for sele~ting the ZPKR switch 730-164 and ZPKL switch 730-166 out~ut signals in a predetermined sequence.
The instant invention further discloses the alignment and merging of the resultant long operand received by the decimal unit from the execution unit. The resultant operand is processed in the decimal unit in accordance with a descriptor stored in the decimal unit describing the characteristics o~ the resultant operand as it is to be 'stored in cache memory.
The decimal unit responds to a firmware command by counting the number of significant words of the resultant operand and storing that'count in an R~C receive word count register. The decimal unit also calculates from the descriptor in~ormation the number of words the decimal unit 25' will send to the cache and stores the value in an RRWC send word count register.

The long operand store operation starts with the execution control unit reading out of the execution control store, a microword which includes signals coded to specify a "store operand in the decimal unit operation". On the next cycle the execution control store reads a microword which results in the system testing the decimal unit start write signal line. The DSTRT-WRT start write signal line from register and switch control 730-91 indicates the relationship bet~een the counts in the RWPC register 730-84 and the RRWC register 730-88. The start write signal line is at logical ZERO when the count in the RWPC register is greater than the count in the RRWC register indicating that the number of operand words in the execution unit ls greater than the number of operand words defined by the descriptor.
This is normal since the execution unit stores 64 decimal digits or 8 words whereas the descriptor defining a long operand would indicate from three to eight words for the long operand. The decimal unit forces words containing zeros `to be processed by the decimal unit meanwhile decrementing ~0 the R~PC register until the RWPC register count equals the RRNC register count. This forces the start write signal line to logical ONE provided that a complete operand word can be`assembled in the decimal unit. If a complete word cannot be assembled in the decimal unit then the firmware initiates the transfer of the next word from the execution C35~

unit to the decimal unit and on the cycle that a complete word is assembled in the decimal unit the start write signal line is forced to logical ONE and the operand word is aligned, merged and transferred to cache.
A DSEND-DATA send data signal is forced to logical ONE
when the decimal unit requires the next word from the execution unit. If the descriptor describes a 9-bit decimal digit resultant operand for storage in cache then the send data signal is at logical ONE on alternate cycles since two operand words are generated in the decimal unit to each word received from the execution unit.
The decimal unit calculates the position of the most significant decimal digit within the operand word of the resultant operand received from the execution unit. The decimal unit also calculates the position of the most significant decimal digit within the operand word as it is to be stored in càche. These calculations are combined to determine the number of decimal digits the resultant operand received from the execution unit to be shifted in the decimal unit.
This shift is stored in an RDSC register 730-58. The direction of shift controls the sequence of the store operation. For a positive shift, RDSCO-at logical ZERO, the sequence is as described supra. For a zero shift or a negative shift, RDSCO
at logical ONE, the above sequence must be delayed a cycle - 25 un~il both the most significant data word and the data word ~451~

following the most significant data word are both stored in the decimal unit.
The store operation is completed when the number of operand words specified b~ the descriptor is transferred from the execution unit, through the decimal unit where it is aligned and merged, and written into cache.
The system also includes a decimal unit which is operative during the processing of decimal arithmetic instructions, and under microprogram control receives the descriptors from the control unit and receives the operands from cache. In the decimal unit the operand characters are stripped of zone bits, and also if applicable, sign, exponent and non-operand characters and assembled into words of up to eight decimal digits per word for transfer to an execution unit. The operand word is stripped of non 4-bit decimal digit information on the cycle the operand word is processed through the decimal unit.
The execution unit performs the decimal arithmetic specified by the instruction on the two operands and transfers the resulting third operand to the decimal unit in the form of words made up of 4-bit decimal digits.
The decimal unit processes the third operand as specified by a descriptor describing the third operand. The descriptor enables the logic in the decimal unit during a store operation to merge the sign, exponents, zone bits and non-operand s~

characters with the decimal digits and transfer the merged words to cache at an address specified by the descriptor under microprogram control. The information is merged into the operand word on the cycle the word is processed through the decimal unit.
The apparatus comprises a plurality of switches and means for controlling the switches. A four level ZSMR switch 730-180 adds the sign, exponent and non-operand characters (rewrite) to the operand as the decimal digits of the third operand are received from the execution unit, processed in the decimal unit and transferred to cache.
Level O of the ZSMR switch expands the 4-bit decimal digit from a 32-bit word to a 36-bit word. Leading or trailing sign characters are added to the operand ~hrough level 1 of the ZSMR switch. One position of level 1 of the ZS~R switch is selected if the descriptor specifies 4-oit characters and two adjacent positions of level 1 of the ZS~IR switch are selected i~ the descriptor specifies 9-bit characters. The selection is made by the SIGNM output signals of the s~lifter 730-118.
The exponent is added to the third operand, specified by the descriptor as being floating point operands, through le~el 2 of the ZSMR switch 730-180. Two adjacen-t signals at logical ZERO input the EXPM shifter 730-122 to select two of the EXPM 0-7 output signals of the shifter to activate 5~35~

the two selected exponent positions of the trailing word of the floating point third operand.
The rewrite information is added to the leading word and trailing word, if applicable, through level 3 of the ZS~R switch 730-180. The RE~YUM shifter 730-149 selects the non-operand positions of the leading operand word and the REWLM shifter 730-114 selects the non-operand positions of the trailing word ~or transferring the rewrite information through the ZEWR switch 730-178 and through the selected positions of the ZS~R switch 730-180.
During the load operation, that is, the decimal unit receiving the operand from cache for alignment, the sign and exponent characters are stripped from the operands in the ZID switch 730-150 under control of the ZIDML shifter 15 730-128 and the ZIDMU shifter 730-130 which mask out information to the right of the least significant decimal digit in the word of the operand containing the least significant decimal digit; and masks out information to the left of the most ~significant digit.
Also during the load operation the ZCRDG~I shifter 730-145 selects the level 2 position of the ZID switch 730-150 for replàcement o~ the overpunched sign character with the specified decimal digit in an ASCII or EBCDIC operand. The overpunched sign decimal character is a single 9~bit character which is coded to indicate a sign and a decimal digit.

~l~S~S~

The descriptor information stored in the decimal unit describes the characteristics of the operand. Descriptor bit position 21 de~ines the operand as having 9-bit characters when at logical zero and 4-bit characters when at logical one. Bit positions 22 and 23 define the operands as follows:
Bit Positions Normal Overpunched Sign 22, 23 leading sign, leading sign floating point O O leading sign scaled leading sign scaled 1 0 trailing sign trailing sign scaled scaled 1 1 no sign trailing sign The length field, descriptor bit positions 30-35 and the scale factor ~ield, bit positions 2~ through 29 together with the field de~ined b~ bit positions 21 through 23 provide inputs to an ALNS adder 730-24. The output signals indicate the adjusted length o~ the operand field.
A vector branch switch 13-72 in the vector branch logic 730-15 enables the PK-VCTR 0-3 signals in response to the [lPKVCTR, ~2PKVCTR and ~4PKVCTR sigr.als which are generated in response to predetermined DUCMD command signals and status flag signals. The DUCMD command signals are generated in the decimal unit in response to microword signals from the execution control store 701-~.
In response to a ~irmware request for the type length ~1~5~

vector, the decimal unit indicates to the firmware whether the operand is a short or long operand, 4-bit characters or 9-bit characters and if a short operand, whether there is an overpunched sign in the descriptor 1 operand or descriptor 2 operand.
In response to a firmware request for the descriptor 1 vector, the decimal unit indicates if the operand 1 is a floating point or scaled operand, an overpunched leading or trailing sign scaled operand or indicates to the firmware to execute the descriptor 2 vector.
In response to a firmware request for the descriptor 2 operand, the decimal unit indicates if the operand 2 is a floating point or scaled operand with overpunched leading or trailing sign.
In response to a firmware request for ~he store vector, the decimal unit indicates if the resultant operand equals zero or there is an overflow.
In response to a firmware request for the long input `vector, the decimal unit indicates the comparison between the operand lengths and 63 for scaled operands and also to e~ecute the descriptor 1 and descriptor 2 vectors.
Arrangements according to the invention will now be described by way of example and with reference to the accompanying drawings, in which:-:

3~

.

Figure 1 i8 an oveE311 bloc~ di~gram of the host processor. The cache unit ~nd sy~tgm integration unit are shown connectod to th~ host proce eor.
Figurc 2 is block di~gram of the execution uni~
and ~ portion of tha char~cter uni~ of the hos~ processor.
Figure 3 is a de~allsd block di~gram of the decimal unit.
Figure 4 iq an overall block diagram of the decimal unit.
Figure 5 shows the in~truction and deacriptsr formatsfor-two declmal numesic i~structions.
Fi~ur~ 6 i8 8 logl~ diagram of ~he leading zero count circuit~. .
Figure 7 i5 ~ logic diagram of the effective digit circuits.
Figure 8 i8 a diagr~m of the vector branch logic.

5`~35~

.

~ 37 General De~c_iption of Processor 700 - Figur~ 1 ~ eferring to ~lqux3 1, it i8 Been that a host processor 700 includ~s an exec~t~on control unit 701, a control unit 7n4, an executlon unit 714, a character unit 720, an auxiliary arithmetic ~nd co~trol unit ~AACU) 722, a multiply-divide unit.728, and a doc~mal unit 730 which are inter-connocted as ~hown. AddltionAlly, the control unit 704 h s a nu~b~r of intsrconn~tionY to the cache 750 as ~ho-rn.
Ths execution control unit 701 includes an execution control ~tore addr~3 pr~p~ration ~nd bran~h unit 701-1, and an execution control ~tore 701-2. The store 701-2 and unit 710-1 aro interconnQe~2d Vi8 buse~ 701 3 and 701-6 as shown.
The control unlt 704 includes a control logic unit 704-1, a control stor2 704-2, an address preparation unit 704-3, d~t~ ~nd addre~s output circuit 704-4, an XAQ register aection ?04-S which interconnect as sho~.
` The control unit 704 provides the necessary control for per~orming add~e~s proparation operations, instruction 20 fetching/execueion operation3 ~ and the sequential control for various cycle~ o~ operation and/or machine states. The control i8 generated ~y logic circuits of block 704-1 and by the e~cution co~rol unit 701 for the various portions of the control unit 704.
The XAQ register section 704-5 includes a number of program visible regi~tQrs suc~ as index register~, an accumulator register, and quotient register. O~cher program visible registers such as ~he instruction counter and address regl~t~rs are lncluded within the address preparatlon unit 704-3.
A~ ~een from P~ gure 1, the section 704-S recei~es signals from unit 704-3 representative of the contents of the instruction coul~ter via lines RIC 00-17. Al~o, lines ~s~

~RESA 00-35 apply output signals from the execution unit 714 corre~pondin~ to the ~e~ult~ of operations perfonned upon varlous operands. The ~ction 704-5 al50 receive6 an output ~ignal from tha auxlliary Arith~etic and control unit via l~no~ RAAU0-8.
~ ho R~ction 704-5 provide~ signals representative of the content~ of one o~ the regi~ters included within the ~ection as an input to the addres prepara~ion unit 704-3 via the line~ ZX0-20 ~nd ZXA 24-3S. The address preparation 10 urlit 704-3 fonY~rds the information through a switch to the execution un1t 714 via ~h~ lines ~DO 0-35. Similarly, the contents o certain o~es of the re~ sters contained within .~ection 704-5 can be tran~erred to the execution unit 714 via the line~ ZEB 00-~5. Lsstly, the contents of selectad ones of these regis~ars ca~ be tran~ferred from section 704-5 to the multiply/d~vide unit 728 via the lines ZAQ 00-35.
The address pr~par~on unit 704~3 generates addresses from the contentq oP var~ous regist~rs contained therein and applies the re~ultant logical, effective and/or a~fiolute addre39es for di~tribution to other units along the lines ASPA 00-35. The addre~ prep~ratlon unit 704-3 receives the r~sult~ o~ operation~ perfonmed on a pair of operands by the execution unit 714 via the lines ZRESB 00-35.
The unit 704-3 receiv~s ~ignals representative of the con~ents of a pais of ~as~ pointer registers from the control logic unit 701 vla the line~ RBASA and RBASA0-1.
Outputs from the multlply~divide unit 728 are applied to the addr~s~ prep~ration unit 704-3~ Lastly, the con~en~s of a secondary instruction reqister ~RSlR) are applied as input to the u~it 704-3 via the lines }ISIR 00-35.
The data and addrese output circuits 704-4 generate the cache memor~ address signals which it applies to the cache unit 750 via the lines RAD0/ZAD0 00-35. These address _ . . ... . _ . _ 5'~
~' signals correspond to t~s ~i9rlAlS applied to one of ~che ~et~ of ~nput lino0 ZDI ~0-35, ASFA û0-35 and ZRE53 00-35 selected by 8witchel8 incl~d,od within t~e circuit3 of bloc3c 704-4. Al~o, wo~d addrss~ slgnals aro applied via ~he lines s ASFA 32-33.
Tho control lo~ c unit 704-~ provides data path which ha~e ~n lnt~r~ace wlth various urlit~ included within the cach~ ursit 705. 5h~ s ZIB 00-35 provide an inter~ace with an ln~ts~uc ion bu~or included within the cache 750.
10 The lin~s ZDI 00-35 are wsd to tran~fer data ~ignals from the cach~ 750 to the cs: ntrol logic unit 704 1.
A~ ~oen rrom Figur~ 1, ~e control logic ~2nit 704-1 provide~ a number of gxoups of output signals. Tha~e output slgnals include the coa~tents of cortain registers, a3 for xampl~, ~ b~sic Ln6truction register (RB}R) whose contents are appl~ed a~ an input to control store 704-~
via the lines ~BIR 18-27. The control logic unit 704-1 recelves cartain control ~ign~18 read out from control store 704-2 vla th8 li~e3 C~SD0 13-31.
The control lo~ic unit 704-1 al30 includes a secondary instruction regists~ (RSIR) which i~ losded in parallel with the ~a~ic in~truction register at the start of processing ~n instruction. m e contents of the secondary instruction ragi~tor RSIR 00-35, as previously mentioned, 25. are applied as input8 to ~he address preparation unit 704-3.
Additionally, a portion of the contents of the secondary in~truction regl~er ar~ applied as inputs to the auxiliary arithmatic control unit 722 via the lines RSIR 1-9 and 24-35, and to ~he dec~mal unit 730 via the lines RSIR 21-35.
The control _tore 704-2 as expl~lned herein p~ovide3 for an initial dacoding o~ program in3truction op-codes and therefore-is ~rranged to lncludP a number o~ storage location-Q (1024), one ~or each pos~ le instruction op-code.

. 3S

As mentioned, ~lgnal~ applied to lines RBIR 18-27 are applied as input3 to co~trol 8 ore 704-2. The~e signals select one of tho posai~le 1024 stor3ge locations. The contents of the Relect~d ~torag~ location are applied to the llne~ CCSD0 13-31 ~nd to CC5D0 00-12 as shown in FigurQ 1. Tho slgn~l~ euppll~d to lines CCSD0 00-12 corres-pond to a~dress ~ whlch are used to address the axecution conbrol unlt 701 ~g explained herein.
ThQ oxecutlon unit 714 provide~ for in~Ytruction 10 execution whQr~in unl~ 714 perfo = ~rithmetic and/or shift op~ations upon opera~d3 ~elected ~rom the various inputs.
The rasults of 6uch ope~tion~ are spplied to ~elected output~. $he execution un~t 714 recaives data from a data input bu- which c~rra~ponds to line3 RDI 00-35 which have 15 as l:heir sourc~ the con~rol loyic unit 704~ he contents of the accumulator ~nd ~uokient regis~ers included within section 704-5 are applied to the execution unit 714 via the line~ Z~B 00-35 aR m~nbioned praviously. The signals appliad bo tha input bu~ llnes ZDO 00-35 from the address preparatlon unit 704-3 are ~pplied via switches included within thn execution unlt 714 as ou~put signals to the lines ZRESA 00-35 and.ZRESB 00-35, ac shown in Figure 1.
Addition~lly, exe~ution unlt 714 receives a set of scratch pad address signals rrom the auxiliary arithmetic and 2S control unit 722 appli~d via the lines ZRESPA 00-06.
Addition~lly, the unit 7~2 also provides shift information to the unit 714 vl~ thQ lines Z~SC 00-35.
The char~cter unit 720 i~ used to execute character type instructionq which require such operations as trans-lation and editing of d~a fields. As explained herein,these types o~ lnstructions are referred to as extended instruction set tEIS) instructions. Such instructions _ __ (35 ~; 3b which the char~cter un~t 720 executes include the ~ve, scan, compare typ~ tructions. Sign~ls representative of operanas are appllsd ~ lines ~E5~ 00-35. Information as to tho type o chDx~ctor po~ition wi~chin a word and 5 the nu~b~r of bits ~s l~pplied to the ch~racter unit 720 via the iRpUt lines ~D~ 00 07.
Inforn~tion r~pr3~0rlt~tive of the results of certain data opQrations is ~ppllod to the unit 722 via the lines ZOC 00-0 8 . Such ln~orfflation includes e~?onent data and 10 data ~n hex~decim~ oxm. The character unit 720 applies output oporand dat~ and control inform~tion to the unit 722, the unlt 730 and the unlt 728 vl~ the line~ RC~U 00-35.
The auxiliary arithm~l:ic and control unit 722 perfonns arithmetic operation~ tapon eontrol information such a~
exponents we~d ln i~loating point operations, calculates operand lengths ~nd poin~rs and generates count information.
The results of thes~ op~r~tions ar~ applied to execution unit 714 via the linea Z~PA 00-06 and lines 2RSC 00-06 as mentioned previously. Inf~nnation ~ignals corresponding 20 to char~cter3 such a 9-bit characters, 4-~it charact~rs, decimal data convertQd ~rom input hexadecimal data, quotient infor;~ation and 8ign info~mation are applied to section 704-5 via the lineR RAAU 00-0 8 .
As seen from Figur~ 1, the unit 722 receives a number 25 of inputs. C~aracter pointe~ information is applied via the lines ASFA 33-36. EIS numeric scale factor infor-mation are applied to the unit 722 via the lines RSIR 24-35.
Other signals relating to fetching of specific instructions ar~ applied via the lin~s RSIR 01-09. Exponent signals 30 for ~loatlng point data are applied to the unit 722 via .

~- 114505~

the lines ZOC G0-08 whll~ floatlng po~nt exponent data signala from unit 704-1 ~re applied via the lines RDI 00-08.
Shift count info~m~tlon signal~ for certain ins~ruotions ~e.g. binary shl~t lnstructlons) are ~pplied to the uni~
~'S via the lin~s R~ 17. AB concQrns the input si~n~ls ppli~d ~o tha lin~ RC~U 00-35, iine~ 24-35 Apply signals corrospondln~ to tho l~ng~h of EIS instruc~ion fields while 18-23 apply addro~a modification slgnal6 ~o the unit me multiply/dlvid~ unit 728 provide~ for high-speed execution o~ multiply 2nd di~ide instruc~ions. This unit -~ mdy be con8idered convsntional in d~slgn and may take the form of tha multiply un~t described in U.S.-Patent ~,041,292 i~ which i8 ~igne~ to tlae~ 8ame ~Bsignea ~s named herein.
The unit 728 as eeen ~rom Figure 1 receives multipler.
dividend and divisor input signals via the lines RCHU 00-35.
The multiplic~nd input ~ignal from registar section 704-5 3 are applied vi~ tho l~nas Z~Q 00-35. The re~ults of the calculations perform~d by the unit 728 are applied as 2~ output signals to *e llne~ ZMD 00-35.
The declmal unit 730 is operative under firmware control during the process~ng of decimal numeric instructions.
The instruction for~at and its related descrip~or words are described in grPater detail with re~erence to Figure 5.
The instructlon word and the descriptor ~ord information received by the de~imal unit 730 via lines RSIR 21-35 and ~SFA 33-36. m ey conditio~ the decimal unit 730 to recei~e the oper~nd`d~scribed ~y the descriptor word from cache 750 via llne ~ 0-35. ~h~ decim~l unit 730 strips the sign character and exponent characters from the operand word, packs thQ data into up to aight 4-bit characters per word, stores the dat~ into 32-bit words, aligns ~nd transfers the .~: `~ *~ s~

~ 3~ .

.
data word~ to ~ e ex~c~tlon unit 714 ~ria line~ RDOD 00-35, ZMD 00-35 4nd ZDO 00-35 . DAta words stored in cache include up to four 9-bit chasact~rs of 2ight 4-blt characters in a 36 bit word. ~e 9-bit c}aaLracter lncludes fi~ one bi~s 5 and four dat~ bits. ~h~ zone bits ara stripped from th2 9-bit charactor ~n~ the romalning d~ta bits ars packed into a 32-bit rogi~tar which n~y conta~n up to two cache dzlta wordt~ up of 9-bit ~aractars or one cache data word msde up o~ 4-bit chAract~rs. ~he packed da~a words of the oparan~8 are a~8 3nib1~d in t~e execution unit 714 as~d proce8~sd in accosdas~ce with the decimal numeric instruction.
The operand r~pr~ ng tbe aesired result of the numeric in~truction i3 tran~orrsd to the decimal unit 730 via lines ZRESA 00-35 to tho ~haract~r unit 720 and then t~ the decimal ~nit ?30 via llnes RCH~ 4-35. There, the operand iR proc~ss~d in accordan~e with the ooded information in a da~crip~or word. The ope~and is unpacked, required ~igns and expon~nt~ addad, vl~ lin~3 ZADSP 3-11, EBCIDIC or ASCll zon~ character3 ~re adde~ if 9-bit decimal char~cters are indlcated by the de~crlptor word coded lnformation, and ~tored back in cach~ 750 ~t an addre~s specified by an addra~ ld in th~ d~crlptor word. The data is stored in c~ch~ 750 v~a line3 RDOD 00-35, ZND 00-3S, ASFA 00-3S
and RADO~ZAD0 00-35. Tho decimal un~t 730 i5 under firmware cDntrol via lines M~M-D0 88, 89, 94-97. P~-VCTR 0-3 signals ~ignal~ ~rom the d~cimal unit 730 indicate to the execution addres~ ~nd branch circuit ~01-1 ~tatu3 informati~n in respon~ to firmw~re comm~nd~ recei~ed by the deci~al unit 730 via the lin~ MEM-DO ~8, 89, 94-97. The PK-VCTR 0-3 30 sign~ rec~ived by th~ ~x cution addres~ and branch 701-1 re3ult~ ~n the ex~cutlon control store 701-2 branchin tc~ a B - particular~ microprogra~ ~routine. ~==~
937 an~itled "Mult~ple Control Store Microprogra~mn~le Control Unlt Includ~ng Multiple Function Register Control 35 Field" de~cribed the ~r~nchinq. loqic associated with the execution control ~ore 701-2.

. . _ . . . _ s~
_~ 39 Dato. and oontrol ~ignAl33 are tr~nf~ f~rred between cache 750 and ~n SIU 100 v~a th~ data interface line 600 and between c~che 750 ~d ~ prt~ 880r J00 via the lines of inte~face 604. ~tly, the cache unit 750 receive~
S add~ess ~nd data. E~ign3~ rom the data and address output circuits 704-4 ~ the lin~s RA~0/ZAD0 00 35 and .the lines ASFA 32-33.

Executlon Unit 714 ~ us~ 2 lhe unit 714 inclu~los ~8 major ~its, addressable 10 tempor~ gister ban3c~ 714~10 and 714~12, an arithmetic logic un~ t ~A~U) 714-20, R shi~ter 714-24 and a scratchpad mE~n~ry 714~30. Ad~ltio~ lly, the unit 714 includes a num~er of multlposieion data aelsctor .~witches 714-15, 714-17, 71d-22, 714-26, 714-28, 71d~34, 714-36 ~nd 714-38 15 ~o provlde flexibility in select~ng operands and output re~ultq .
In operatlon, tha operands are selected vi~ the ZOPA swltch 714-15 and ZOP~ switch 714-17 from one of the registar~ o~ the b~ks 714-12- and 714-10 or from other 20 input llne~ ~uch a~ 2EBo-35 or RDIo-35 as shown. The ALU
714-20 and ~hi~tQr 714-24 perform~ operations upon the selectsd operands cnd th~ re8ult8 are selected via the awitches 714-24, 714-36 and 714-38 to be applied to the output bus ' $nes ZRESA 0-35 and Z~ESB0-35 . Sirni1arly, the contsnts of a scratchp~d loca~on selected via signals applied to the ZRSPA 0-6 lin~s by the AACU unit 722 can be read out via the ~wltches 714-34, 714-36 a~d 714-38.
The selectod outpue ~e6ults or other data are there-aftar lo~ded lnto othar r2gistes~ within proce~sor 700 including the temporary rogister banks 714-12 and 714-10 or the scratchpad mamDry 714-30 of execution unit 714.

_. .

~5~5~

In greater detail, the sources of operands are identical for both the ZOPA and ZOPB switches 714-15 and 714-17. The selection of switch position for the ZOP~
switch and ZOPB switch is under the control of the microinstruction word. The ALU 714-20 performs logical, decimal and binary operations upon the selected operand data under the control of the microinstruction wordn The shifter 714 24 is a combinational logic network used to align, shift or rotate binary data under micro-program control. The input data signals from the ZSHFOPand ZEIS switches 714-28 and 714-22 can be viewed as being concatenated to form a single double word input.
The shifter 714-24 provides a 36-bit output shifted in accordance with the shift count. The ZS~IFOP switch 714-28 is controlled by the microinstruction word while the shift count is established by the sequence control constant field of the microinstruction word which is appropriately selected via the auxiliary arithmetic control unit 722.
For the purposes of the present invention, the ALU 714-20 and the shifter 714-24 may be considered conventional in design.
The scratchpad memory 714-30 provides a working space for storing various data reauired for the execution of certain instructions as well as various constants and descriptor values. For example, octal locations 10-15 are used to store an edit instruction table value required for carrying out edit operations. Wxiting into the scra-tchpad memory 714-30 involves first loading the RSPB buffer register 714-32 with input data applied via the Z~ESB
switch 714-38. During a next cycle, the contents of the register ~5~35 714-32 are wr~tten intt~ location ~pecified by the ~ign~ls appli~d to ~ ~RSPA 0-6 lines by the AACU unit 722. Wrlting ta3ce~ placa when bit 22 of the m~croinstruction word (~SP fleld~ orc:sd to a binary ONE.
R~ co~ce~ oth~r ~witches, as mentioned, the re3ult8 produc~d by th~ ~lt 714 sre provided via the ZAEU
Rwitch 714-26, th~ BSPDI BWitCh 714-34, the ZRE:SA switch 714-36 and tho 2RES13 sw$tch Imder microprogr~m control.
The Z~U an~ ZSPDI ~wl~hQs p3~vide ~ irs~ level o f selection to th~ 2~U:SA ~d Z~ESB ~witches ~hich provide a last levol of ~ ct~o~. S~ nce both the ~RESA and ZRESB
~witch~ ha~ ido~tl~l lnput ~ourca~, they can provide th~ ~2m~ output d~ta.
Op~2a~ fso~ the decimal unit 730 are received via the ZDO 00-35 lin~s ~nd stored in ~elected RTRL 0-3 registers 714-12 ~nd R~ gist~r~ 714-10 as are describeà supra.
~ong operands ~re 3to~d in scratchpad m~nory 714-30. ll~e reRultant ope~ond i8 ss~d through the 2~Æ5A switch 714- 36 into the RC~0 regi~tQr 720-10 o~ character unit 720 and 20 to the daclm~l unlt 730 via the ~C~U 0-35 lirle.

~42 Referring ~o Plgu~ 3, tlle d~cimal unit 730 i~
operatlva under fl~ar~ control processing of decim~l numeric inRtruction~ and xacelves d~ta word~ from cache 750 5 made up o~ 4-bit cbar~ctor~ or 9-bit EBCDI~ or ASCII
character~. ~he da~ca wo~ may contai~ a trailing sign or a leadlng 81gn which fflay be part of an overpunched character and will al~o cont~in an ~xponent if ~he data word i~ a part of a flo~ting po~t op~rand.
~ha dec~mal ~it 730 ~trip~ the sign and/or exponent from the data word, co~ se~ the d~ta words from 36-bit words to 32-bit words, pac:lcs both the 4-bit and 9-bit dec~mal diglts into d~ta words made up of 4-bit decimal digits, and tr2ns~nrs th~ xe~ulting 32-bit data words to thc exocutlon unit 714 gor proce6sing a~ defined by the instrùc~ion.
The most signi~ic~nt and least qignificant words of tho opor~nd recei~ad ~rom cache 750 may oontain information which is not a p~st o~ ~h~ operand. ThiB rewrite information iq stored in registers dnd added to the most significan~
and least signi~icant word~ of the operand if required during the store oper~t$~n.
The decimal unit 730 processe~ operands made up of decimal d$gits either ~8 short operandq or long operands.
25 Short operands ars 1~ decimal digits long or less. Long oper~nds Ar~ from 16 to 64 decimal digits long. Operands having more than ~4 declmal digit3 are not processed in the declmal unit 730 but are procassed by the firmware.
Short oper~nd~ co~pr~ing 1 or 2 data words are t~ans -ferred to temporary r2g~ster-R RTRL 0-3 714-12 and RTRH 4-7 714-10 in tha execution unit 714. ~ong operands comprising from 3 to 8 words sre tr~nsferred to the scratchp~d memory 714-30 in the execution unlt 714.

~51:35~

l~c~mal numeric in~tru~tion~ include an instruction word dRfin~ ng ths ~r~ ic operatlon to be perfonned, a descrlptor 1 word del~lnl~g the characteristics of an opes~d 1, a de~criptor 2 word deflning the characteristics 5 of an op~r~s~d 2 ~nd 4 descriptor 3 word defining the ch~r~ct~ristlc~ of ~ ~ultant operand 3. Some irlstructions use de-crlpts~r 2 ts~ the characteristics o~ both operan~ 2 DS~ op~r~d 3. q31a ins~uction and d~c;ciptor ~orm~t~ ~re ~hown in ~i~ura 5.
Thc docim~ nit 730 under firn~are ~ntrol rPceives oper~nds 1 ~nd 2 ~rom cac}~ 750, aligns them and transfers the~ to the oxecut~o~ un~t 714. Both operands ~re checked for an illegal sign or illegal digits . The res~l tant op~rand 3 ia t~an~f~rr~d ~rom ~he ex~cution u~it 714 to the decimal unlt 730 where it i~ unpacked to 36-blt data words from 32-bit dst~ words, ASCII or.EBCDIC zone characters - are added for 9-bi~- wordx. Exponent characters and signs arQ add~d 1~ requlr~d. Operand 2 or operand 3 rewrlte $nfo~atlon proviously stored msy be added. The oparand 18 checke~ ~or zero/overflow conditions, is rounded or trunc~tad ~ raquir~d and stored back in cache 750.
Descriptors de~ining the operandQ are stored in the RSI~ regi~t~r ~not ~hown in the drawing~) of the control loglc unlt 704-1. The RSIR bit positions 21 ~hrough 35 corr~ponding to the b$t positions o~ the descriptors OL
E~igure 5, are transfesr~ to and stored in registers in th~ dec~mal unit 730. Th~ RSIR bit positions 17-20 are transferred to the d~cim~l unit as signals ASFA 33-36 which Are also stored in a register in the decimal unit 30 7 30 .

~s~

As shown in Figure 5, the descri~tor fields are defined as follows:
ASFA 33 is the least significant bit of the address of the most significant word of the operand indicating an odd or even word address.
ASFA 34-36 points to the digit position within the mast significant ~ord of the high order character of the operand.
RSIR 21 indicates an operand of 4-bit characters if a ONE or 9-bit characters if a ZERO.
RSIR 22-23 defines the operand type and sign position.
00 Leading sign floating point or over-punched sign leading.
01 Leading sign scaled.
10 Trailing sign scaled.
ll No sign scaled or overpunched sign trailing.
RSIR 24-29 indicates the scale factor, i.e., the position of the decimal point. A negative number moves the decimal point to left of the least significant digit. A positive number moved the decimal oint to the right of the least significant digit.
RSIR 30-35 indicates the number of characters in the operand. Characters include decimal digits, sign characters and exponents.
The firmware controls the decimal unit with the signals RCSR 88-89, 94-97. The signals are outputs from the execution control store 701-4.

~5~5~

~ ~LS

TAB~E 1 __ RCSR Sig3~als ~cription Logic N~ of Fi rmware 88, 89, 94, 95, 96, 97 Controlled rYPE F CI.X, 2~M, MPYREG Signals S 1 0 0 0 O O Set EMYDV if DUCMD-200 FPOPll:~, oth~rwise NUL~
0 0 0 0 1 Sel~ct PESULT ~ DUCMD-201 ~RO i ndicator 1 10 1 0 0 0 1 0 S~l~ct OPl~ZERO, DUCMD-202 OP2~ZERO i~d~c~tors 0 0 0 1 1 I.oad STC ~ASX in~o DUCMD 203 1 O O 1 0 0 &lect DU OVERFI,OW DUC~D-204 u~d TRUNU~TION
indl c~tors 0 0 1 0 1 Rgl3et ZEh~/OVER- DUCMD-205 FLOW CEIECK lo~7i c 1 . O O 1 1 0 5et FC~N if FPOPlD DUCMD-206 20 1 0 0 1 1 1 Unused 5~

~ .
.

RSCR ESCRIPTION ~OGIC NAME
88,8~9~,95,96,9.7 TYPE F DU~MD
1 1O O O O Set FMVN if FP0PlD, DUC.~D-300 otherwi~ NULL
1 1 0 0 0 1 R~d OP~AND through DU DUC~D-301 1 1 0 0 1 0 . ~orc~ Lo~d Complete DUCMD-302 Statu~
1 1 0 0 1 1 Stor~ Ope~nd Thru DU DUCMD-303 10 1 1 0 1 0 0 Cbec~ ZERO/OVE~FLOW DUCM~-304 1 1 0 1 0 1 ~ran#fer D~t~ from RCHO -DUCMD-305 to RPK
1 1 0 1 1 0 ~oad Rewrlt~ D~ta DUCMDo306 1 1 0 1 1 1 Load th0 DU Sign DUCMD-307 1~ Reg~tsr (RSGN) 1 1 1 0 0 0 Load the DU ~xpo~ent DUCMD-308 Regl~ter (RE%P) 1 1 1 0 0 1 Put the Rounding Con- DUCMD-309 . stant into RD~D
20 1 1 1 0 1 0 Put Operand ~ding DUCMD 310 Z~ro Count i~to ~D0D
1 1 1 0 1 1 Put Operand Word Count W CMD-311 Into RD~D
1 1 1 1 0 0 Unu~ed 25 1 1 1 1 0 1 Select Descriptor Vector DUC~D-313 Indic~tors 1 1 1 1 1 0 Select Store Op Vector . DUCl~Do314 Indic~tors 1 1 1 1 1 1 Select ~ong Op Vector DUCMD-315 Indicators Note that tbe ~SCR bit poRition~ 88 and 89, the TY~E
F field, ~e~lne t~ ald~ identi~ied by RSCR bit positions ~4-97. If th- TYPE F ~leld contains a "10" then m~croword fields CLX, ~ nd MPY~lEG are elacted. If the TYPE F
f~eld contain~ n mlcroword field DUCMD i5 ~elected.

s~
æ~ 4 DUCMD 200 ~et~ the F~lYDV flag durinq a multiply or divi~e docl~al lnstruction.
DUCMD ~01 s~ ct~ .~o ADsæ conditional branch.
DUC~ID 202 scl~ct~ ~o R~LT~D condlt~ on31 branch indic~ r i opor~nd 1 equal~ zero ~nd ~ale~c~ ~ RREQRD cond~tlonal br~ch indlc~tor if operu~d 2 equ~ls zero.
DUCMD 203 trsn3~a~ the RCH13 30-35 outp~t signal~
STC mas~c in~ he RDOD register 7 30- ~ 54 .
DUCMD 204 ~elocts the RRLTRD conditional branch indic~tor ~or an overfïow and the RREQRD
condit~onnl branch indic~tor ~or a trYncatlon oper~tion.
DUCMD 205 reJ~ts th~ ~C~D ~d FDOFL flags.
DUC~ID 206 ~at~ PCMPN ~lag if the FPOPlD flag is at logIca~ ONE.
DUCMO 300 ~t~ ths FMV fl~y if the FPOPlD fla~ is at loglcal ONE.
DUC~ID 301. st~t~ operand lo~d oper~tion in the docim~l unlt 730.
DUCMD 302 forc~s compl~tion of the load operation by ~etting the FLDCOMPL and the FRDPl ~lag~ .
DUCMD 303 starts the store result through the decim~ll unit 130 by setting the FOPSTR
and FPlSDRN ~lags.
DUCMD 304 ~t~ tho FCZO flag for R check zero/oYer-flow o~ word ~tored in t~he RCHO
regl~ter 720-10.
DUCMD 305 . set~ the FCZO ~nd FRPK flags.
DUCMD 306 set~ the FLD~ flag and selects the RREQRD eol~dition br~nch indicator for a trun catlon oper~ti on .
DUC~D 307 conditions the loading of the 5ign r~giY~r RSGN 730 -134 .

l~S~S~
_. .
~ 4~
~ . .
DUCMD 30 ~ cond$tiorls the loading o f the exponent reg~ 8~r R~XP 730 -138. ~lso oondit$0n5 the loa~g ~ the RSF3 crlle ~a~:tor raglst~r o~ ~egi3t~-r b~nk 730-4 du~ g a floating polnt FPOP3 cycle.
DUCMD 309 control~ th~ lo~ding of tha round~ng tant ~tor0d in Sh~ ZP~t switch 730 150 into ~o p~oper chzlractar po.~$tion of ~che RDOD r~gi~r 730-154 and sets the F~CMD
fl~g.
DUCMD 310 control~ the loading of the oper nd le~dinq z~ro count into the ~DOD register 7~0-154 .
DUCMD 311 control~ t~e lo~ding of the operand word co1mt lnto tl e RDOD rsglster 730-154 .
DUCMD 312 unu~d.
DUC~ID 313 ~elQcts ~he descriptor 1 vector and de3crlptor 2 vec:tor indicators and sets th~ FDVCl ~lag.
20 DUC~SD 314 re~t3 ~ FC~D ~lag and selects the store tor iAd~c~tor~ .
DUCMD 315 select~ ~he long input vectDr indicators.

The Decimal Uni~ 730 ro~ponds to the fin~are requests with the PX V~TR 0-3 si0~al~ indicated below.

VECTOR. ~ DATA
, PK- VCT~
0 l 2 3 , IYP - LENGTI~
O O O O Short Oper~nd and 4-bi t data 30 o 1 0 0 Short Operas~d and 9-bi t data 0 0 0 Short Opers~l and ( 4 or 9 bit data) and overpunch~d 8ign 1 1 0 0 ~ong Ope~nd -5~

TABLE 2 - Continued VECTOR BRANC~ ~ATA

PK-VCTR

0 0 0 0 Execute Descri~tor 2 vector 0 1 0 0 Descriptor 1 = floating point 1 0 0 0 Descriptor 1 = overpunched leading sign, scaled 1 1 0 0 Descriptor 1 = overpunched trailing sign, scaled 0 0 0 0 Descriptor 2 ~ floating point or overpunched sign 0 1 0 0 Descriptor 2 - flcating point 1 0 0 0 Descriptor 2 = overpunched leading sign, scaled 15 1 1 0 0 Descriptor 2 - overpunched trailing sign, scaled STORE VECTOR
0 0 0 0 Check for RESULT=ZERO, OUERFLOW
0 1 0 0 Floating point result - Check for RESULT=0, Overflow 1 0 0 0 Overpunched leading sign output - check for RESULT=0, Overflow 1 1 0 0 Overpunched trailing sign output - Check for RESULT=0, Overflow LONG - INPUT
0 0 0 0 Both operands scaled and adjusted length descriptor 1 5~3 and adjusted length descriptor 2 ~63 and overpunched sign 0 1 0 0 Both operands scaled and adjusted length descriptor 1~63 and adjusted length descriptor 2 ~63 and overpunched sign 1 0 0 0 Both operands scaled and adjusted length descriptor 1 ~63 or adjusted length descriptor 1 1 0 0 Execuke descriptor 1 and descriptor 2 vectors 5~

TABLE 2 - Continued VECTOR B~ANC~ DATA
PREDICTED NUMBER OF CYCLES OF DELAY FOR PROCESSING
DESCRIPTOR I or DESCRIPTOR 2 OPERANDS

OF OF

The following Boolean expressions show the firmware selection of the vector branch data: `
[lPKVCTR = FDUACT (DUC~ 315 ~ DUCMD 313 ' FDCVl + FRDPl : r (DUCMD 313 DUCMD 314 DUCMD 315)) [2PKVCTR = FDUACT (DUCMD 314 + DUCMD 315 ~ DUCMD 301 +
DUCMD 313 ' FRDPl) [4PKVCTR = FDUACT (DUCMD 313 t DUCMD 314 + DUCMD 315) [PKVCTR = 1 selects the type length vector which indicates to the firmware whether the operand is a short or long operand, 4 bit characters or 9 bit characters and if a short operand whether there is an overpunched sign in the descriptor 1 or descriptor 2 operands.
[PKVCTR=2 or 3 selects for short operands the numher of cycles of delay needed after the first read command is sent to cache 750 to the first data word being sent to the execution unit 714. This prediction simplifies the firm-ware processing of short operandsO
[PKVCR = 4 selects the descriptor 1 vector which defines descriptor 1 as a floating point operand, an overpunched leading or trailing sign scaled operand or indicates to the firmware to execute the descriptor 2 ~ec tor.

5C~5~
`5/

[PKVCTR - 5 selec~ aescrip~or 2 vector which defina~
desc~iptor 2 as a fl~ating point or sc:~led operand with ov~ ched leading or trailing .'BL~a .
S [PRVCTR = 6 selec1~ e store vector whi :h indicates to the fi~are to speciic ~ecic fos re3~1~g oper~d equal to zero.
[P~CVCTR = 7 select~ ~e lor g-input vector and indicates to t~e fir~Tare the comparison }~etween the operand lengths and S 3 for scaled operands .
T~e vec:tor also indicates to the firrware to execut~ the descriptor 1 and descriptor 2 ~ctors.

me decimal unit 730 supplies a number of conditional 15 branch indicators to ~e e~ecute address and branch circuits logic 701-1.

CONDITION~ BRY~Nt:EI INDICA$0RS
~ .
Name Sou~
-S TART--WRT RRI.~rRD
2 0 SEND-DATA R~E:QRD
OPl=ZERO R~TR9 OVERFLOW RRLTRD
T~UNCATION RR~QRD
2 5 RESUL~ ZEPO ~DS Z
DATA-AVA ADS Z
CR-STR-VECT ZAMO

The RRLTRD sigslal is generat~d:
1. during a DUCMD 202 command when the FOPlZ flag 30 is set indicating that operand 1 is zero.
- 2. during a DUC:~lD 204 ~omraand when the F~OEL flag is set indicat3ng that there was ~n operand overflow.
3. during a start write operation to indicate to ~he firmware to sent wri~e comn~ands to cache 750.

s~s~

~,~ s-~

~ho P~EQ~ al 1~ ge~rated:
1. durlng a ~UC~D 2~q or DUCMD 306 comm~nd with the truncatlon ~gnal at log~ cal 1 lndic~ting that lea~t ifieant digit~ of an op0raAd will be 108t.
2. dur~ng ~ DU~ 202 command s~hç:n the ~OP2Z flag 80t indicating o~Dr~ 2 is zero.
3 . dus~ ng ~ Clàt~ operation to indicate to the fir~r re to trans~s data to the decimal unit 730 from the ex~cut~on ~i~ ~14.
10 . 5h~ ADSZ ~ sanerated:
1. dur~ng a DUCND 201 command when the operand is e~ual to zero.
2. wh~n data i8 not a~rail~le excep~ during a DUCMD
2 01 con~nd.
. 5~ ZAMO 8ign~1 13 g~nerated to indicate a check 6tore voctor funct~on ~uch as floa'cing point, overp~ched charact~r, ov~rflow, r~sult ~ O operand.
$1~a conditional br~c~ indicators are called for by the firs~ and r~ults in an exl3cution control store 20 701-2 branch.

._ ~

5~

~ s~3 Descxiption o~ deci~al unit st~tus flag~ including the bool~an 8xpr~8~0n3 for ~etting and resett~ng the flag~
are:
F3DESC Set for th~ processing of oparand 3 which is do~lnod by either descsiptor 2 or des-c~ipto~ 3. The boolean expression is:
F3DESC S~ FPOP~RDESCO-RDESC1) F3D~SC ~SET: (FPOA) FALT Sat durl~g the store operation on alterna~e cycl~. The dec~al unit prepares a word for tho RDOD register 730-154 on one cycle and tSans~ers the word to the Execution Unit 714 on the next cycle. FALT se~
~n~bl~s the ~toring of a word in the RDOD
~ogi~t~r. The boole~n expression i5:
FA~T SET~ UCMD 303 ~ FOPSTR~ FALT FPOAl FA~T R~SET: (FOPSTR-FALT + FPOA) FCMPN Se~ for ~ DUCMD 206 firmware command for a compdra nu~eric inatruction. The boolea~
expre~sion is:.
FCMP~ S~T: (FPOPlD-DUCMD 206) FCM2N ~S~T: (FPOA~
FCPCO Set wh~n loading or 3toring 9-bit data word3 from odd addre~se~ in Cache 7~0. The boole~n ~xpre~ion i~:
FCPCO S~T: ~(ZCPAO (FDUACT~FRDPl + SFOP2LD
+ FLDCOMPL (DUCMD 303 + FOPSTR)) + FCPCO~FOPlLD~SFOP2LD
+ FOP2~D)~(FDID + FUFD) + FCPCO
30 ~ UC~D 303 + FOPSTR)~[$RDOD) ~FPOA) ~.3 ~S~

FCPCO RESET: (ZCPA0~(FDUACT FRDPl SFOP2LD + FLDCOMPL
DUCMD 303 ~ FOPSTR)) ~ FCPCO
(FOPlLD-SFOP2LD t FOP2LD) (FDID + FDFD) ~ FCPCO
(DUCMD303 ~ FoPSTR).[$RDoD
~ FPOA) FCRPl Set during an operand load operation when one of the o~erands is long. This flag lets the second load DU operand command (DUCMD 301) start a load process. A long operand causes the decimal unit to cancel the first load DU
operand command (DUCMD 301) to enable the firmware to get set up to process a long operand. The firmware always assumes a short operand operation. The boolean expression is:
FCRPl SET: ((DUCMD 301 FRDPl-(DlEQOVP
+ D2EQOVP + LONG))-FPOA) FCRPl RESET: (FPOA) FCRD Set by a DUCMD 305 firmware command or an FCZO flag on for a check zero/overflow operation and reset by a DUCMD 205 or 314 command. Remains set for the entire operation processing. The boolean expression is:
FCRD SET: ((DUCMD 305 + FCZ0)-FPOA) FCRD RESET: (DUCMD 314 ~ DUCMD 205 t FPOA) FCZ0 Set by a DUCMD 304 or 305 firmware command for a check zero/overflow of the word stored in the RCHO register 720-10. The booleah expression is:

~5~5~

FCZ0 SET: ((DUCMD 305 ~ DUC~ 304))-FPOA) FCZ0 RESET: (SFCZ0 + FPOA) FDADIS Set for 9-bit decimal digit operand loads on alternate cycles to allow two 4 digit words to be received from cache 750 and stored in the RDOD reaister 730-154 as one 8 digit word. The boolean expression is:
FDADIS SET: ((ZTNSA0-FRDP2 ~ ZTNSB0 FRDP2)-DATA-AV-FPOA-SFOP2LD) FDADIS RESET: (SFDADIS-(~$RDI-PC + SFDFD
+ FDFDRFDFD) ~ SFOP2LD) FDATA-AV Is set to load the RDOD register 730-154 by controlling the strobe signal [$RDODA. The boolean expression is:
FDATA-AV SET: (DATA-AV-FPOA) FDATA-AV RESET: (SFDATA-AV 4 FPOA) FDFD Is set during a load operation to indicate that the complete operand has been received from cache 750 by the decimal unit 730. The boolean expression is:
FDFD SET: (DFCQ FDID (RFDFD)-FPOA-(FOPlLD
SFOP2LD ~ FOP2LD)) FDFD RESET: (FPOA ~ DFCO-FDID-DTECO
~[$RDODA t DFCO~FDID.FDTED
+ DTECo-[$RDoDA-FDFD) FDID Set when operand data is loaded into the RDID registers 730-158. The boolean expression is:
FDID SET: ([$RDI-PC-FLDRXWR.FRDP1) FDID RESET: (SFDID) ~5;~5~

~56-FDOFL Set when an operand overflo~J is detected during a check zero/overflow operation and reset by a DUCMD 205. The boolean exPression is:
FDOFL SET: ((DUCMD 305 + FCZO) DOFL-FPOA) FDOFL RESET: (DUCMD 205 ~ FPOA) FDTED Set when all of the decimal digits of the operand were sent to the execution unit 714 but not all of the operand information has been received by the decimal unit; exponent or sign information for example. The boolean expression is:
FDTED SET: (DTECo.~$RDOnA~(RFDFD).FPOA
~(FOPlLD~SFOP2LD + FOP2~D)) FDTED RESET: (FRDFD) FDUACT Set during an FPOP control logic unit 704-1 cycle to indicate a decimal unit 730 operation. The boolean expression is:
FDUACT SET: (FPOP) FDUACT RESET: (FPQA) FDVC1 Is set when the firm~lare sends a DUCMD 313 for descriptor 1 information so that descriptor 2 information is sent on the next DUCMD 313. The boQlean expression is:
FDVC1 SET: (DUCMD 313~FPOA) FDVC1 RESET: (FPOA) FDZERO Is set if the operand check with the check zero/overflow commands DUCMD 304 or 305 equal to zero. The boolean exPression is:
FDZERO SET: (~DUCMD 305 + FCZO)-DZERO-FPOA) FDZERO RESET: (FPOA ~ (DUCMD 305 ~ FCZO) DZERO~FCRD) lqoD54 P~D~ t wh~n the ~lrs word o~ the operand ~r~ c~cho 750 is lo~ded into ~h~ decLmal ~;: unlt. Th~ boole~n QXpr~s ion i6:
F~D~ SE~: ~ (FDID~ tFOPlLD + ~OP2LD)) ~ ~
PPDI RES~T: ~POP2LD + EPOA) .. ~ P~DO ~ J~t whe~ the ~ir~ word of th~ operand . - ~ ~to~ the RDOD registar 730-154 p~lo~ ~o b~ing tran~erred to the execution s 10 unlt 714. ~he bool0Rn ~xpr~8~ion is:
FFDO SE~: ( ( [$RD0DA & (POPlLD ~ FOP2LD) l FFDO R~BE$: (SFOP2~ ~ FPOA) n~ FFOSD Is sot when the flr~t data word to be ~oEod ln cache 750 i8 loaded into the RDOD rogi~ter 730-154. The ~oolean ! eXP.rn~10~
FFOS~ SET: ( (POPSTR + DUCMD 303) [SRDODA
~ F~) ~OSD ~ES~ POA) PILI,DIG I~ ~Ot wh~n an ~11e~a1 digit Or i11ega1 ~8 ~CeiVed bY the deCima1 Unit 730.
I1: O-~gJ~16 ~ :EaU1t tO the SY~tem and iS
r~8-~ 0~ CYC1e 1atOr bY the PLDGR f1ag.
The ~01ean eXPre88iOn i8 F~ G SET~ S~DODA. (FOP1LD I FOP2LD) D2IDEQID ~ ILLEG~LLENG1~H
(SFOP1LD + FCZO) ) (~
. . ~o FILI.DIG RESEr: (FLDGR ~ FPOA) _ .

~5~5 ~ .~g FLI~COMPL I ~ s~t wh~n both operands have been t~n~s~xed to the axecution unit 714.
The ~oolo~m expres3ion 18:
FS.I)CO~L SET: ~ ( (FO~lI.D~PMVN + FOP2LD
~ (DFCO FDID . D~ECO
[ S~l)onA + DFCO FDID . FDTED
DTECO [ $ }~I)ODA FDFD ) ~UC~D 3 02 ) FPOA) FI.DCO~lPL ~%ESE~: ~FPOA) Fl.DGR i~ ~ot at the same time as the FILLDIG
flt~ t 1. ~., when ~n illegal digit or illegal length is r~ceived in the decL~al un~t 730. It resst~ the FI~LDIG after one cycle. ~rh~ bool~an ~xpression is:
F~ SET~ SRDODA- (FOPlLD + FOP2LD) .D~IDEQID + II.LEGA~LENGTH
~ ~SFOPlL~ + FCZO) ) ~FPOA) FLDG~ RESET: tFPOA) FLDREWR I~ sQt ~Ylom the firmwdre by a DUC:~!D 306 load rewrlte d~ta signal to start the ~e~uence fo~ storing the eirst or last words def ined by desc~iptor 3 in the REWR 0-3 register bank 730-177. ~he boolean expres~ion i~:
FL~EWR SET: (DUCMD 306) ~LDRSWR ~ESE~ IR~D~
F~D~EWR~ t one cycl~ after the FLDREWR flag is ~et to ~t~obe the fir~-t or last word into the REWR2 or ~EWR3 regtster resp~ctively of the R~WR 0-3 register 730-17~ during a d~crlptor 2 ~tore operation. The boolean expre~sion i.~:
F~DR~WR~ SET: (FLDREWR) FLDREW~H RESET: (FLDREWR) ~ S~5~

_2~
~P~ ~

FMSDRGT~ I~ 8~t during a store operation on ~ DUCMD
303 i~$n~w~re co~mand i~ word count in the R~C ro~lst~r i8 greater th~n o~ equal to th~ d count ir~ t~o RWPC reg~ ~ter at the tis~s tbe DUCMD 303 ~ 5 used. The boolean exp~o~lon 18:
FMSD~;T~ S f3T: ( DMSDR~;TE DUCMD 3 0 3 ~ ~ FALT
~;~) ~MSD}~GT~S RESET: ~FPOA) FMSDRN SetA on the Dl~c~sra 3 03 f irmware con~n~nd f or long ope~nd store if the word count in reqlst~r 1~ negative ini~ially.
~h~ ~ool~an expr~ssion is:
P~SD~N S~Ts tDUCMD 303-RRWCO-~) F~SD~W RESE~: ~ FPOA ) FMSEQ Set~ dur~llg a long operand ~tore sequence whsn the word count in the RRWC register oqual~ the word count ln the RWPC regi~ter.
Thc ~oloan expre~sion is:
- F~ a ~ T: (DMSEQ- (PSW~T~DMSDRG~E * FSWRT
~ (ZTNSAO + ZTNSAO-FCPCO) ) - . (DUCMD 303 + FOPSTR) ~FALT
( DllCMD 3 0 3 RRWC O + FMSD~N ) ~;~) FMSEQ RESET: ( FPOA ) FMVN I~ set for a move numeric instruction.
The ~oolean expre~sion is:
FMVN SET: ( DUCMD 3 0 0 ~ FPOP lD ) 3 F~(JN RP;SET: ~ FPOA) . ~ 5~35~

~ 60 FMYDV Ia 813t i~C)~ multlply and divide instructions.
Thls ~l~g 8Uppre~88e8 the scale f actox a~lyr~nt and ri~Oht ~ustif les the operand~
o~ la lon~l operation. . The boolean ~xpr~ on 1~:
F~YDt7 9~ DUCMD 2 0 û o FPOP lD ) F.'~lYDY R~:SET: IFl?OA) FOPlLD I3 oot ~or the oper~nd one lo~d oper~tion.
~he ~ool~ expre~a~ on is:
FOPl~ S~3T: (DUCMD 301 FR~Pl.FPOA- (DlEQoVP
D l E~VP~ FCRP 1 ) ) . POPlLI~ 55ET: (FPOA + FOPlLD-DFCO DrECO
.F1~ID- [SR~DA ~ FOPlLD.DFCO
FDID FDTED ~ FOP lLD . DTECo [ $ ~DODA FDFD ) FOPlZ Is 3et i~ operand 1 equ~ls zero. The boole~ expressio~ i8:
FOPlZ 8ET: ~lS~DODA-FOP1LD-DZIDEQZ-FPOA) FOP1~ R~8ET: ~FPOA~
20 FOPSTR Is ~t by the DUC~D 30~ s~ore oper~nd through decimal unit 730 firmware command.
~ha keol~n expressio~
FOPS~R S~T: (DUCMD 303 FOPST~ RESET: ~FPOA) 25 FOP2F Is set ~or an operand 2 load and the f irst data word is rece$ved in the RDID register 730-155. The boolean expression i8:
FOP2F SET: ~FD~D-FOP2LD~
FOP2F RESET: ~FPOA ~ DFCO - FDID) FOP2LD 13 . ~st or the oper~nd 2 lo~d operation .
$he boolean expression i~:

~5~35~
., .
~ 6l . ` POP2L.D SET: ( (FoPiLD~ (DUCMD 301 + P~P2) (DFCO-FDID-DTECO
[S~DO~ I DFCO-FDI"-.FDT~D
+ DTECO- [$RDODA-FDFD) + E~PI~D
J s .~.DUCMD 301.FRDPl).~) FOP21D ~e:SET: (FPOA + FOP2~D- (DFCO-FDID
~TECO- [S~DODA + DFCO-FDID
FDTED ~ DT CO- ~SRDOD~-FDPD) ) FOP2S Is ~t o~ an operand 2 load operation when :1 10 t:~6 s~co~ad word i5 ~tc~red in the RDID
r ~ist~ 730-158. The boolean expr~ssion . FOP2S SE~: (FOR2F-FDID-~) ,~ FOP~S ~d3SET: (FPO~
15 FOP2Z I~ ~t lf operand 2 18 eql~al to z~ro. The - bool~ ~xp~es~ion i3:
~OP 2 2 Sg~ S RDODA - FOP 2 LD - ~ ~ I D~QZ - ~) , FOP2Z RE~El`: (FPOA) FPF~ I 8 sot i~ operand 1 or operand 2 are speci-fi~d a~ ~loating point. The boolean exprosslon is:
FPF~ 8~s ( (DlEQFLT ~ D2EQFLP) FOPlLD PPOA) ) FPFI. RES~:T: (PPOA) PRC~ set by B DUCMD 3 0 9 f irmware command to 25 . re~d ~he rounding constant into the RDOD
. regi~ter 730-154. The boolean expression is:
P~C~D SET: ( DUCMD 3 0 9 ~P~) FRC~D ~ESET: 5FPOA) 30 FRDIDH Is ~ot to indic~te that the re~uested infor-mation i~ not stored in cAche 750 and cache mu3t re~uost it o~ backing store. When the data i8 ~sceived in cache and ~ent to the ~S~5~

~ 2 dscin~l unit 730, the FRDID~ flag gate~
th~ r~o~y 8ignal to s~robe the d~ta ~nto th~ ~DI~ regi~ter 730-158. The boolean ~xpr~s6ion i8:
. F~D~D~ ~ET: ~SRDI-PC) FRD~ %~SET: (F~DIDH) FRDPl I~ ~t by DUC~D 301 or DUCMD 302 firmware co~and~ to indi~te that the command for read~ng the first operand has been i~sued to th~ d~cimal unit 730. ~he boolesn oxpre~lon i8:
FRDPl SE~: ((DUCMD 301-(DlEQOVP D2EQOVP
+ FCRPl) ~ DUCMD 302) ~) F~DPl R~SE~ POA) ~RDP2 Set by ~ DUCMD 301 firmware command when ............. ........ ` the ~DPl ~lag i~ set to indicate that the cGmm~nd ~or reading the second operand has bs~n ~uod to the d~cimal unit 73C. The bool~an expre~s~on is:
F~DP2 S~T: (DUCMD 391 FRDPlFPO~) F~P2 RES~Ts (FPOA) FREWR Is sat by the FLD~EWR~ flag in the cycle followlng the setting of the FLDREWRH flag.
Th~ ~lag ~8 used to force the rewrite data to bo ro~d from REWR2 and REWR3 during the oper~nd ~to~e prooa~s. The boolean expre~lon i8:
F~EWR S~T: (FLDREWR~FPOA) FRE'AR RESET: (FPOA) FREWR2 I3 ~et ~y the FREWR and FLDREWRH fla~s both on. It ~auses the REWR3 regi~ter to be ~S~5~

-~~ 6 3 u~od to provide rewrite data for tha last wor~ o~ ope~a~d 3. The boolean express1on i8:
F~EWR2 SET: (FLDREW~H-FREWR-~POA) FR~W~2 ~ES~T: (F~OA) F3D~S~ t ~or the de3crlptor 3 oparation. The bool~n ~xpre~sion i~:
P3D~C 8~T: (FPOP-RDESCO-RDESCI) F3DE8C ~E5ET: ~FPOA) 10 FPOP3D I~ set ~or the cycle following FPOP3 cycle o~ tha contsol logic unit 704-1. The booloan expression ~s:
FPOP3D S~T. (FPOP-RDE5CO RDES~r) . FPOP3D RESET: (~POA + FPOP3D~(DUC~D 305 ~) FPT~ Is ~at ~or the co~dition that the ldjusted - length, length plus soale factor difference is gse~ter than 63 characters. The ~oolean 8xpr~a~ion ls:
FPTL SE~ NSLTE63-FOPlLD-FPOA) FPTL ~SSET: - (YPOA) FRPX I~ ~et on a DUCMD 305 transfer data from RCHQ to RPX firmware commsnd and is used for tha short operAtion ~tore. The boolean expression is:
FRPX SET: (DUC~D 305-DlEQFLP-FPOA) FRP~ RESET: ~FPOA + DUCMD 205) FSND Is set when the SEND DATA bit is forced to a ONE . SEND DATA indicates to the f irmw3re to load ~ new woxd into the RCHO register 72û-10 during a long operand store. The FSND ~l~g qtrobe3 the previou~ word stored in the RCltO regi~tes into the RPK regigter 730-162. The boolean expre~sion is:

~ , s~ ~

~ ~,4 i FSND 5ET: (FALT 5END-DAT~-~POA) FSND RESET: (F~LT~SEND-DATA + FPOA) FSSFD I~ s~t when the s~ale fac~or differon-~
1~ neg~tive. The boo~ean expre~sion is:
S FSSFD SE~ (ASP2-FDUACT~FRDPI) PSS~D ~ESET: (~ FDU~CT-~ + FPOA) FS~RT ~8 ~t when the STRT-W~ ignal to the firm-wa~e ~ forced to ONE. STRT-WRT enable~
the flnmw~re to st~rt issuing write commands to the c~che 750 during the long operand store procedure. FSW~T in~orms the DU
hardw~re control that ~he firmware is i~uing write comm~nd~. Th boole~n express~on i~:
i; FSWRT SET: ~FALT-STRT-w~T (DUCMD 303 + FOPSTR)-~b~) FSWRT RESET: (F~OA) FPOPlD Iq set for the cycle following FPOPl cycle of the control logic unit 704-1. The boolean expression is:
FPOPlD SET: (FPOP- ~DESr O RDESCl ) FPOPlD ~ESET: (SFP~PlD) PTDBO Are set as a 2-bit counte_ ~o count down FTDBl the number of cycles of delay for strobins the oper~nd word into the RDOD register 730-154 for transfer to the execution unit 714. The boole~n expresqion is:
FTD30 SET: (TDBO~DUCMD 301-FPOA) FTDBO RE~ET: ~TD30-DUCM~ 301 +(FOPlLD
+ FOP2LD)-D~C~D 3~I-[5RDI-PC
+ FPOA) ~5~5 ~- 6S
~TD~l S~ ( (TDBl DUCMD 301 ~ FTDBO
~FOPlLD ~ ~OP2LD) DUCMD~0 PC~
Fq~DBl R~S~: (~FI~D~ICMD 301 ~ FTDBl ~ (~OPlLD + FOP2LD) ~DUCMD 3~I
l$~ PC ~ PPOA) FZC~ aot du~ing the load operand procedure wh~n th~l ~lrst non zero char2~c~er i~
d~t~X~d in th~ i~put data. It indicates the ~d o~ the nu~r of leading zeros in the op~rand.
FZCF SET: ( [ ~RDO~A~ (FOPlLD ~ FOP2LD) ~ ~)) ~ZC~ R~SSE$: ~SFOP2LD + FPO~) ) The followl~ a~ oole~n exprecsions f or functions not prov~ou~ly d~crlb~s~s SFCZO 8 (DUCMD 305 ~ W C~D 304) ~
SFDADIS ~ F~ + ~ ~RDP2)-DA~A-AV~FPOA
.~
~0 SFDFD ~ DFCO~FDID~
SPDATA-AV ~ DATA-A~-~
PC ~ EN~BIZ + FTRP + FMT- (~ - (RDIN.EQ.(1-11)) + ~YPE-~MIS~G.EQ.4) + TYPD-(IBUF.EQ.3~) + FMT
((SLPIP~.EQ.l)~FE12 + TYPBD (2)-(MSKD.NEQ.0) + TYPBD (3)-STL) ~ FREQCA-(RM~M.EQ.(8-10)) ~ FRE0DI + FDIDBL
SFDID ~ [SRD~-PC~ R~-~RDP1 DOFL lndi~ates an ove~low condition DZIDEQID - ~ZID4-(2~D5 + ZID6)) + ~ZID8-(ZID9 + ZID10)) ~ tZID12 (ZID13 + ~ID14)) + (ZID16-(ZID17 ZID18)) ~ (ZID20~(ZID21 + ZID 22)) + (ZID24 .(Z~D25 + ZI~26)) ~ (ZID28~(ZID29 ~ ZID30)) ; + (ZID32-(Z D33 ~ ZID34)) I~LEGAL~NGTH ~ ALNDA~ ~ ALND~0 + ALNDAZ ~ ALNDBZ
3s DZE~O ind$cates that the oper~nd word contains all zeros.

~5~Sf~

Decimal Unit - Logic The scale factors for operands 1, 2 and 3 are received in the decimal unit 730 through a 4 position switch ZSFN
730-2 over signal lines RSIR 24-29 from the control logic unit 704-l and are stored in registers RSF0, RSFl, RSF`2 respectively of register bank 730-4. ZADSP 3-11 signal lines apply the scale factor to position 0 of the switch when the scale factor is calculated by the ~irmware. ALNDA
signal lines apply the adjusted length of operands to position 2 of the switch during a floating point operation.
The ~EDC and ZEDC signals are applied to position 3 of the switch to store the number of effective digits during a floating point operation. This is described in greater detail as part of the store operation description.
Control signals [lZSFN and [2~SFN select the switch 730-2 positions. The boolean expresSiQns are:
[lZSFN = ((F3DESC ~ FMVN)-FLDCOMPL-~POP-(DlEQFLP
~ DUCMD 305 ~ FCZ0)) [2ZSFN = ((F3DESC ~ FMVN)-FLDCOMPL-FPOP-DlEQF~P) For non-floating point operands the operand 2 scale factor is selected by the RSF1 position of a ZSFB switch 730-8 and is applied to an input of an ASF adder 730-10 where the operand 2 scale factor is subtracted from the operand 1 scale factor selected by the RSF0 position of a ZSFA switch 730-6. If the operand 1 scale factor is larger than the operand 2 scale factor, then the signals ASF0-9 represent a positive number and bit position ~SF2 is a logical ZERO. If the operand 2 scale factor is larger, then the signals ASF0-9 represent a negative number and bit position ASF2 is a logical ONE.
The length or number of numeric characters for operands l, 2 and 3 is received over signal lines RSIR 30-35 from the control logic unit 704-1 and is stored in registers ~4513~

RLND0, RLNDl and RLND2 respectjvely o~ a register bank 730-12. An ALNDA adder 730-18 and an ALNDB adder 730-20 calculate the number of decimal digits in operands 1 and 2 respectively. This is accomplished by subtxacting the number of non-digit characters in the operand such as sign and exponent from ~he length. The output of a decode logic 730-38 and a decode logic 730-40 is apPlied to adders ALNDA 730-18 and ALNDB 730-20 respectively to adjust the operand 1 and operand 2 lengths.
The sign and decimal tyPe for operands 1, 2 and 3 are received over signal lines RSIR 21-23 from the control logic unit 704-1 and are loaded into registers RTMS0 RTNSl and RTNS2 respectively of register bank 730-32.
A ZTNSA switch 730-36 selects the operand 1 sign and decimal type stored in register RTNS0 and applies it to the decode logic 730-38. A scaled unsigned operand resuIts in a ZERO outPut, a scaled signed operand resuIts in a ONE
output, a floating point operand having 9-bit decimal digits results in a TWO output and a floating point operand having

4-bit decimal digits results in a THREE output from decode logic 730-38 respectively. The output value is subtracted from the operand 1 length in the ALNDA adder 730-18 to give as an output, signals ALNDA 0-6 which indicate the number of decimal digits in operand 1. The number of decimal digits in operand 2 indicated by signals A~NDB 0-6 are calculated in a similar manner.
Signals DBITX and DBITZ at logical ONE indicate that a binary ONE is subtracted from the ALNDA adder 730-18 and the ALNDB adder 730-20 respectively. The boolean expressions are:
DBITX = ~(ZTNSAl-ZTNSA ) + (ZTN~A0.ZTNSAl-ZTNSA2)) DBITZ = ((ZTNSBl-ZTNSB2) ~ (ZTNSB0-ZTNSBl-ZTMSB2)j Signals DlEQFLP and D2EQFLP at logical ONE indicates that a binary TWO is subtracted from the ALNDA adder 730-18 and the ~513~4 . . .

6~ .

ALNDB ~dd~r 730-20 r~pcGtlvaly. The boolean expreesions are DlEQ~I P w (~~ ZTNSA0 ~
D2EQF~ .~. ( ZT!~SB0 ~ ~) )

5 ROPl in~ic:~as ~n o~er ?~h~d ~i~ in~truction .
A ZAI~ND ~wltch 7io-22 ~el~ct~ tbe adjusted length of the opor~d wl~ th~ l~r s~al~ façt,or and applie~ 1:he outpu~
to an A~NS ~daor 730^~4 whlch add~ to it ~e absolute value of the scais ~ctor AS~ 0~ output of the P.SF 730 10 adder.
10 Bi~ poslt$on ASF2 ~Ql~ e operand with the larger scale ~actor. B$t po~itlon ASF2 -at a log~c~l O~E indicates that t2~Q operand 2 ~Icalo ~wt~ i8 larger.
~ he output o~ n ~NADJ ~w~tch 730-26 applie~ the ad~wtad longtl~ to ~ A~: o~unter 73û-60 and an ACPR
15 count~r 730-62. T2~ l~pu~ to the ZLN~DJ ~wit~ 730-26 are de~scslbe~d ~elow.
e oparand 1 ~c81~ factor is larger, then the swit~h ~elsct3 the ~NS 0-9 ~nput signals for operand 1 and the A$NDB lnput slgnal~ ~or operand 2 . I f the oper~nd 2 20 ~cale ~actor $~ r, th~n th~ ~witcA ~elect~ the AL~DA
0-6 input 3i~als for opQrand 1 and the ~NS input ~ignals for operand 2. A floati~sg polnt oper~d or a multiply or divide ln3truotion doe8 not xequire a scale factor align--ment, th~ ora,. t~le ~$NDA 0-6 and AI,.`~DB 0-6 input signal~
25 are selQctad ~or op~rand 1 ~d oper~n.l 2 respectively. The ~LZCl input sigs~ala a2~ ~elected during a floating point store oparand and prov~ds the number o~ leading zeros in the operand .
Control 3ignal~ 41ZLN~DJ and 42ZLNADJ select one of four 30 posltion~ o~ Z~ADJ ~wi~ch 730-26. The boolean expressions ~re 5~5~
... .

~lZI-NAOJ ~' t~F~.FRDPl. (~S~FD ~ FMYDV + DlEQFLP
D2~Q~ AINS2) ~ Fl,DCOMPL (F3DE~SC
lEQFI.P ~ FDOFL~
~2 ZLNAW 8 (FDQ~ ~ + FRDPl . FSSFD) ~-~.~i~ ~ AL~S2.FLDCOMPL
F~COM~ (F3DESC ~ FMVN) .~I~
5~5C1FT~P FDOFI. j If th~ outpu~ o~ th~ ~LND~ adder 730 la, ~he ~I.ND~
ad~r 730-20 and t~a AI~aS add~r 730-24 are all 15 decimal digits or leo~ ~ thl~ lnd~cates ~hat the non floating point dbclmAl ~n~truct~on~ are~ exocuted in the short operand mode.
Thi~ pro-rldb~ ~or i~cre sed system throughput in pxoco~ilng dbcl~l in~tructions ovor the prior art, ~ince mudl of ~e op~and m~lpulatlcln is don~ using logic per-formi ng mu~y o~ tho o~r~nd 5QtUp ~unctions in parallel .
The prior art perfor~d nany of the functions ~erially. The booleul ~xpression ~o~ tho shot operand i~ a~ follow~:
Sho~t ~ t3=-~) (3~-~) (AL~15~ 154 ) (~ + D~EQF~P) 20 Not~ that tho ~cal~ ~acto~ ad; wt~ant i not impl~mented for the ~ult~ply or d~ ino~uc~cion~.
ARNC addl3r 730-60 calculat~ n~er of words to be ts~nsfQrro~ xa~:ut~on unlt 714 for both short and long oparand~. m~ ~l9nal [ONE/A~WCB is applied to the m~nus 25 input to ad~r ~ 730-60 and, when at logical ONE, is sub-tract0d ~rom 'chel ~d~ d l~ngth ZI~tADJ 0-9 ~or a load op~r~tlon. Thi~ w~o~ that if the ~d~usted length as ind~eat~d by ~ha 2~ADJ 0~9 signalA was û-decimsl digits, i.e. the ZT,N~DJ~ l wa3 a ONE, then s~lbtracting ONE would 30 m~lka blt po~itlon A~WC6 a ZE~O and 8 decim31 digits will be load~d ln~o th~ fl~t word, Di~carding bit po~itions ARWC
7-9 lo~ blt po~ on ARWCfi a indicatinq the number of ~5~54~

words for tho ~hort op~rand. A ONE in bit po~ition ARWC6 indic~tQY a ~hort opQrs~d of 2 words ~uld a ZERO in~ica~es a short operand o~ one word. q~e boolean expres3ion for c~ntrol ~ignal [ONEJARC~CB
S tONE/A~ ~ + ~
~i~) + (~ ~ ZLNI~DJ8 .
~ FLl:COMi?~) ) m~ MWC 0-6 output ~ignals indicating the number o f words ir~ ~ operand 18 . a,rail~ble to ~he firn~are when the 10 execution cont~ol 3tor- 701-4 send~ a ~irnware word which is decodad in the d~cima~ unit 730 as a Dt~C2~D 311 "Put Operand Word Count lnto ~DOD" 31ç~al and make~ the word co~t available th~ough a Z~Zt: ~wltch 730~76, position 3 of a ZID swltch ~30-150, po~ition 0 of a ZDOD ~witch 730-152 15 to a RDOD r~gl~te~ 730~154 ~rom which it ls transferr~d to the e~cecution unit 714.
Th8 ACPR dddl~r 730-62 subtract~ the adjusted length in declmal diglt~ decodad by tha ZLNAW ~-9 3ignals from dec~m~L 64. ~e 5~ ity 64 is the maximum number of digits 20 in a~ op~and that i~ proce~sed by the decimal unit 730. rhe re3ultlng output signals ~CPR ~-9 indicate the nu~er o zero digits to the le~t o~ high o~der digit position for a 64 dbcl~al dig~t op~rand~ value is stored in an RLMP
regiqtor 730-102. Bit ~ositions ~LMP 4-6 ~tore a binary code 25 indicJ.tlng the n~r o~ high order positions in the first wosd of the op~rand~ lved by tha decimal unit 730 to be forced to ZERO. 5~ PLMP 4-6 -~ignal ~ are applied to a ZIDMU
shi~tor 730-130. 'rho nu~ber of hlgh osd~r digits to the left of th~ mo~t sign$~icant~ digit poc~itlon to be forc~d to ZERO
30 is indic~tod by th~ nwnbar o~ gUCCg~iVQ signal~ st~rting wlth tl~o ZDMU O ~ a~ which arQ forced to ZERO. The ZIDMU
0-7 aign~l3 Ar~ appllod to a ~ZID lclgic control 730-132.

: ~45-~5 ,~,9 .~, .

m~ OUtF~lt ~i~nals [EZID 0~7 outpu~ ~ignal~ suppress the ZID 3wit~h 730-150 in z~2:~ to tho l~ft positions and enables th~ diglt po~itloT~s O~ ~ ZID switdl 730-150 starting with tho n~st s$g~iflcant dlg~ t po~ition . The portion of the 5 R~P ~g~tox~ 730-102 l~toring the RLMP 0-3 bit positions ha~ tho csp~bllity o~ ~lng incr~n#nted ~or every operand word rec~l~d by ~a d~sG~ unlt 730 by the lC~TUP-RLMPU
sign~ 3~oole~ qua~lon $a tCNTUP~PU ~ ~ (FOPl~D + FOP2LD) [SRDoDA~sFop2BD) 10 Tho boclo~ slon .for the 3ignal ~ONE,/ACPNBB is:
ONE/ACPNBEI ~ Al (~ + Zl~iSA0 + ZTNSA2) ( ~FD.SJACT..~;~) + FLDCOMPL.~
. ~. Z~;~ND~9 ) ) + ~ ZTNS~l ~ ~ ZTNSB0 ~ ZTrlSB2) ~ (F~Pl ~) ) An AT~ add~r 730-30 calculates the ~umber of zeros to the right of the l¢als~t ~ if$c:ant digit of the operand with the largor ~cal~ factor. ~e ZASFB ~wi tch 730-28 selects the ad~u~ted ac~lo gz-e.~or binary si~slals ASF 0-9 which are 20 addad to thQ ~u~ntlty 63 1~ ~e opera~d 2 scale factor is larg~r or ~ubtra~ d i~o~ the~ qu~t~ty 63 i~ the operal~d 1 -scale ~c~or i~ larg~. The ou~put ~lgnals Aq~MP 3-9 are loaded into an P~q~ ~gi3ts~ 730-l000 Bit positions RTMP
0-3 ~tor~ a bin~ry cow~t of the nwr~er of words o~ the 25 op~rand to th~ le~t o~ word containing the least 3ign1fic~nt d~git pol~itlon. Bit position~ RTMP 4-6 ~tore a binary nu~er indlca~ng the la~t si~nificant bit posltion.
Signal~ ~ 4-6 ~ndloat~ n~b~r of zero~ to the righ~
o~ tho loa~lt ~igni~ic~at dlgit .
A co~ ato~ 730-104 cOmparQs ~i ~al~ RTMP 0-3 and ~P 0-3. ma d~ cs aquals the number of words of the opa~d to bs ~ocolv~d ~y the d~cim~ nit 730 from cache 750.
me blna~ word ~ t }~ 0-3 is incremented each ti~ a ~5i~315~

~2 word of thQ ope~d i~ lo~ d into the RDOD regi~ter 730-154.
~e dif ~er-nca b~w~ blr~ als RTMP 0- 3 and RLMP 0- ~
is zero wh~n th~ 1 ~t word o~ operand i3 recei~ed in the declmal 7~it 730 ~lar~y ~nabling tha Ar B output ~ignal of S tho oompaxat~r 730-104~ miS enables the ~SC 0-3 output o~ TM5C loglc co~trol 730-106 which i~ ~ binary c07~t of the n7~r of zero~ to th~l rig7ht of t~ lea~t significant digit.
Ihi8 co7.~nt i~ appliod to ~e ~ ISC logic control 730-106 by ~ignal~ R~P 4-6. ~h~ TMSC 0-3 count is applied to a ZIDML
10 8hi~r 730-120. ma ~ r of low order digit positions to tho rtght ol t~ ~t s~ ficant digit to be forced to ZERO 18 lndlc~t~d ~y the~ r of succes~i~e sigrlals st~rtlng wlth tho 2IDMS. 7 qlgnal whlch are forced to ZERO.
ma ZI9Mr. 0-7 si.gs~ appliad to the ~EZID 0 7 logic 15 control 730-13~ oul:put ~ignals EEZI~ 0-7 reflect ~he ZMIDL 0-7 ~ gnal ~ta~ and enabla the high order positions o~ the ZID ~itc~ 730-150, forcing the low order positions to the rlght o~ tha lo~t slgni~i~ant ~git to 2ERO.
mO A~2`A 33-36 ~ als are racolved from the address 20 proparatlon unlt 70~-3 ~or op~rands 1, 2 a~d 3 and are stor~d in re~ 0, RCPl ~d RCP2 respectively of s ro~st~ ba~c 730-42.
The AS~A 33 ~ nl indicate3 the least significant bit o~ th~ C~lCh8 750 atdra~ o~! the high order word of the 25 op~rand lndlcatlng whothe~ s woxd ~8 fros~ an odd or even m~mosy addsa~ loca~lon. mis i~ u~ad in the compacting of op~r~ds h~ving 9-blt. ~a~cters which are recei~ed in the d~ci~l unlt 730 as 4 da~ arscterq per word to 3-~ciJa~l dlgl~3 pè~ word, which i8 ~ent to tha execution 30 unlt 714.
F~or 9--~lt dtar~ctor op~rar~ds, 3ignals ASFA 34 and 35 indic~to the ywltlo3- o~ the leading character in the high ~, .

5~S~

order wGrd of the ope~ d. For 4-~it character operand WO~d~l, 8ignal8 A~FA 34-36 indicate th~. position nf the leadl~ng c~aracte~ in t~e high order word of the operand.
Ths opersnd po~t~x ~tored in ~egi~ter RCP0 i~ selected 5 through th~ ~C~0 pwitlon of ~ ZCPA switch 730-44 and applied to a ZCPNB switch 730-48. ~he ZCPA 0-2 po~ition of the ZC~NB swltch 730-48 1~ ~81QCted lf operand 1 con~prise~
9-blt c~aract~r3 ~nd tl~ ~CPA 1-3 position i~ selected if op~rand 1 compri3~ 4-~t characters. Signal [ONE/AC~NBB
0 i8 appl~ed to ~n lnpu~ o~ ACPNB adder 730-50 and is added to t~ ~CPNB 0-2 with~18 ii~ operand 1 hA~ a leading ~ign.
Thlq i~ lndl~nted by t~ bit o~ ~e RTNS0 register b~ing a ~EBO. Tho ~CPNB 1-3 output of the adder poir~t to the mo~t sls~l~lcAnt daciD~l d~ glt po~ition of 'che high order 15 word O~ op~r~ t 1~ roceivod in the decimal unit 730 fro~ c~che 750.
An AC~DF ad~r 730-52 subtracts the high order digi t po~ition ~ro~ the~ A~ 7-~ 3ignal output of the ACP~ adder 730-62. mO AC~R 7~ xy signal indic~te~ the number of 20 ZE~O~ to t:he le~t o~ st sign$~icant diglt in the oper~nd hls~h ord~r word to b~ tran3~rred to the e~cecution ~it 714. Subtracting bln ry ~ignals P~CPNB 1-3 from ACPR 7-~in th~ ACPDF addQr 730 52 give~ an output binary value signal AC~?DF 0-3 which 18 tl~o ~unt the operand being received from 5 cache 750 i~ shl~!tad t~ ba properly aligned for tran~fer to cocu~on l~it 714. ~hi8 ~h~Lft value i5 ~tored in an RDSC r~g~8tor 730-58 t:hrough a switch 730-56. ~he output of th~ ~DSC r~gi~ter 130-5~ ~8 applied to a qhifter 7~0-i56 through a 2~SC ~witc3~ 730-72. 'rhe AC~D}' adder 730-52 calcu-30 latlon is m~ds 0~p~rAtoly ~or op~r~nd 1 and oparand 2 ar~dalign~ tho operands solativ~ to e~c~ other ~or nwr,eric proc~oslng in t~e ex~cu~on unit 714.

~5~5~

A ZCPWC switch 730-46 selects the operand character pointer for 4-bit and 9-bit character operands and a~lies it to an ACPWC adder 730-66 where a ouantity ONE is sub-tracted to give an output signal ACPWC 0-3. A ZLNT switch 730-64 selects the operand 1 length for the operand 1 load and the operand 2 length for the operand 2 load for in ut to an ASWC adder 730-68 where it is added to the ACPWC 0-3 binary signal. A ZSWC switch 730-70 selects an ASWC 0-4 switch position for a 9-bit character operand and an ASWC
0-3 switch position for a 4-bit character o~erand and applies the ZSWC 0-4 binary output for storage in an RSWC
register 730-110.
The RSWC register 730-110 stores a binary count of the number of words in the operand to be transferred from cache 750 to the decimal unit 730. The count in the RSWC
register 730-110 is decremented by a [CNTDWN-RS~C signal each time a word is received in the RDID register 730-158.
The boolean expression for the signal is:
[CNTD~N- RSWC = ((LDRRWC(FDID~(FOPlLD ~ FOP2LD) .DFCQ ~ [$RDoDA-(DUCMD 303 ~ FOPSTR))) [LDRRWC = (FDUACT-FRDPl + SFOP2LD
~ FLDCOMPL~(FOP5TR t DUCMD 303)) DFCO = RSWC0~RSWCl~RSWC2~RSWC3~RSWC4 [$RDODA = (FDATA-AV + DUCMD 203 + DUCMD 310 ~ DUCMD 309 + FRPK-DUCMD 303 ~ FRPK~FALT
'FSWRT)~DUCMD 311 The RSWC register 730-110 at zero indicates that all the words of the operand have been received by the decimal unit and the DFCO signal output sets the FDFD flag in status flag control logic 730-202.
The ARWC adder 730-60 output siynals AR~C 0-6 are stored in an RRWC register 730-88 when the [LDRRWC signal is at logical ONE. The RRWC register 730-110 stores the number 7~

o f word~ in ~e operand t o be trans ~erred to the . execution unit 714 during thQ load operation. E~ch time a word of an opQEand is lo~d~d into t~ RDOD regi~ter 730-154, the RRWC
reglster 730-110 1~ q~cr~mentad by one when the ~C~TDWN-R~IC
5 ~ l is at logic~l ONE:. The boole2n expression is ~CNTDWN-RRWC 8 (b~;5. (FOPlLD + FOP2LD) [SRDODA
( ~FOPSTR ~ DUCMD 303 + (~-RDSC0) ) ) ~FALT- (F~i~
DRGTE + (~- ECPCO ~ ZTNSA0 ) F~WRT) ) ~F~ + F~PK-DUCMD 30.
FCPC0 + ZINSA0 ? ) DTECO ~ RRW~-~-~-RRWC6 me R~WC r~gi~t~r 730-ll0 ~1: ZERO indicate~ that all the deci~l dlgit~ o~ t~e opoxand have bsen 3ent to the exacutlon unit 114 l:y t~o D~CO output signal setting the .
FDTED flo.g in 8tatu8 flag control logic 730-202.
The FOPl~D ~laq l~ ~Qt by the firnware initiating a DUCMD 301 ~ignal lndic~ting a "Read Operand through Decimal Unlt~ op~ration. ~e 2~PlLD ~lag i~ re~et when the DFCO and D5'ECO ou~put 3ignalJ tndtc~te that both the ~SWC r~gister 730-ll0 and th~ R~IC r~ ter 730-88 respec~ively have decro~nt~d to 8ERO du~ng the opsrand 1 load op~ration.
The FRDPl flag sat il~dlcates that the DuCMD 301 has been is~d to re&d operand 1 through tha declmal unit 730.
The FOP2I,D ~lag 18 set by the flrnw~re to read operand 2 when the DUCMD 301 has b~en i~sued with the FRDPl flag set.
The FOP2~D flag ~s r~ t and ~h~ FLDCOMP flaq is set indi-cating that tha load op~ration $~ complete when both the R~WC ~nd ~SWC regl~tsrs havo d~cromented to ZERO during the oper~nd 2-op~r~tlon, l.a., bs:)th operands 1 and 2 ha~e been . procoes~d in ~h~ decl2aal unit ~30 ~d transferre~1 ~o the execl~tion un~ t 7l4 .

~ 5~35~

.~

An ~ZCl reqist3r 730-96 and an RLZC2 regi~ter 730-98 are usl~ad to indlca~ tO the firmwars the num~er of zeros to the le ft o f ~e ~Dst 81 gn~ fl cant non~ ze ro di gi t in ope ran d and op~and 2 r~2~p~tlvely. Regist2r positions RLZCl 1-3 S ~nd RS-ZC2 1-3 are load~d wl~h the i~W~ 4-~ output Rignals of t~e ~WC co~ 730-60. Thi~ essentially prebiase~ the word count portlon 0~ nd F~LZC2 regis~ers, bit po~l~on~ ~ZCl ~nd ~ZC2 0-3 with the val~e of 7 word~ minus the nu~ o~ wos~da to bl~ ~ent to the e~æcution unit ~binary 10 value o~ ~C a~ to~ 730-60 bit posi~ion~ ARWC 4-S) and equ~ls th~ su~or o~ w~xds not b~ing ~ent to th~ execution unit '714, 5h~ nu,~:r o~ lsading zero~ to the lç~t of each op~rand i8 ~on~ed a~ t~ output o~ the ZID 730-lS0. The ZID
04-35 ~ ~9 applllsd to the load zero count logic 15 ~30-182 and th~ output ~ZC 0-3 ind~cate~ the numb~r of leading z~ros in ~te word. Signal LZC0 being a ONE indicates that ~ll ~e de~ci;~al ~gits of the word are zero, a ONE is . addad eo th~ RIZCl or ~C2 ~gi8tes3 at t:he bit 3 position and t~ n~xt word i~ d from cache 750. Aqain, if the 20 word cont~ln0 all ~an~s then ~lgnal I,CZ0 is a ONE, a ONE
1~ agA~n added to ~o ~lk 3 position ~nd ~e next word is rcce~v~d f~m co~che 750. AB8U~ that the next word received ~rom cach~ 750 do~ not cont~in all zero~, then the ~i~;nals I.2C 1-3 indicat~ nu~ r of zero~ to the left of the first 25 ncn-z-ro decl~aal diglt. ~i~ ~et~ an FZC~ ~lag indicatir3g to the logic ~at ~ Z~ to ~h~ left count i~ co~leted for thl~ op~rand. m$~ count i5 tr~n~f~xred throug~ a ZEDC
~w~td~ 730-~ to th~ ~LZCl ~nd R~ZC2 registers and stored in bit po~ltlons ~ZC~. 4-6 and RLZC2 4-6 for their resp~ctive 30 oporand~.
Tho blna~y v~ tored in the RLZCl regi~ter 730 96 and 21ZC2 r3gistar 730-ga a~ tha count of the number of t8ci~a~. dlglt po~ltlo~8 to th~ l~ft of op~rarlds 1 and ~

~45~3S~
. .

respectlvely to fill l:h~ 64 decimal digit positions set asid~ in th~ Qx~ut~on urlit '714 for each operand.
Tho output o~ 3 ~ZCl and RLZC2 registers are trans-ferrad und~r girm~ars cotltrol through a 2LZC switch 730-76 5 po~ltlon 3 o~ ~o ~ID ~wltch 730-150, through the ZDOD
~witch 730-152 to the RDO~ register 730-154. Th~ ARWC
signal lnput to the ~$ZC switch 730-76 provide~ ~he number of wordD tsans~3rrad ~or a long operand. The ATMP signal input provido~ th~ wox~ location to which the rounding 10 constant t ~ ~dd~d. The boolean expressions controiling the RCZCl r~gt star 730-96 a~d the RC2C2 regi~t2r 730-98 for lo~d~ng the low o~da~ po~ltior~s of .the registers are R~ZCl~ N ~I~RDODA POPl~D.FZC~ + (DUCMD 305 ~ ~C20)-~F) [SR~ZC2T~ $~DoDA . FOP2LD~ + (DUCMD 305 ~ FCZ0) DED~Z) Tha boolean oxpr~ on~ for loading the high order posi tions of tha rsg~tcr~ ar~s ZClU ~ SFOl?lLD ~ (DUCMD 305 + FCZO) ~DEDCZ
lr.DR~C2U. ~ S~.OP2~D + (DUCMD 305 ~ FCZO) i5 Tha r~gi~ters aro incr~nted by [CNTU~?~ZClU ~ [SE~DODA-FOPl~D-~-LZCO
tCNTUPR~ZC2V ~ ¦ SRDODA FOP2 LD . ~. LZ CO
~5 SFOPl~ DUCMD 301.o~ F~;- (DlEQOVP-D~QOVP
~ + ~CRPl) ) SFOP2~D ~ tPOPl~D-~. (DUCMD 301 + FR~DP2) (DFCO
~D~D D5~CO l $ RDODA ~ DFCO . FD ID . FDTED
~ D~CO- [SR,OOD~-FD~D) + ~FZ~I~5-~J
DUCMD 301 PRDPl ) ~) DlEQOVP -- (Æ~- ROPl ~l$t~O) D2EQOVP ~ ROPl ~ ~iSElO) ~5~3S~
1g ~r~

LONG ~ NDAGTE16 + AL.NDBGTE16 + ALNSGTE16 FMYDV ~ Dl~QFLP + D2EQFL?
A~NDAG~Slli a AI~1!3DAl ~ ALNDA2 ~NI)E~G~rE16 ~ A NDBl ~ ALNDB2 ALNSGTE16 ~- A~NS3 + AI~NS4 ~ ALNS5 . ~

s~s~

'9 Op~ d3 a~e tran~rrod from cas~he 750 to the deci~a' I unit 730 over 3ig~al bU8 ~ 0-35 and are loaded into an ~DID regi8ter 730~15~ undex finTlware control. The finm~rare ~ 5 initiatos - a DUCMD 301 "~ad Operand Thxough ~ecimal Unit"
s com;~nd. Thl~ sats the F~Pl arld the FOPlLD f l ag~ tocondltlon t~e d~clm~l unit 730 logic to receive operand 1 ~rom cach~ 750.
~SWC regi~ter 730-110 is loaded with the nwnber of words to be r*c~lvod ~xom cache 750~ The RRWC register 730-88 i~ load~ wlt~-~e number of words to be sent ~o the execution unlt 714. The RSWC regi-~ter 730-110 is decremented by ONE ~or each wo~d recsived f2~0m c~che 750. ~he RRWC
ragiste~ 730-88 is dec~mented by ONE for each word sent to ~7 15 th~ ~xoc:ution ~mit 71~. The boole~rL expressions for the loadlng and decr~m~ntlng the RSWC and RRWC registers 730-110 ~nd 730-8~ ro~p~c~i~ly are:
[LDRSWC ~ ( (FDW~C'r~ PRD~ + (FLDCOMP!L- DUCMD~
~ + S~OP2LD) tCNTDWN--RSWC -- ( r~ (PDID (FOPlLD + FOP2I.D) ~ + t$~Do~A~ (DUC:MD 303 + FOPSTR) ) ) tI~RRWC ~ (FDUACT~ + SPOP2LD + FLDCOMPL

~ DWN-RRWC -- (D~- (FOPl~D + POP2LD) ~ ~SRDODA
. + t tP'OPSTR ~tDUCMD 303 tDMSDRGTE
~DMSEQ-RDSCO) ) ) ) ~- ~
~ RGTE + ~ ZTNS~5- FCPCO ~ Zl~IS~O) FSWRT) ) ~;~ + FRP~ DUCMD 30 3 FC~CO + ZN5'SAO) ) 30 me FOPlLD flag is rosot on t~3 cycla following the RSWC and RRWC rogl~t~r~ counting down to zero by the DFCO and l:)T~:CO
outputs ~t logical ONE. The bc;ol~n equation~ are li~ted ~5~

supra. This indicates that all of the operand l words have been received by the decirnal unit 730 and sent to the execution unit 714. The firmware initiates another DUC~lD 301 command which sets the FOP2LD flag since the FRDPl flag is still set conditioning the decimal unit 730 to receive operand 2 words. Again the RSWC register 730-110 and the RRWC register 730-88 are loaded with a number o~
words received from cache 750 and sent to the execution unit 714 respectively and counted down to zero indicating to the decimal unit 730 that operand 2 was received, processed, and transferred to the execution unit 714. The FOP2LD flop is then reset.
The operand may contain 4-bit or 9-bit decimal digits.
Operands containing 4-bit decimal digits are processed through the decimal unit 730 differently from operands containing 9-bit decimal digits. Assuming that the operands contain words with 4-bit decimal digits and the first word is stored in the RDID register 730-158, control signal [lZPK is forced to a ONE selecting the 1 position of a ZPK switch 730-160. The RDID 0-35 output signal is compacted from a 36-bit word to a 32-bit word in the selected position 1 of the ZPX 730-160 switch and outputs as signal kus ZPK 0-31 which may indicate up to eight 4-bit decimal digits. The negated output signal bus ZPK 0-31 is stored in an RPK register 730-162. The decimal digits of this data word are the high order digits of the operand.
If the decimal digits of the first word of the operand outputting the ZPK switch 730-160 have a sufficient number of decimal digits to be sent to the execution unit 714 as specified by the decimal unit 730 logic then the necessary switches are conditioned by their respective control signals to load the RDOD register 730-154. In this case the ZPR 0-31 output signals are 5~5~
1 .

~lected through a ZPKR ~witch 730-164. The output ~ignals ZPKR 0-31 a~e appliad ~ shi~tQr 73D-156 wher~ thPy a~e shifted to the right ~n a~ouslt ~pecified by the ZDSC 1-3 bin~ hift count oul:put o~ th~ RDSC register 730-58~ The S ZDS 0-31 output ~ignal~ are applied to a ZID switch 130-150 wh~e non d~cim~l diglt char~ctar~ ~uch as signs and Rxponont~ and alalo non-op~rzmd repl~cement characters are replac~d l~y zero u~ control of the [EZID 0-3 ZID switch ena~le signal output o~ th9 [EZID control logic 730-132.
10 me output l~ignal Z~:D 4-35 ~re selected by position 0 of the ZDOD ~wltch 730-152 . ZDOD 4-35 output signal are qtorad ln th~ ~OD ~Qg~st~r 730-154.
If the d~ta wo~ do up of 4-bit digits will not fill a su~ficlent portio~ o~ th~ RDOD ragister 730-154 for transfer to the ex~cution unit 714, then the first word remain~ stored in ~he RPK register 730-162 and the next data word Or 4-btt diqi~-8 i~ transferred from cache 750 to tho RDID rQgist~r 730-158 und~r ~irmware control. The ~acond data word i~ appll~d to th~ shifter 730-156 through 2û the ZPX ~witch 730-160 and. the 7PKR ~witch 730-164. The first data word stonad in the RPK rQgister 730-162 is applied to the ~hl~ter 730-156 thraugh ~ ~P~L switch 730-166. The shlft co~t signal 8D~C 1-~ ~elects 32 of the 60 input~ to the shiftQr 730-156. The ZDS 0-31 output ~ignals are 25 stored in the RDOD r~gl~tsr 730-154 through the ZID switch 730-150 ~nd ~ho ZDOD ~witch 730-152. Necessary zeros to the left and.rlght ~re ~dd~d to the ZDS 0-31 shifter output under control o~ the lEZID 0-7 ~raable ~ignals whlle the operand word i8 ~wltch~d through the ~ID qwitch 730-150.
If the op~rand ~rom cache ?50 to the decimal unit 730 con-~ st~ of a 9-blt d~cimal digit the first data word con-taln~ng ~ maximum o~ 4 decim~l digit~ tored in the RDID

~5~5~

~, register 730-158. Th~ g-bit d2cimal digits are stripped of th~ S hlgh ord3r b~t3 of each d¢cim31 digit and compact~d a~ tha ~ord 1~ swlteh~d through ~h~ selected 2 position of th~ ZPX l~witch 730-160 ~nd are stored in either the left 16-~it~ of th~ RPX 0-15 reyister 730-162 if from an even addre~ in cach~ 7$0 or ar~ stored in the right 16-bits of the gPX 16-31 r2sl~t~x 730 162 1~ ~rom an odd address in cache 750.
If a d~ta word m~y be made up to send to the execution unit 714 th~n it inputs tho ~hifter 730-156 through the ZPX ~witch 730-160 ~nd th¢ ZPKR switch 730-164. Note that the d:~cimal dl~its arc rap~ated in ZPK 0-15 and ZPX 16-31 switch positlon 2 a~ t~Q digits pe~s through the ZPK 0-31 swit~h. The extr~ou~ d~git~, the 8ign, exponent and rewrite digits ~ tripped from t:he data word in the ZID
t30-15C sw~tch. Thæ ZDS 0-31 ou~put of the shifter 730-156 i8 ~tored in th~ RDOD regic~ter 730-154 through positions 0 of-ths ZID ~wlteh 730-lS0 and the ZDOD switch 730 150 and tho ZWD ~witch 730-152 .
A~-umlng that the first dat~l word comprising 9-~it d ~:actl~r~ wa~ d ~rom an a~3n cache 750 addresR and stored ln ~P~ 0 15 ragistar 730-162, the ~e~nd data word would be rec~ived ~ro~ an odd cac~e 750 addre.~s and would ~e sto~ad in the RPK 16-31 regLster 730-162.
mO ~cond d~t3 word i9 applied to the ahifter 730-156 through ths ZPX switah 730-160 and the ZPXR switch 730-164 a~tor ba~ng ~ts~lppod o~ tho high order 5-bits of each 9-bit d~cl~nAl dlgit ond packod lnto both halvs~ of the ZPX 0-31 data word. Tlle flr9t data word 5tored in either the odd addr~ or ev~n addrel~ h~ of the RPK regi~ter 730-162 i~
appl~ed to the shi~tar 730-156 through tha ZP~tL switch 730-166 .

~5~5 ~3 Control sigs~al~ [lZPK and [2ZPX ~elect orle of ~our po~tlons Oe ths ZPX ~wl ch 730~160. Posltion 0 i~ selecte~
for the store opos3tlon, po~ition 1 for ~che 4-~it digit oporand, poslt~on 2 ~ox the 9-bit digit operand and poqition S 3 for th~ xou~ding op~atlons. The bool~an equations are ~lZPK ~ ~TNS~O~FO~l~D ~ ZTNSBO-FOP2LD + DUCMD 309 [2ZPX 8 ~n~ OPlLD + ~TNSBO~FOP2LD + DUCMD 309 Control ~ign21 ~$RP~U enables ~he loading o f the RPK
register 7~0-162, ponltlon~ ~PX 0-15 for 9-bi~ operands 10 from an evQn cache 7S0 addre~s, and 4 bi t operands .
Control slgn~l [S~K~ enable~ ~he loading of RPK register 730-162, posltions RPX 16-31 for 9-bit operands from an odd c~ch~ 750 addre~-, and 4-bit opara~ds.
Th~ bo~lea~ e~uatlon~ ~re ~$~PgU ~ DUCMD 305 ~ FDID-(ZTNSA0.FOPlLD
+ Z ~ S~OFOP2LD ~ ~ FOPlLD
PCPCO ~ ~N~OFOP2LD~FCPC0) ~P~FOPST~ + FALT
. ~SWB.T- FSND) ) ~$RPKL ~ DUCMD 305 + FDID- tZ5NSA0-FOPlLD
+ Z5NS~0 . FOP2W ~ Z~N~- FOPlLD
FC~C0 ~ ~- FOP2 LD ~ FCPC0 ) + ~-FOPSTR~ (FALT~
+ F~.FSWRT~FSND) ) 2S Control slgnal~ fOZ~CL and lOZPX~ enable respectiv~ly tho ZPXL swltch 730-166 and the 2PKR switch 730-164.
Control signal tlZPRI, at logic~l ONE -~alects the ZPK 4-31 b~t pollitlons from 2PKL swltch 730-166 and the RPK 16-31 bit position fro~n ZPXR swltch 730-164. Control signal 30 [lZPX~lU, at logical ON~, elac s th~ RPX 0-15 bit po~ition~
of tha ZPX~ switch 739-164.

- - -1~5 [OZPXA W FOPlI,l:~ ~ FOP2LD ~ tFOPSTR + DUC~ID 303) ~ (E~P~ (D~SDREQlO-RDSCO + DMSDREQOMl + ~s~' ~æa~, FMSEQ ) ) S ~OZP~R ~ FOPl~;D + FOP2LD + (FOPST~ + DUCMD 303) (F~ D~SD~EQ21~Rl)SCO + DMSD~:Q10 ' ~) t ~;~ . ~ - ~ FM~ DRGTE
~5~ t ~)DMSEQ) + DUCMD 3O9 ~ ~ DlEQFI.P t (A7i~ii~) FRCMD
+ (1~ 1~) .F~CMD) ) tlZPXL ~ (D1~3D~Q}~Ql~RDSCO + DT~:CO-~) F~IPX- ~FoPS~rR ~ DUCMD 303) tlZP~RU ~ (FOPl~D ~S + FOP2LD ~) ~ + (FOPS~R + DUMCD 303) ^FRPK
~ ~DMSDEaWEQl~ RDSCO + I:TECO ~) DMSD:REQ10 - DT}5CO ~ DMSI: F~WEQl DMSDR~EQMl -- RQWt:O ~ FE~7Cl RRWC 2 RRWC 3 RE~WC 4 RRWC 5 ~RWC 6 DMSD~EQOMl i~ DTECO ~ DMSDRWE:QM2 DM8D~TMl ~ ~JC13~DM~I ~Qhl DM51~R~T~l2 ~ ~CO~
DP5~3DRæQ21 -- D~D~ 2 + DM5DRWEQl Dq!ECO ~ ~ ~ ~- ~ ~ ~- ~5 ~ ~
DMSDRW~Ql ~ RRWC:3 ~ RRWC4 ~i~- RRWC6 DMSDRW~Q2 ~ ~-g~-~W;~-~-~RRWC5-~WC6 ~ha. boolean ox~?r~3ions for the control ~ignals that condltlon the opara~sd word~ during both the load and store operation ar~ a~ ~ollows tlZlD ~ DUCMD ao3 I DUCk~ 310 ~ DUCMD 311 +
~-DUC~ 309 ~2ZlD 0--7 -- DUCMD 310 + DUC~ 311 ~ (F~-FRCr~D
3 0 DUC~) 3 0 9 ) + Z C~DG -M~S X
~lZDODO -- ~ ~S~RPXD + [UNP~DI.WR ~ ~UNPRDUPR ~ [lZSMRO
2Z~o ) 5~
~S

.
[12DODl - (~STR~XD ~ lUNPRDLW~ + ~UNPKD~PR (~lZSMR2 + ~2ZS~R2) ~lZDOD2 - (~ST~PX~ + [UNPKD~WR ~ [UNPXDUPR (~lZSMR4 + [2~R4) [lZDOD3 ~ ([5~RPRD + [UNP~DLWR + [UNP~DUPR ([lZSMR6 + ~2 zSMR6 ) 12ZDOD0 ~ ~4S~RPXD ~ ~UNPXDUPR + [UNPRDLWR (~lZSMR0 - ~ [2ZSMR0)) t2ZDODl Y ~4S~gP~D ~ ~UNPRDUPR + [UNPKDLWR ([lZSMR2 ~ [2ZS~R2)) ~2ZDOD2 ~ ~45TRPgD ~ ~UNPKDUPR + ~UNPKDLWR ([lZSMR4 + [2ZSMR4)j [2ZWD3 - ~4~RPXD + [UNPKDUPR + [UNPKDLWR (~lZSMR6 ~ 12ZSM~6) [12SMR 0-7 ~ SIGNMASX ~ REWUM 0-7 + REWLM 0-7 ~2ZSMR 0-7 Y EXPMA5K + REWUM 0-7 + REWLM 0-7 tSTRPXD - (ZTNS~0 IDUCMD 303 ~ FOPSTR)) lUNPKD~W~ - t~ h~ (DUCMD 303 ~ FOPSTR)-FCPC0) ~UNPXDUPR ~ DUCMD 303 ~ FOPSTR)-FCPC0) An ACPR ~dde~ 730-62 c~lculate~ the number o f ze ros d~ git~ to tho l~l~t of th~ oparand neces~ary to fill a 64 digit block of stor~g~. Ths adjusted length ZLNADJ 0-9 output of switch 7 jO-26 i~ subtract~d from 64, the maximum number of digits that w~ e tran~f~rred between the decimal unit 730 ~nd tl~Q axecution unit 714. The output of tho ACPR idder 730-~2 1~ ~tored in the RLM~ register 730-102.
The R~MP 4-6 cutput ~1gnals, the low order 3-~its, store the nwrber of 4-bit d~eim~l dig~t positions to the left in the high ordor word ~o. bo ~orct~d to z~ro and i3 applied to the shift cous~t input of ~ ZIDMU shifter 730-130. Th05e output sigslal~ 2~DMU 0-7, whlch i.ndicate zsro digits to the left, ~ ~5~35~

~s~
ar~ forcod to ~ERO. Thi&l ~orces the indicated output~ of ~EZID legic co~trol 730 132, . ignals [EZID 0-7 to ZERO
theroby ~orcing l:ha ~ls~t~d digit posit$on~ of the ZTD
swltch 730-15a to ~E~O of the fir~t word of the operand S rE~c~lved by th~ dec~ unit 730. If the opexand had a l~ading ~ign, it woul~ have been replaced by ZEP~O in the ZID 730-150 switch ~i~co thR 3ign character position count wa~ ~lubtrac~d ~rom ~ch opf~x~d length in adders ALNDA
730-18 ~nd AI.NDI~ 730-20 re~pectively. Also, rewrite ch~ractors in tl~e op~rand word would be replaced by ZE~O's.
~n A'rMP adder 730-30 calculate~ the number of zeros to the right of t~o l~t signi~icant digit position of the oporand havlng the lar~r scale factor. Switch Z~SFB 730-28 ~elect~ the n~or o~ zelroQ to the right for operand 1 or opelrant 2 durln~ tha~ cycle in which the operand transfers from c~c~o 750 tO tho dscimal unit 730.
$f the op~rand 1 scale factor is larger than the operand 2 scalQ f~ctor t~en th~ ASF 0-9 input to switch ZASFB 730-28 1~ ~ poslti~ nu~bor which i~ subtracted f rom 6 3 in the ATMP
add~r 73û-30 and th~ ference, output signal~ ATMP 3 9, ar~
~torod in ~ R~MP ~gistar 730-lO0. The low order pssitions 4-6 input a 1!M~C logic control 730-106 and output a~
~lgnal~ TMSC: O 3 whlch are applied to the shift count input of a ZlDM~ ~hlft~r 730-128. This forces the ZI~ 0-7 output 3ign~1s to lndlcat~ t:he numb~r of digit zeros to the right of th~ aperasld~. mO 8ID~L 0-~ output signal~ are applied to tl Q lEZIi loglc cor~t~l ~30-132. 1~e [EZID 0-7 output s~gnal~ conditlon th~ indicsted low order digit positions of the ~lD swltch 730 150 to ZERO ~ereby stripping trailing glgn, expon-nt, as~d r~write characters from the operand word.
Slgn~ls R~MP 0-3 the output of register 730-100 and slgnal~ RL~ 0-3 the output o regi~ter 730-102 indicate the cycla on whlch the operand word which require the ZEROs l~sas~

~r to ~he rlght i8 tran~arred from th~ decimal unit 730 to tha executlon unlt 714. Th~ 64 deci~al digit ~aximum tranJf~r is mada up oi sight words of 8-decimal digit~ per word. SignAls RLMP 0-3 ars a binary representation of the S number o~ word~ t~ th~ left of the word containing the most ~igni~lcAnt dlglt that cDntains ~11 zeroR. Signals R$MP
0-3 aso a ~n~y r~prss~ntation of the number of words in the maxlmum trand~r ~inu~ the word in which Z~Os to -~e right are ~orc~d. Plus 1 i8 added to binary signals RLMP
0-~ each t$mo r~gl8te~ R~O~ 730-154 i~ loaded. Signals ~TMP 0-3 and R~MP 0-3 ar~ compared in a comparator 730-104.
Signals TMSC 1-3 zse ~orced to ZE~O on the cycles where b$nary aignals ~TMP 0-3 lq greater than binary signals RLMP 0-3 Z~Os to th~ ~ight are ~orced in the ZID ~witch 15~ 730-150 on the tran~fe~ cycle whare ~omparator 730-104 indic~t~h that th~ binary values of RLMP 0-3 and RTMP 0-3 ~re Qqu~l.
Control 3ignal lSRTMP ~nables ~he input loading of R$MP sogi~tar 730-100, and the RLMP 4-6 bit po~itions of the RIMP registor ~30-102. .Control ~ignal [SRTMP enables tha output o~ th~ RIMP 0-3 bit position~ of the RLMP
r~gi~tQr 730-102.
Contsol ~gnal t ~ en~bles the output of the ~MP 4-6 blt po8ition~. Control signal lCNTUP-RL~PU
incsem~nt~ ths RLMP 0-3 bit position~. The boolean equat~ons aro l$RTMP ~ (FDU~CT~ FI + SF0P2LD) [ZERO/~LMP~ ~ ~FFDO ~ (FOPlLD ~ ~P2LDJ~ ~ZIDA)) [CNTUP-~LMPU ~ ~(FOPlLD ~ FOP2LD)-[$RD0DA-SF0P2LD) . .

~5~5~
g~
_~

Tha FPOP3 cycl~ load~ d~3crlptor 3 information in-to regist~r RSS~ 70~ 1S4 for a 3 de~criptcr instrue tlon. In d~c-m~l a~lthm~tic in~tructions, de~criptor 3 d~in~o tho ~l~ld lnto whlch the re~ults of the cal-culatlon Oe ~he de~cs~ptor l ~nd de~criptor 2 operands ~re stor~d. Som~ 1n~truction~ store the re~ult of the descrlptor 1 and ~e~c~iptor 2 operand calculations in tho flald de~nod by d~criptor 2. In either case the RSIR reglster 704-15~ s~or~s the delcriptor information and tran~2rs it to ~he declmal unit 730 for the store op~rand 3 ope~atlon. Tho decimal unit 730 receives opexand 3 from tha ch~racter unit 720 over the RC~U 0-35 ~lgnal bus. Tho d~cim~l unit unpack~ it, adds the sign and exponant ~ re~u~red, posltion~ the operand 3 digits within th2 word, pl~ces the proper number of 2ero~ to the loft and rlght of the operand, adds re-quir6d ASCIl or E~CDSC zone bit~ and rein-~tates the portlon of ~ha flrst and las~ word.q o~ the operand 2~ th~t ara not ~2fins~ a~ part of the operand. The dec~mal unlt 730 00t8 ~p-the necas~ary control~ in the logic to r~c~v~ op~r~nd 3, manlpulate lt and store it ln c~cho 750 ln confon~nce with it~ descriptor in-torm~tlon.
~he op~xand 3 ~cale factor ~lgnals RSIR 24-29 inp~ut~ swltch ZS~N 730-2 and are stored in regi~ter ~S~2 o~ rogi~ter b~nk 730-4. For the ca~e where the lnput oporands wor~ ~uch that the decimal unit 730 did the scale factor allgnmonts, the ZSFA ~witch 730-6 selact3 the contont~ of the ~SP2 register, and the ZSF8 ~witch ~elect~ th~ cont~nt~ of either the RSFO or RSFl reglster o~ r~i~tor bank 73~-4. The regi~ter ~e-lect~d 1~ th~ ono ~torlng the smaller scale ~actor of oporand 1 or 2. Th~ FSSPD ~lag which i~ et by the ~c~le factor co~pa~l~on during the losd operation make~
the selectlon.

5~35 gol Control sign~ W~RSFl and 4WRRSF2 ~elect 1 of the RSF 0-4 r~gistes~ 730-4 in which the ~cale factor is stored.
Th~ boole~n exp~o0~10n~ are [W~RSFl ~ ((F3D~SC + FMVN) F~DCOMPL, FPOP DlEQFLP) . (EI~S) + RDESCl F~OP + (FMYDV
FP~ FPFI.) DUC~5D 308 iSIi~;~
(FMV~ + F3DESC) !~-FLDCOMPL
[~ F2 ~ ( (~IYS:)~ + FPTI. ~ FPFL) DUCMD 308 PF~-FLDCOMPL
~15I3~ (PMVN ~ F3DESC) + ~DESCO-FPOP
(~3D~C + ~MVN) FLDCOM2L FPOP DlEQF~P ) Ths ZSFB ~wltCh 730 3 outpu~ ls subtracted from the ZSFA swltch 730-5 output 1~ the ASF adder 730-10.
The ~SF0-9 outp~t signal inputs the ALNS adder 730-24 and 18 al~o 3tored ~n.the RSCLM register 730-144 where it servs~ a3 a pointor to the least ~ignificant end of the data to be ~ctually stored.
For a floatlng ~o~nt store operation, the RSF3 rogi~t~r of r~gl~t~r ~ank 730-4 tores the adjusted longth output of tho ~NDA addar 730-18 and the RSF2 raglster hold~ ~ho ef~cti~e diglt count~ of the ln-te~na~ ra~ult~ the ~r3t t~me the count is taken, i.e., the output of the ~EDC adder 730-36 and the ZEDCl-3 output of the Z~DC swlt~ 730-82 inputtlng the ZSFN
switch 730-2. I~ th13 ~a~e the co~tents of the RSF3 ~egl~tor is selectea th~ough the ZS~ switch 730r6 ~nd tho cont~nts o~ th~ R~F2 regi~er ls salected through tha ZSPB ~witch 730-8 ~nd are subtr~ct~d from sach other ln the A5~ a~d~r 730~10. Again the ASFO-9 out~ut 1J appll~ to th~ input of ~he ALNS adder 730-24 and the RSCL~ reg~ot~r 730-144. ~owever, for the purposes of obtainlng the zaro or e~foct$Ye dlglt count, the first tim~ tho op~rand 1~ ~xa~in~d, the contents of the RSCLM
regi~tor 730-144 ar~ o~er written in forming up the in-puts to the output z~ro and overflow datectlon logic ~q~

730-8~. After the first count, if the number of e~-fectlve digits i9 gre~ter than the a~justed len~th of operand 3, the declmal overflo~, flag FDOFL will be ~et and the calcul~tlon o~ the effective digit count from RSF2 regi~t~r contents mlnu3 the acljusted length fro~ the content3 o~ the RSF3 register will be Qnabled at tho output o~ the ~SCL~ register 730-144 for a sub-sequent zero and ov~rf~ow examinatlon.
The length ~i~ld signals ~SIR 30-35 are stored in reglJter R~ND2 o~ r~g~ter bank 730-12 and are swltched through the RLND2 po~ition of the ZLNDA
switch 730-16 to input tha ALNDP adder 730-18.
Control slgn~l~ t1ZSFA and [2ZSFA select the out-put~ of the RSF 0-3 re~i3ters 730-4 for application to tha plus input o~ ASF adder 730-10. Control signals llZSFB and t2ZSFP ~lact the RSF 0-3 outputs for applic~tion to tha m~nu~ input of ASF adder 730-10.
The bools~n ex~r~sions are llZ FA ~ FI,DCOMPL- (FMVN-blEQFLP) ~2ZSFA ~ F3DESC-F~DCQMæL ~ FMVN-FLDCOMPL
FlEOF~P
[lZSFB ~ R~iF~ ~ FMVN-FSSFD
F~DCOMP~ 3DESC. ~ FMVN) + FLDCOMPL-(F3DESC + FMVN)-DlEQFLP
+ FLDCOMP~F3DESC ~ FMVN)-DlEQFLP
(F~Y~V ~ FPTL ~ FPFL) + FLDCOMPL-~F3DEsC
+ PMVN) 12ZSFB ~ P~DCOMPL-(F3D~SC + FMVN)~DlEQFLP
+ FLDCOMPL-(F3DESC + FMVN)~
~FHYDV ~ FPTL + FPFL) ~45~54 ~ q I

The ign and dec~al type ~ignal~ RSIR ~1-23 are stored in regiat3r R~NS2 c register bank 730-32 and are trans errod tb~ouqh tha RTNS2 switch position of the ZTNSA sw$tch 730-36 to th~ decode logic 730-38 wher2 the corract~on fac~ors to the length are determined. If oporand 3 ia a n~ne-bit floaklng point number then 2 diglt~ ar~ su~t~actod ~om the l~ngth. If operand 3 is 3calad wlth ~ leadi~g or trailing ~ign then 1 digit is subtracted from tho length. A four-blt floating point numb9r will ha~e 3 digi s ~ubtracted from the length. The boolea~ 2xpr~s~ion~ for -~ignals D~XTX and DlEQFLP which are appliQd to th~ AhNDA adder 730-18 and the ALND~ adder 730-20 ware d~scrib~d ~upra.
The output of decode logic 730-38 is applied to 15 the othor lnput~ og the ALNDA ~dder 730-18 and sub-tract~ ~rom signals Z~NDA 0-5. The output of the AINDA adder, ~ignal~ ~LND~ 0-6, ad~usts the length to indic~te the number of declmal digits in operand 3.
Tho ALNDA 0-6 outpu~ ~ig~als are applied through the 20 2ALND ~witch 730-~2 to the lnput of the ALNS adder 730-24. Th~ sca~e factor signals A'.F 0-9 are added to the A~NDA length and th~ output ~ignals ALNS 0-9 is the ad~usted le~gth o~ operand 3. Tbe output ALNS Q-9 is applied through the zero po~itlon of ehe ZLN~DJ switch 25 730-24 to input addex~ ~RWC 730-60 and ~CP~ 730-~2 and 18 stored ~ n an RSCUM r~gi~ter 730~78. Adder ACPR subtrActs tho ad~u~eed length ~LNADJ 3-9 fro~ 64 and ie~ output ~gn~ CP~ 3-9 ind~c~tes the position.
o~ the most slgnl~i~ant dlgit to be ~tored within the ~nternal result ~iold. Sign~ls ACP~ 7-9 indicate the po~ition o~ ths mo~t signl~icant digit within the word : .

S~35~
~ Y, of th~ operand contalning the most significant declmal dlglt. Th~ slgnals ACP~ 7-9 are applled to the input of the ACPSC add~r 7 0-54.
The output of the ARWC addor 730-76, signals A~WC
0-6 ara applied to th~ RRWC regi3ter 730-88 and indicates the location of the op~r~nd word containing the most ~lgnlflca~t dl~it to be tran~erred from the decimal unit 730 to cach~ 750. A ONE ls ~dd~d to the A~WC adder in the ~a~ o~ op~ran~ 3 having a leadlng sign which would result in ano~hox w~rd baing transerred to cache 750.
~ or the flo~tlng point operation during the irst examination for zero or over~low, i.e., the DUCMD 304 chec~ zaro overflow command and for any subsequent examlnations ~or whlch the overflow fla~ FDOFL has not been ~at then the A~NDA adder 730-la output is ~e-lected through the ælN~ W switch 730-26. If on a floatlng point output re~ult th~ decimal overflow flag FDOF~ had boen ~et th~n the ALNS adder 730-24 output is selected through t~ ZLNA W switch 730-26. The ALNS
addor 731-24 ~orm~ the di~feranca b~tween the adj~sted length output o~ tho A~NDA adder 730-18 and th e~-factivo digit count mlnu~-the ad~usted length from the ASF adder 730-10 output.
The starting charactQr pointer signals ASFA 33-36 ~re stored ~n rogl~ter RCP2 of register bank 730-42 and aro selected ~y th~ RCP2 switch position of the ZCPA switch 730-44. Signal ZCPA 0-3 inputs the ZCPNB
~witch 730-~8. ~f op~rsnd 3 ~ 8 made up of 4-bit cha~actar~ then 3~qn~1s ZCPA 1-3 are selected and if operand 3 is made up o~ 9-b~t characters then signals 2CPA 0-2 are 301ect~d as the output signals ZCPN~ 0-2 to ~nput ths ACPNB addar 730-50. A ONE i~ added to the ..41,5~4 ~9 ~

ACPN~ adder if the op~ran~ has a leading sign. The outyut signals ACPNB 0-3 are applied to the input of an ACPSC
ad~e~ 730~54. SwltCh 730~56 by mean~ of the FLDCOMPL
status flag select~ s~gnals ACPSC 0-3 ~or storage in regi~tor ~DSC t30~58. The ACPSC adder ~30-54 subtracts the ~o~t sign~icant digit position within the internal oper~nd word a~ indlcated by the A~P~ 7-9 signal~ from the digit positlon within the in storage word of the most significnnt digit as indicated by the ACPNa signai to give the v~lue of the nu~ber of digit po~itions the operand to be 8tor~d i~ ~hi~ted~ This value repres2nted by signals ACPSC 0-3 stor~d ln reg~ter RDSC 730-58 is the 3hift count ~or the Z~S ~hl~t~r 730-1S6.
- The ASWC ~dder 730-68 output signals ASWC 0-6 provides input signal~ to ~SWC switch 730-70, ZRLMP switch 730-112, 2SMP switch 7~0-116 and the ZEMP switch 730-120. The out-puts of the 3witches are applied to shifters 730-114, 730-118 and 730-122. The shifter outputs are applied to control llZSMR lo~ic 730~142 and control[2ZSMR logic 730-146 for genexating t~e ~lZS~R 0-7 and 12ZSMR 0-7 signal~.
TheJe ~lgnals are applied to thQ ZSMR switch 730-180 for loading th~ ~ign, ex~cn~nt and rewrite characters into the operand 3 words. Tha staxting character pointer signals ZCPA 0-3 are applle~ to the input of ~witch 730-46 whose output, signal~ 2CPWC 0-2 are derived from signal~ ZCPA
1-2 for a 9-bit cha~cter operand and ~ignal~ ZCPA 1-3 for a 4-bit cha~aotor operand. Sign~la ZCPWC 0-3 are applied to the lnput o~ adder ACP~C 730-66. The decimal digit ON~
i9 ~ubtracted and th~ output, ~ignal~ ACPWC 0-3 are applied to the lnput the A~WC adder 730-68. The length field of operand 3, 5ignal8 Z~ND~ 0-5, are added to the starting character pointer ~inu~ ONE to indicate the character pointer for the l~st decimaL character in the operand.

~5~5~
~ 74~

The 1rst ward of operand 3 i3 rec~ived from the charactor unit 720 over sign~l line~ RC~U 4-35, through buffQr 730-168 whlch g~n0rate~ ~he as~ertion ignals RCHU 4-35 ~nd th~ n~gation ~ignal~ RC~U 4-35.
S Control ~iynal~ tlZPR and 12ZPK ~lect the zero poaition of thR ZPR Rw~.tch 730-~60 and RCHU 4-35 appear at the outPut of the ~wlt~h as 3iana~ ZPX 0-31 and ~F~ n-31.
For the lon~ oporand, that is operands greater than 15 decimal dl~lts th~ op~r~nd i9 tran~ferred from the RCHU r~gi~t~r ~20-10 a woxd at a tlmc with the word con-t~lnlng the mo~t slg~l~icAnt decimal digits being trans-farred to tha do~lmal unit 730 fir~t.
lf a Jlgn 1~ roquirod for the operand, the firm-ware loads th~ RSGN r~gist~r 720-134 over the ZADSP
lS 3-11 Blqnal lin8s ~rom th~ auxilliary arithmetic and controI unit 722 in ~sponse to a DUCMD 307 com~and n~oad tho ~U Sign Ragister". The output of the RSGN
rog~tor 730-14 i~ ~ppllad l:o selected position 1 of ths 2SMR swltch 730-1~0. The charac~er location in 20 2SM~ swi~ch positlon 1 19 ~slect.ed as follows. The output o~ th~ ASWC .adder 730-68 points to the low order character po~ition o~ a trailing sign. The out-put of tha ZCPA ~wltch 730-44 point~ to the leading slgn char~cto~ po-itio~. A ZSMP ~wltch730-116 ~elects 25 a tralllng or l~ading ~ign for 4-bit or 9-bit operands.
Tha ZSMP 1-3 shl~t co~ is ~pplie~ to an SIGNM shifter 730-118. Th~ logt cal 2~P~O input to the SIGNM shifter 730-118 JelQcts the. ono of th~ SIGNM 0-7 output signals ~or 4-bi t oper~ndh. ~e logic~l ZERO and the ZTNSA0 30 ~ign~ls s~l~ct two ~dia~unt signals of the SIGNM 0-7 output ~ o~ 9-blt oparands. The ~ignal SIGNM 0-7 output of th~ shl~tor ~elects the [lZSMR 0-7 output ~ignal ~5~5~

of control [lZSMR 730-142 which selects 1 of 8 of the switch 1 positions of the ZSMR switch 730-180 for the 4-bit decimal digit operand sign or 2 adjacent positions for the 9-bit character operand sign.
The exponent is added to the operand in response to the DUCMD 308 "Load the DU Exponent Register" command.
An REXP register 730-138 is loaded from the ZADSP 3-11 signal bus~ A ZEXP switch 730-140 selects the exponent bit configuration for an operand having 4-bit decimal characters and storing the least significant 4-bit char-acter in an even digit location in cache 750 through the ONE position of the ZEXP switch. All other exponents are selected through the 0 position of the switch. The signal ZEXP 0-8 output is applied to the 2 position of the ZSMR
switch ZSMR 730-180. The exponent character positions are selected by the [2ZSMR 0-7 siynal outputs from a control logic [2ZSMR 730-146. The signal is generated as follows. The boolean expressions for control signals [lZSMR 0-7 and [2ZSMR 0-7 are shown supra.
The ASWC 5-6 output signals of the ASWC adder 730-68 indicate the location in the low order word of the operand of the low order character for 9-bit characters. Binary ONE is subtracted from this value in an ACPE adder 730-74 to give the location of the high order digit of the exponent for an operand made up of 4-bit characters. A ZEMP switch 730-120 selects the character position and the output signals ZEMP 1-3 are applied to an EY.PM shifter 73-122.
The EXPM 0-7 output signals are applied to the control logic [2ZSMR 730-146. The output signals [2ZSMR 0-7 select the two adjacent character positions in the ZSMR switch 730-180 to enable the exponent to be written into the low order word.
For a 4-bit operand it is possible for the most significant digit position for the exponent character to be in digit position 7 and the least significant position 5~5~

to be ln digit positlon 0 of the next word. In thi~ case the EXPM ma~k 730 122 gan~rates a ONE ou~put on the EXP~ 7 signal llno when ~he Z~P 3witch 73a-120 pointer i9 at decimal 7 during ~h~ next to the la~t word received. When thc ladt word 1~ r~coivad the ZE~P qwitch polnter remains at 7, the D3ITS input ~lgnal i5 forced to a ONE re~ulting in th2 EXPM0 lino ~;~1ng ~orced to O~E thereby activating the 0 cha~acter po~tion of the least ~ignificant word.
The boolRan exp~ssion for the DBITS signal is DBITS -- DFeO (DUCMD 303 + FOPSTR) ( ACPEl -AC~E2 ~ ACPE3) DlEQFLP
Signals RDESC0 and ~DESCl are applied to the write select lnputq of RLND0-3 rogister 730-12, RTNS0-3 register 730-32 and RCP0-3 regiJt~r~ 730-42. Signal~ ~DESC0 and RDESC1 are 15 binary codod 00, 0~. ~nd 10 to identify operand~ 1, 2 and 3 respectiv~ly .
Control signals 1l2LNDA and [2ZLNDA are applied to the ZLNDA switch 730-16 a~ the ZTNSA ~witch 730-36. Status flag ~ff~ is applied to ~h~ ZL~DB switch 730-20 and the Z~NSB ~witch 730-3~.
Control slgn~l3 llZCPA and [2ZCPA are applied ~o the ZCPA switch 730-44. The boolean expre ~ion4 describing ~he ~ignals are 113LNDA ~ FLDCOMPL
E2 2~N~A ~ F3DESC FLDCOMPL
` ~lZCPA ~ F~DPl ~LDC~5~5PL + ~3~ FLI)COMPL
[2ZCPA ~ ~3DESC F~DCOMPL
Tha ZSMR 0-35 outE~ut including decimal digits, exponenes and 31gsl are ~pplied to the 2DOD switch 730-152 and aro lo~dad $nto th~ RDOD regi3t~r 730--154 for tran~fer to tha c~che~ 75 0 .
- In tho ~hort oporand ~tore the word are received from th~ ex~cutlon un1t 714 with the lea~t si~ificar~
word ~$r3t and 1~o ~t significarlt word la~t. A DUCMD 305 35 "Tr~ er Dat~ from RC~O to RPR" conunand is initiated by ~ 5~5~

the firmware. The lea~t signi~icant word is received from the character unit 7~0 o~er the RC~U 4 35 3ignal bus and is qtor~d ln the RPX r~lst~r 730-162 through a buffer 730-i68 and po~ltlon 0 of the ~R 730-160 switch. If the short operand compri3es 2 wo~d~ thon the most ~ignificant word is placed in tha RC~U r~gl~tQx on the same cycle and appears over the RC~U 4~3S ~lgn~l bus on tha followin~ cycle ~hrough - thQ ~uffa~ 730-168 po~ltlon 0 o~ the Z~K 730-160 switch and is appli~d to the input of a ZPXR switch 730-164 and a ZPKL
~wltch 730-166 as ~i~n~18 ZPR 0-31. If the short operand was only one wo~d long, ~eroR are pl~ced on the RCXU bus to serve as the most signifi¢ant word.
The negat~d output of the buffer 730-168, signals 2CHU
4-35 1~ appl~ed to th~ input of an output zero and overflow det~ctlon loglc 730-80 ~d ~he sffective digit logic 730-81.
During th~ cycle ln whlch th~ DUCND 305 is present the least qignificant word i8 to~ted for zero or overflow and the most slgnif~cant word is t~ted for zero or overflow on the followlng cycle whlch ~s marked by the FCZO flag being at loglcal O~E.
An RSCUM rsg~ster 730-78 ~tore3 the operand 3 length plu~ scale ~actor output o~ the ZII~DJ -Qwitch 730-26. An . RSCLM r~gist~r 730-144 ~tores the operand 3 scale factor out-put of tho ASF adde~ 730-10. The output~ of the RSCUM and ~5 RSCL~ r~glst~rs ~nput the logi~ u~lt 730-80.
Tho zero and ov~flow detection logic 730-80 masks out the non operand 3 ~ and lndi~ates to the firmware if the operand 3 ~ield i~ z3ro ~ince the DZERO output signal of detetion logic 730-80 ~3 at loglcal ONE in that caRe and al~o ma8~s out the opQrand 3 fi~ld and the scale factor ~lald and lnd~cato~ to the firmware if there was a non zero d~cimal dlgit in th~ character po~itions to the left of the most slgni~icant cha~scter of operand 3 in the most signi-flcant word that i8 thQ DOFL output signal of detection logic ~145~5 9~ , 730-80 is at logic~L ONE. The RSCLM and RSCUM regi~ter outputs ar~ u~ed to ~ask out the non operand 3 character position~ and, ln ~dd~tlon the RS~UM register output mA8k8 out the op~rand 3 ~nd scale factor character po~itions theroby enabllng th~ over~low ohe_k.
Th~ boole~n oxproa~ion or loading the RSCUM regi~ter 730-78 ~nd the R5ChM ~ogl~ter .730-144 i5 ~LD~SCM ~ (FLDCOMPL t~ + DUCMD 314 + DUCMD 205) The bool~n oxpre~slon fo~ decrementing bit position ~SCUM
0-6 ~nd RSCLM 0-6 is tCNTDWN~SCM ~ (DUCMD 305 + FCZ0) A DUCMD 303 ~Stox~ Operand t~rough Decimal Unit" comm~nd is inlti~tod by th3 firmware. S$n~e this is a short operand oparation, 2 words ~ s~nt from th~ execution unit 714 to the daclmAl unit 730 ov~r th~ RCHU 4-35 buq. The least ~ignl~lcant word rRmains tored in the RPK regi~ter 730-162 and the moat ~ig~l~lca~t word remains on the RCHU 4-35 bus for tho proce~lng o~ ~h~ ln~ructlon.
The RRNC r~gi~t~r 730-88 store~ th~ internal location o~ the mo~t signi lc~nt d~t~ word to be tran~ferred from the dscimal unlt 730 to cache 750. TAe register is decrom~nt~d each t~ma ~ wo~d madQ up of 4-bit charac~ers is oant to cach~ ~50. ThQ ragiQter is also decremented each t~ma ~ wo~d ~d~ up of 9 ~it ch~racters i5 5ent to an odd ~ddro8~ in c~Ch~ 750. Th~ boolean expre~ion for the d~cr-mantlng ~lgn~l tCNTDWN-RRWC are described supra.
~ hc ~DSC regl~to~ 730-58 tore~ the ~hift count which i9 applla~ to tha ~DS shi~ter 7~0-156 through the ZDSC
sw~ch 730-72.
Assumin~ th~ shiit count iq po3itive, i.e. the RDSCO bit 1 a zoro and tha M WC register indicates ~ word count of gre~to~ than l,~then the zero outputs of the ZPXL ~wltch 730-166 and ZPKR 730-164 are ap-plled to the 3hifter 730--156. The ZDS 0-31 output 5~5~.
q~ ' signals are zero and ~ra applied to the ZID sw~tch 730-150. The ZID 0-35 output signals are applied to the 2SMR swltch 730-180 wh~re the rewrite characters and lead$ng ~ign m~y bo added to the mo~t significant word. ~he ZSMR 0~35 output i9 applled to the ZDOD
switch whQre for 9-blt char~cter word~, EscDIc or ASCll zone charactars are added and the ZDOD 0-35 out-put qlgnals loaded into the ~DOD register 730-154 for tr~n~fer to cache 750. Control signal ~S~DODA at logical ONE loads the ~DOD register 730-154. The boolean expression i~
[SRDoDA 8 (~FDATA-AV + DUCMD 203 I DUCMD 310 + DUCMD 309 ~ FRPX ~ DUCMD 303 +
~ FALT ~ FSWRT) ~ 3UCMD--~rr) When the count in the RRWC register 730-88 equals ONE then the most 3ignlficant word ~tored in the RCHO
regi~ter 720-10 and appearing on the RCHU 4-35 signal bu~ is ~pplied throu~h the buffer 730-168 through position 0 of the ZPX ~witch 730-160, through po.qition 0 of the 2PXR swltch 730-164, through the ZDS shifter 730-156 where it i8 ~hifted to tha right the number of d$git positions equal to the ZDSC 1-3 binary shift count.
Zeroa equal in numb2r to the shift count are inserted to the left of the mo~t signif $cant digit position.
Thc 2DS 0-31 output ~l~nal~ are 3witched through posi-tlon 0 of the ZID ~wltch 730-150~ The output signals 2ID 4-35 are applied to the 2SMR ~witch for 4 bit charact~rs where the word i3 expanded from 32 to 36 blt posit$ons. Th~ ZSMR 0-35 output signals are qwltch~d through~positlon 3 of the ZDOD switch 730-152 to the RDOD regist~r 730-154 ~rom which the word is tran~ferred to c~ch~ 750.

~5~
. ~ ~

~ ' .

If th~ word co~pri~es 9-bit cl-aracters, the.l the ZID 0-35 output ~1gn~1~ are applied to position 2 of the ZDOD switch 730-152 i~ the word is writtan in an aven addres ln oach~ 750 or applled to position 1 of the ZDOD ~witch 730~1S2 lf the word ls written in an odd adarQ~s ~ C~ch~ 750 throu~h the ~DOD register 730-154.
Assuminy a word to ~n even addres~ in cache 750. Then the ZID 4-35 18 ~wltched through posltion 2 o~ the ZDOD-switch 730-152 where th~ 4 characters indicated by ZID 4-19 are expanded to 36 bits by adding the E~CDIC or ASCII zone characte~. on the ~ext cycle the ZID 4-35 signals are 8witchod through po~ltion l of the ZDOD switch where the ZXD 20-~5 ~lg~al~ ~e expanded to 36 bits by ad-ding the EBC~IC or ASCII zone characters.
The RRWC regi~ter 730-a8 is deoremented each time a 4-bit cha~acter wo~ is transferred to cache 750 or each time ~ 9-bit cha~cter word i5 tran~ferred to an odd ~ddreJs ln cache 750. ~he RRWC counter 730-88 is decrem~nted to ze~o with the ~hift count ZDSC 1-3 a 20 posltlvo blnary numb~r. In this case the ZPK 4-31 output ~ig~ Arc appll~d through the ZPRL switch 730-166 ~nd tha RPX 0-3 output ~ignals are applied th~ou~h th~ ZPR~ Jw1tch 730-164 and the ~econd word is procQJsed a~ bafore.
Tho ~RWC ~egiAt~r 730-88 i3 decremented to binary -1 wlth th~ ~hi t count ZDSC 1-3 a po~itive number.
The ~PX reg1Jt~r 730-162 st~ring the least significant word h~ its RPX 0-31 output s1gna1~ applied through the ZPXL switch 730-166 to the ZDS shi~ter 730-156.
30 Zero~ wore App11ed to th~ Z2S ~hifter 730-156 through th~ zPXn 3witch. Th~ ZDS 0 31 output ~ignals are ap-pll~d through the Jw1tchos to load the ROOD register 730-154 ~or transf~r to oache 750.

45~
~ol ~ .

1~ requir~d the RRWC register 730-88 is decremented to binary -2. Z~ros are applied to the ZuS shifter ~30-156 inputs. Thlo cyclQ of opera~ion enables the exponant of tralllng ~lgn and also replacement char-S acters to be stor0d ~n the RDOD register 730-154 after boing ~w~tched th~ough the ZEWR.~witch 730-180 and the ZDOD sw~tch ?30-152.
Each of the abov~ store operations is enabled by the DUCMD 303 signal 3et by a firmware command to load the word in tha RDOD register 730-154 on a first firm-ware cycle and to write the word in cache 750 on a qecond firmware cy~ls. Th~ first and second firmware cycle~ are r~poated until ~11 of the words containing oporand 3 ln~ormitlon sr~ tran~ferred to cache 750.
The s~q~ence o~ ~t8ps for loading cache 750 for a negatl~ ahlft count, l.e., the RDSCO output signal is equal to ONE, la tho s~me as for the positive shift count wlth the oxcoptlon that the binary value in the RRWC regl~ter 730-88 at ~Ach step i8 one more than its correApondlng ~alue ~o~ th~ positlve shift count.
A~ a part o~ thQ long operand store operation the fi~mwaro lnitiate~ a DV~D 304 "ChecX Zero/Overflow"
operatlon. Oper~nd 3 information is sent from the ex-ecution unlt ~14 to tha decimal unlt 730 under firmware 25 control a word at a time starting with the least sig-nlfic~nt word. A DUCllD 304 command i~ is~ued for each ~lgnl~icant word o ~ checX and the word is put into the RC~O regl3t~r 720-lO, Figure 2, at the same time. The l~st 3UCMD 304 command i~ iasued by the firmwaxe for the most slgnlficant word of the long operand. m e decimal unit 730 ~cans sach word recaiv0d on the cycle following the DUCMD 304 comm~nd whlch is marked by the ~CZ0 flag being ~et from the le~t ~ignific~nt word to most significant word, counting the nufflb~r of dig~ts to the right of, and includlng the most signi~ic~n.t digit. ~ is count is stored _ _ . . _ . _ . .. , . . . .... _ . . .

~S1~5~
~oz in the ~W~C regist~r 730-84, RLZCl regi~ter 730-96, and RIZC2 730-98. Tha outp~t ~f theqe registers is availabl~
to the ~1rmwaro ln re~pon~ to a DUCMD 311 "Put Operand Word Count lnto RDOD~ command.
E~ ective digit logic 730-81, Figure 7, examines the re3ul~nt operand word RC~U 4-35, receiv2d from the character unlt 730. The roqul~ant operand word was generated in the execution unit 714 and is the resul~ of the decimal numeric operation per~or~ed on operand 1 an~
op~r~nd 2.
ThR nega~d signal~ R~ 4-35 are a~plied to the inputs of NAN~ gate~ 81-2 ~hrough 81-16. Decimal digit 0 signals R~HU 4-7 are applied to th~ input of NAND gate 81-2.
Dacimal diglt 1 slgnal8 EFff~ rr are applied to the input of NAND gat~ 81-4. In a similar manner the decimal digit 2-7 signals ara applied to the inputs of NAND gates 81-6 through 81~
If tho input~. to. NAN~ gate 81-2 indicate that digit posltlon 0 ~ignal3. ~ ~7 indicates a digit which 2S no~
zero, thon the ~ output signal of NAND gate 81-2, at logical ONE, i~ a~pl~ed to the input of a NAND gate 81-42.
. The ou~put slgnal ED~-O at logical ONE indicates that the word contains eight 3~gnlficant digitq. The output signal DGZ0, at logical ZERO, is applied to the inputs of NAND
2S gate3 81-44, 81-46 and 81-48 thereby forcing the output signals EDCl-3 to logical ZERO.
If the di~it 0 ~ignal ~J ~=7 indicates a decimal zero, then th~ output o~ NAND gate 81-42 is di~abled and the output o~ NAND ~atu3 al-44, 81-46 and 81-48, which 30 indic~tes the position of the most ~ignificant digit of the oper~nd word, i3 enablod. Assume that the most significant digit 18 ln po3itlo~ 5 of the 8 position operand word po3itions 0 through 7. Th~refore the DGZ5 output of NAND
gate 81-12 is at log~ c~1 ZE~O and the DGZ 0-4 outputs of 35 NAND gate~ 81-2, 81-4, ~1-6, 81-8 and 81-10 are at l.ogical ONE .

~5~5 ~' ~ igit 5 signal, at logicai ZERO, is applied to the input of NAND gat~ 81~22 and 81-32. ~he outpllt signals 1: ZR56 and i5~7 at loglcal ONE are applied to the inputs of NAND gates 81-23, and 81-~0 resp2ctively. The other 5 inputs, ~ignals DZ~ 34 and DGZ4 at logical ONE are applied to the other inputs of NAND gate-~ 81-28 and 81-90 respectively.
The output signMl ~ at lo,gical ONE i5 applied to the lnput of a NAND g~t~ 81-36. The other input, signal DZR12 at logical ONE forc~s the ou~put signal DZRl-4 of NAND gate 8-34 to logical Z3RO, here~y forc~ng the output of N~ND
gate 81-44, ~ignal EDC-l to logical ZE~O. The output of NAND gate 81-36, 3ignal E~aÇ~ i at;logical ZE~O since the input ~ig~al DZR34 o~ N~ND gate 81-23 is at logical ONE.
This forcas th~ ou1æut signal ~I7~ to logical ONE forcing 15 the output of NAND ga~e 81-46, ~ignal EDC-2 to logical ONE.
The output o~ NAND gate 81-40 signal ~4/7 at logical ZERO i3 applied to the input of NAND gate 81-24. The output ~ignal ~ at loglcal ONE i~ applied to the inputs of a 20 NAND gatQ 31-30. The other input signal DGZ-2 at logical ONE foree~5 the output ~ignAl D~/7 to logical ZERO thereby forcing the output o~ a NAND gate 81-38, signal DZRl/7 to logic~l ONE. This orce~ the output of NAND gate 81-48, signal EDC-3 to logical ONE.
Sign~18 EDC~ t logical ZE~O, EDC-2 and EDC-3 at logical ONE, indic~t2 that there are 3 significant digits in thc oper~nd word.
The le~st 81gnificant word i9 received by the decimal unit 730 o~rer the RC~U 4-35 signal bu~ into the buffer 30 730-168. The negat~d output signalq RCHU 4-35 are applied to the effective dlglt logic 730-81. The effective digit logic 730-81 output 8ignal~ EDC 0-3 are applied to the input of th~ ZEDC swltd~ 730-8- . The ZEDC 1-3 output signals repre8ent a blnar~ cc~wtt of the signiicant digits in the 35 word starting ~rom th~ ~t 3ignificant digits and counting ", ~5~5 4 ~ .

to and including the low order digitq poqition.7. The ZEDC
O output signal at a logical ONE; indicating that the most signlflcant po~ition oi~ the word, po~ition zero, contains a decimal digit which 1S not a zero, i~ loaded into the AEDC
adder 730-96 ~tor ~h~ first word is received and the RWPC
regi3ter 730-84 is irlcrom~3nted by ONE each time a subsequent word is rcco~ved ~ro~ the executio~ unit 714 by control signals ~EN~WPC, lCNTUP-RWPC and ~LDRWPC being applied to the input terminals o~ the RWPC ragi~ter 730-84.
3001ean expre$sion~ for control signals ~LDRWPC which loads the RWPC rag~tar 7~0-84 and ~ENRWPC which enables the output of the ~gister are as follows:
[ENRWPC ~ ( ~D~ M1~05- + ~C:ZO) ~ FCRD DUCMD 314 . ~) [LD~WPC ~ ( (DUCMD 305 + PCZO) (FCRD ~ DUCMD 314 + DUC~ID 205~ ) The RWPC 0-3 output ignals are applied to one terminal of an ~EDC adder 730-86. The ZEDCO signal is appLied to another terminal ot~ the ~EDC adder 0--3 whose output is switched 20 th~ough th8 ZEDD ~witch 730~94 and stored in positions 0-3 of R~ZCl reglst~ 730-96 and RLZC2 ragister 730-98 whenever the receivad word ha~ a non zero decimal digit stored. The ZEDC 1-3 bln~ry output signals of the ZEDC switch 730-a~
which indlcate~ the nu~er of sigrlificant digite in the word 25 are atored in positlon8 4-6 of the RLZC1 register 730-96 and t:he ~ZC2 reglster ~30-98. The register outputs signals R~ZCl 0-6 and . Rt,2C2 0-6 ara applied to the ZLZC switch 730-76, whose ou~put 18 available to the firn~rare through position 3 af ~o ~ID ~witch 730-150. qhe RLZC1 and RLZC2 30 regists~rs bath ~toro the num~er of qignificant digits in operand 3. Whcn tho ftxst word i~ recaived from the axecu~lon unit 714, a~suming po~itlon û containq a decimal d~ glt, not z~ro, tho blnary qua~tity 8 i~ ~tored in the R~ZC1 ~nd RLZC2 rQgi8tors. The ZEI~CO signal input to the 35 ZEDC ~dder 730-84 i5 a loglcal ONE. When the ~acond word is received again assuming position O contains a decimal digit, then the ZECDO ~ignal input to the ZEDC adder ,~ at ~ O'i~
and the RWPC3 ~ignal lnput is at a one. This forces the ZEDC 0-3 output to a blnary 2 and the quantity binary 16 S i3 qtor~d in th~ RLZC1 and RLZC2 register~. As~uming the third word contain only 3 decimal digits with the most signi~c~nt dig~t i~ po~itlon 5' then the ZE~C 0-3 will store a blnary 011 ln the ~ZCl and RLZC2 registers 730-96 and 730-98 resp~ctively which will now have ~he quantity 19 5tored ln tha regi~ters, Tha RLZC1- 2 snd RL~C2-2 bits ~binary 16 bit) are again -~et ~inc~ tha A~DC 0~3 output is at binary 2. The RWPC
730-34 register wa~ incr~m~nted from binary ONE to binary TWO. Tho RRWC regi~t~r 730-88 stores the adjusted length of the ope~and wh~ch i8 calculated from length and scale S~ctor values, a~ d3signated by the descriptor. The RWPC
regi~ter 730-~4 stor~ the nlunber of words examined by the firmware ~s the result of the DUCMD 304 on a long operand In the long oper~nd ~tore operation it is necessary 20 to compare operand 3 which i~ the result of the operand 1 and opc~and 2 calcul~tions, as it exists internally in the ~xecution unit 714 wi th the operand 3 as it is to be stored in cache 7sn, and to do so with a simplified firmware procedure .
Initially, the fi~ rare i~sueq the DUCMD 303 "Store Operand Thru DU" command. This coTmnand initiates the ~ctual stoxe sequanca in the decimal unit 730. Unlike the short opernnd ~tore procodure, the firmware will not prepare a write address and~. 8end ~ write command to cache 750 until 30 it is permitted to do ~o by the decimal unit 730. The declmal ~tt 730 mak~a th$~ deci~ion based on the information stored ln tha R~WC r~g$ster 130-88, the RWPC register 730-84 and the position of the most Yigrlificant digit within the word when the operand l~ received by the decimal unit 730 35 from the execution unlt 714 ~s indicated by the output o f ~5t35 0~ ,~s ths ACP~ adder 730-50. As in the short operand ~ase the output of the ACPR addex 730-62 is ~tracted from ~he output of the AC~NB a~der 730-50 in the AC~SC adder 730-54 to generat~ the shl~t count which i8 stored in the RDSC
r~gl~ter 730-58.
It should bo not~d that ev~ry word qtored in cache 750 r~qulr~s 2 ~ir~wa~ cycles mlnimum for the store operation.
Th~ ~dds9~9 in cach~ 750 in which the operand word is written Ls sant to csche 750 on the first cycle and the data to cache 750 i~ 8ent o~ th~ second cycle. The firmware there-~ore i~ organ$zed ~n 2 ~t~p loops, the first step generates the Addro3~ and the write command and the nex~ step passes the data ~hrough S~om tha decimal unit 730 to cache 750.
~he p~ocs8s ~tart~ on the cycle the firmware sends the 15 DUCMD 303 com~and to t~n dacimal unit 730. The firmware examines the 9ta~t w~te ~ignal RRLTRV to the execution addre~ and branch c~r~ult~ 701-1, Figure 4, for logical ONE which indicstQs ~hat a writa command should be generated ~nd issued to t~ cach~ 750.
Th-3 FS~R~ ~lag 1~ s0t to indicate to the decimal unit 730 t~l~t the fi~are $~ sendLng write commands to cache 75~. If the ~tart wxlte line RR~T~D is at logical ZERO
then the }i~mwa~e control~ the loading of the RCHO register 720-l~ o~ the dlara~tor u~sit 720 with words from ~e 25 e~cution unit 714 unt~l the most ~igni~icar~t word is ~tored.
Thi~ i~ the ca9~ whel~e 1~ count in the RWPC regi3ter 730-84 would ~o gruater thcm tho count in tAe RRWC regi~ter 730-88.
The ~WPC regl8t~r 730 84 i~ decrem~nted each time a word 1~ pl~d in the RCHO regi~ter 720-lO ~til the count in the 30 RWPC ~gi~ter e~ count in the P~RWC rcgi3ter i f the RDSC r~gi~ter 730-58 lnd~cates a positive shift or until tho coun in thc RS~PC register Ls less than the coun~ in tho MWC rog~ster i~ DSC reglster indicates a negative shift. For a po~ltlv~ 9hi~t the mo~t ~ignificant word i~

~45~5~
, 1~7 ~

~tored in the RCH0 register 720-10. For a negative shift the mo~t significant word i8 ~tored in the F~P~ register 730-162 and tha sacond word is ~tor~d in the RC~0 register 720-10.
Fo~ the positlv~ shlft operation, the start write line R~LTRD is ~o~c~d to logical ONE and the firmware in~tiat~s ~ writa lnto cach~ 750 loop when the RRWC register ?30-88 count e~ual8 the RWPC ragister 730-86 count. This ~ets the FSND ~l~g which strobes the previous word stored in th~ RCHO regi9t~r 720-10 into the RPK register 730-162 and in~c~te~ to th~ fir~are to load the next word into the RC~O regist~r 720-10 ~rom the execution unit 714 by forcing the sond data 8 ign~l XREQRD to logical ONE.
Th~ ~oolQan expression3 for the start write ~ignal RRLTRD ~nd tho ~nd data s~gnal RREQRD for long operand store op~rations are ~8 follows:
DSEND DATA ~ (FCPCO ZT~SAO + ZTNSAO) DMSEQ
~ FSWRT ~M~D~N
DSTRTW~ ~ ~ ~a~ RDSCO + DMSDRGTE
~ISW5 + DUCMD 30 3 RRWCO
R~EQRD ~ PDUACT DSEND DATA DUCMD ~02 ~ ~
~LTRD ~ PDUACT DSTRT-WRT DUC~D 202 ~ ~UC~D-~0'4 2S DMSDRGTE ~ (RWPC 0-3 MINUS ~
~CO (~RWCl + RRWC2) RRWC3 RRWC~ M WC5 RRWC6 DMSEQ . ~R~PC 0--3 MINUS 1 ) t~ ( RRWCl ~ RRWC2 ) ~ RRWC 3 RRWC4 ~RWC5 RRWC6 DMSDRGT - (RWPC 0-3 MINUS 1 ) (~Wi~ t RRWCl + RRWC2 ) MWC 3 RRWC4 MWC5 RP~WC6 ) _ .

5~5 o~ ~
~ .
The boolean expressions for the count down of ~he RWPC
reglster 73Q-~4 are ~ ~ollows tCNTDWN-RQ~C ~ FR~ DU~MD 303 ~ g~ ~ FC~CO
+ ZTNS~..0) ~ P~K (FOP~rl'R +
.05 DUCMD 303 ~ DMSDRGTE) ~ ~F~ (FSWRT
D~SDRGT ~ (~;~-FCPCO ~ ZTNSAO) ~S~DOD ~ FD~TA-~V ~ DUCMD 203 ~ DUCMD 310 DUCMD 311 ~ DUCMD 309 + FRPK -DUCM~ 303 ~ FALT FSWR~
The decimal unlt 730 compares the RRWC 0-6 output signals with the RWPC 0-3 output signals in a comparator 730-90.
The comparator output 3ignals DMSE~, DMSDRGT and DMSDRGTE
condltion the regist~r and ~witch control 730-91 for generating the M LTRD and R~S~D slgnal~ and the various signals control-ling the ZPR ~w~t~h 730-160, the RPX register 730-162, the ZPKL swlt~h 730-166 and the ZPXR sw~tch 730-164. ~he sig-nals also condition the ~tatus flag contrGl logic 730-202 for set~lng the FSND, FSWRT, FMSDRGTE and FMS~Q flags as well a~ decrementlng th0 RRWC register 730-88 and the RWPC
register 730-84. When the number of words stored in the RRWC regi~ter 730-88 1~ greater than the number of words storQd ln th9 ~WPC r~g~ster 730-84 then the cache write flag FSWRT ~g sot but the FSND flag i8 not set. This results in the RDOD r~glster 73-154 o~tputting words containing all zeros to cacha 750 ~nd d~cr~ment~ng the RRWC register 730.
When the comparator 730-90 ln~icates an equal condition, the FS~D ~lag i8 sQt ~nd u~d~r firmwaro control the most signi-ficant wo~d is 3ent ~rcm the execution unit 71~ to the decimal nibu730 over tho ~C~U 4-35 lgnal bu~ thereby inputting tho buffer 730-168. ~ho bu~fer 730-16a output is applied to~the 0 position o~ tho ZP~ swltch 730-160. The ~o~
signiflc~t word is ~to~d in tho RPX reglster 730~162 from the ~ wltch 730-16~. Contxol logic, not ~hown, enables tho ZPKR switch i~ a daba word can be as~embled and sent to cache 750. In that .cas~, tha ZPXR 0-31 output signals are 5~5 ,~
. ~
applied to the ZDS shifter 730-156 and the word shifted by a number of digit po~ition~ equal to th~ binary value of the ZDSC 1-3 signal3. Zero3 are applied on the ZP~L 4-31 signal bus~ The ZDS 0-31 output ~ignal is switched through 5 positlon O of the Z~D switch 730-150 to position 0 of the ZSM~ switch 730-180 lf the operand comprises 4-bit characters.
If ths operand compri~s 9-bit'charac~ars then the ZDS 0 31 output signal is ~witched through position 0 of the zIa qwitch 730-lS0 to position 1 of the ZDOD qwitch 730-152 if th~ word is to b~ written in an odd address in cache 750 or to positlon 2 of the ZDOD switch if the word is to be written in an evan ~ddre~s in cache 750.
Po-qition O of the ZSMR switch expands the word containing 4-bit digits ~ro~ 32 bl~3 to 36 bits after which the word 15 is witch~d th~ough posltion 3 of the ZDOD switch 730-152 to the RDOD r~gi~tor 730-154.where it i~ stored and sent to cache 750 on th~ ~xt cycle.
Posltion 2 o~ tbc ZDOD switch 730-152 e~pands words of operands to be ~nado up of 9-bit diglts by expanding the 20 ZID 4-19 output 8ign~13 to.g~ner~te the 36-bit word by adting the ACSII ox EBCDXC zone characters. Position 1 of the ZDOD ~witch 730-152 expand~ the ZID 20-35 output signals to the 36-bit ZDOD 0 35 ~ignal bus. The ZDOD 0-35 output signal~ from position 2 o~ the ZDOD switch are s-tored in th~ ~DOD rogi~t~r 730-15~ and transferred to an even cache 7$0 ~ddress. Th~ position 1 outputs of the ZDOD switcn are transfered to odd ca~hQ 750 addrasse~.
In th2 cvent that th~ comparator 730-90 output indicates that th~ MWC 0-6 b~nary count of the RRWC regist`er 730-88 i~.le~s th~n tho RWPC 0-3 b~nary cou~t of the RWPC register 130-34 than dat~ words are neith~r received from the execution u~it 714 no~ s~nt to cache 750 by the decimal unit, ; and ths RWPC registe~ 730-88 coun~ down until the output of ths comparator 730 90 indicate3 that the RWPC 0-3 binary count equalQ the MWC 0-6 binary count. Thi sets the FMSEQ, ~5~4 and FSWRT rlags and the data words are clocked into the RDOD register 730-154 and transferred to cache 750.
Operand~ having 9-bit characters transfer 2 words to cache 750 for ev~y word received from the execution unit.
714 during normal operation. The word recei~ed from the exacution unit 714 ha~ up to eight decimal digits of 4-bits each and i8 exp~nded to 2 words, each containing up to 4 decimal diyite of 9oblts each. The FCPCO flag cycling on and o~f controls ths transferring of words to odd addresses and to even addrQ3se~ in cache 750.

~S~54 .

- ~r Cycl~ Dsl~ .
The proc~3sing of ~hort operands is spe2ded up by predicting, as the processing of the instruction is starting, the number of word~ sent from the decimal unit 730 ':o th2 S execution unit 714 and the number of cycles bet~een t.'ne time the first ra~d commar.d is sent to the cache 750 and the first data word ~8 eent to,the execu~ion unit 714.
The.number o~ wo~d~ and cyclas of delay are calculated in the declm~l unit 730 and sen~ed by the firmware in the execut$on control unit 701. The decimal unit 7 30 ou~put siynal~, PX-VCTR 0 3, Figure 4, are applied to th~ execution addras~ and branch circuit~ 701-l and cause the fir~are to-branch to a particular addxess in the execution control stora 701-4 which r~sults in the firmware executing a sub-routina to proce~s the operand. The particular subroutine salect2d i~ de~lgned to process t'ne exact number of words o~ tha opera~d with th~ exact number of cycles of delay thereby processin~ tha operand with minimum of number of microwords.
Tho calculatlon for the number of delay cycles is a ~unctlon of the typ~ of data, tha~ i~, whether ~he incoming oparand is mada up o~ 40bit or 9-bit charac~ers, thP
loc~t~on of the at ~lgnificant character in the operand coming from cache 750 and the location of the most signif-25 ic~nt digit in tho opar~nd being transferred to the e~cution unit 714. A~ an example, assume an 8-decimal digit operand made up o~ 9-bit characters with a leadirlg ~ign. ~130 as~u~ lel 3ign was in the third character position o~ the fisst word of th~ operand. The second word 30 f~om cache 750 contalna 4-decimal characters and the third word ~rom cache 7S0 cont~ins 4-decimal character . The dec~ mal unit 730 would not load any decimal digits ~lpon rscsivlng the first word since the first word only contained ~a ~ign. Four decimal digits were recei~ed from the second 35 word, still not enough to fLll t}se RDOD 730-154 register.

s~s~

.

Four decimal digits wo~e received from the third wo;.d and tha RDOD r~g~t~r wa~ loaded with 8-decimal digits.
mi~ load ~pexatlons taok 3 cycles to asse~ble and transfar th~ word to tha oxecutlon unit 714. The PK-VCTR
0-3 signals llnes would indicatc a one word transfer with a 2 cycl~ delay to th~ ~rmware. The firmware by using the info~mation indicating the number of words transferred and tho num~er of CyC1~8 0~ delay performs the control of transferring data word3 from one register to another on a specific cycle r~ther than to halt or loop waiting for the data word.
The delay~ nre a ~unction of the data type, 4-bit or 9-~it decimal characters as indicated by the condition of the output o~ th~ ZTNSA switch 730-36 and the ZTNSB
switch 730-34, Z~NSAO or ZTNS~O ~ignal~. The ACPNB adder 730-50 give~ a~ an output the digit position of the most significant dlgit o~ the word received from cache 750.
Th~ ~CPDF adder 730-52 give~ the difference in po~itioning ~etw~en the first charactQr po3ition for the high order 2~ digit in th~ fir~t word from cache 750 and the digit position of the most -~ignlficant digit as it is tran~ferred to the execution unit 714. ~ output of the ZCPA switch 730-44 signal ZCPAO id~nti~le~ the word from cache 750 as being from an odd or aYen wo~d address.
~he Boolean equatlon~ for the number of words and cycle d~lAy calc~lation~ are readily interpreted into f~nctional hardware by on~ of ordinary ~kill in the art and ar~ aB i~ollows:
PX-VCTR ~ ~ 0 PX-VCTR 1 ~ TDB0 PX-VCTR 2 ~ TD81 PK-VCTR 3 8 ~RWC6 i4 ~ .

TDa0 ~ [ (~ FDUACT ~1 + ZTNS~ FF~DP1) (ACPDF,0 ~ ACPDP,0 ZCPA~ ~ ACPDEl) ~
TDBl 8 [ (Z5NSA,0 P'DUACT ~ ~ ZTNSB0 FRDPl) (ACPDF0) + (~ FDUACT ~ + ~ FRDP1 ) S [ ~CPDF~ ~ ~) + (A~iii~0 ZCPA,0 (~ 2 ~3 +
~ ~ ACPNBl) + ACPDF0 ZCPA0 ACPDFl) ] ]
The P~-VCT~ 1 ~ignal forced to binary ONE indicates a 2 cycle d~lay. The PX-VCTR 2 signal forced to binary ONE
10 indicat~s a 1 cycle delRy. The PK-VC~R 3 signal forced to bln~y ZE~O ~ndi~to~ that 1 data word will be trans-farred to t~e ~xQcution unit 714 ~rom the decimal uulit. The PK-VCTR 3 slgnal ~o~ced to blnary ONE indicates that 2 d~ta wo~ds will be tra~erred to t~e execution unit 714.
For the PK-VCT~ 1 c~lculation the ZTNSA,~ FDUACT -FRDPl BQoloan expres~ion indicat~-~ a 9-bit operand 1 word from c~che 750. Tho ~ 0 FRDPl indicates a 9-bit oporand 2 word from c~ 50. The ACPDF~ ACPA~ expression indicate~ a left sh~ft throu~h the shifter 730-156 of the 20 word from an even cachQ 750 addres~. m e ACPDF0 ZCPA0 -Z~PDPq QXpr~sio~ ind$cate9 a le~t 3hift of from 1-3 decimal digit8 o~ a word from ~n odd cache 750 addre~.
~or the PK-VCTR 2 calculation ZTNSA0 FDUACT FRDPl ACPDF~ lndicat~s a 4-~it operand 1 word from cache 750 25 requiring a le~t 9hi~t through the ~hifter 730-156.
Z~NS80 ~ FRDPl ~ ~CPDFP lndicates a 4-bit operand 2 word.
requirlng a left shi~t. ZTNSA0 FDUACT FRDPl + ZTNSB~ -FRDPl indlcates a 9-blt operand 1 word arad a 9-bit op~orand 2 word.
-It4-ACPDFZ ~F~ + ~P~0 ~ indicates either a zero shift or a right ~hift of the word from the even cache ` address. ACPNB~ ACPN~ 2 ~ ACPNB3 indicates that tha high ord~r dacim~l digi~ is in po~ition 4 of the 4-bit character word or po~it~n zero,of the 9-bit character word ~rom odd cacha ~ddre3s. ACPDFl ACPNB0 ~
indicat~ that th~ h~gh order decimal digit received from cache 750 i~ in locatlons 1-3 and the shift count is less ~han 4 dlglts. ACPDF0 ~ ZCPk0 ACPD~l indicates a left -~hift of ~ro~t~r than 3 digit positions from the odd cache addrass word. Not~ that the ACPDFZ signals at binary ONE
indicates that the ~dd~r 730-52 is ~et a binary ZERO. For the PX-VCTR 3 calcul~t~on, ARWC6 indicates a one word transfer from th~ declmal unit 730 and the execution unit 714 wh~n at ~inary Z~O and a two word tran~fer when at binary ONE.

_ ~.

5~5~
7s Decimal Uhit 730 - ~i ur~ 3 - Rewrite O eration Operand 3 may ~ art and end in character positions withln the most signi~icant word and the least sisnific~..
word. It may be nece~ary to retain the information stored S in th2 most and ls~t significant words of operand 3 that are not part of oper~nd 3. In thiq case, the firmware initiates a DUC~D 306 "~oad Rewrite Data" command in the decimal unit 730 to load the most s~gnificant word into th~ REWR2 ~gist~r of regl3ter bank 730-177 through the ZDI 0-3S bus from cache 750, the RD~D register 130-158 and the ~b bu~far 73a-l76. The firmware initiates a second DUCMD 306 to load the least aignificant word in the REWR3 regl~ter of thn REWR 0-3 regiqter bank 730-177. When the firmware initiat~ a DUCMD 303 "Store Operand Through Decimsl Uni~ com~a~d ~he mo~t significant word appears on the ZID 0-35 s~gnal bus. Assuming 4-bit decimal character~ ~or the operrnd the RCP2 register of register b2~.k 730-42 store~ the sta~ting character po~ition of the operand 3. Sinc~ this is a d~ crlp or 3 operation the RCP2 position of gwit~h 730-44 is aolected and the ZCPA 0-3 output signal is applied to a ZRUMP swltch 730-148. Position l of the ZRUMP switch is activat~d and the ZRUMP 0-2 output signal i~ applled to an R~WU~ ahi~ter 730-149. The REWUM 0-7 output signdls ara spplied to control [lZSMR logic 730-142 ~n~ control ~2ZSMR 0-7 output signals select the digit positions of thc Z~MR ~witch that will be selected. For axample, for proca~81ng ~he most significant word of the 4-~lt digit ope~antp dlgit positions in position 0 of the ZSMR ~witch 730-180 would be ~elected for the operand digit data. The ~ign po~ition in po~ition 1 of the ZSMR switch 730-l80 would be s~leeted if the operand had a leading sign and the digit pc~itions to the left of the operand would be ~elected ln pos~tion 3 of the ZSMR switch for the rewrite data. l~e REWt~M 0-7 sign~l output of the shifter 730-149 35 i~ a ~ero ~or those ~iglt positions requiring write da~a.
The ZSMR 0-35 output bu~ i3 switchad through position 0 of the ZDOD ~witch 730-154 to ~he ~DOD register 730-154.

If the operand contains 9-~it decimal digits then the [lZSMR 0, 2, 4 and 6 logic 5Lgnal9 and [2ZSMR 0, 2, 4 and 6 logic signals a3:e ~pplied to the unpack ZDOD iogic 730-184.
Tho [12DOD 0-3 and 1~2~0D 0-3 output signals enable the 5 rewrlta and le~ding 8ign dlgit position~ of switch position 3 and the oper~nd d~cimal .digit positions of either position 1 or positlon 2 of the 8DOD switch 730-152.
During the load op~xation for a 2 descriptor operation the mo~t significnnt word of operand 2 which could contain 10 rewrite informatlon is writtQn into the R~WRO register of the regi~ter bank 730-177 and all ~ub3equent word~ are writt~n into ~he REW~l ragi3ter replacing the pxevious word.
Thl8 re~ult~ in the m~t significant word of operand 2 ~tored in the ~EWR0 r~glstex and the leaqt significant word 15 of oparand 2 sto~ed in th~ REWRl register. The loacling of ~e~o r~giqtors l~to the RDO~ register 73U-154 is as described supra.
The REWR registsr bank 730-177 is enabled by the control ~ignal lS~EW~. Tha boolean expression i3 [SREWR - tFDID +
20 FLDRE~RH) .
Control si~nal lWRREwRl is applied to terminal 1 and ~tatus fl~g FLDREWRH is applied to terminal 2 of the register select input termi~ls to select one of four registers ~EWR 0-3. Tha boolean expre sion control signal ~WRREWRl i3:
[WRREWRl ~ FOP2LD FOP2F + FLDREWRH FREWR
The output of r~gi~ter-~ REWR 0-3 is selected through tha ZEWR ~witch 730-178. Signal [lZEWR is applied to output qelect terminel 1 a~d tatu~ ~lag FREWR is applied to the output ~elect terminal 2 of 2EWR switch 730-178.
The boole~n expra~sion ~or control signal [lZEWR is:
. [lZEWR ~ (FREWR FR~WR2 FFOSD + FOP2S ~ FFOSD -~;~) .
~,, _ ~5~5 Dec~m~l ~
Two DUCMD 309 ~Put ~he Rounding Constant into RDOD"
commands are initidt~d ~y the firmware. For short operands *e rounding con~tant 1~ senl: to the execution unit 714 in response to tho ~ir~t DUCMD 309 if the constant is to be inss~ted in the loa~t slgnifican~ word. ~he rounding const~nt 19 sent to tha execution unit in response to the second DUCMD 309 if the con~tant iq to be inserted in the most signlficant word. For either case, a word of all zeros is sont to the ex~cution unit for the other DUCMD 309 comm4nd. The other rounding constant, binary 5, is added to tho posltion to the riqht of the scale factor pointer (declmal polnt). me rounding con~tant is stored in bit position~ 4-7 o~ swltch position 3 of he ZPK switch ?30-160.
The ATMP adder 730-30 subtracts a ONE from the operand 3 scalà factor ~to~od in the RSF2 register of register bank 730-4 and i~ appliod ~o the ATMP adder 730-20 through the ZASFB switch 73a-28. If the ATMP6 ou~pu~ signal is a ZE~O
then the rounding constant is applied to the least si~lificant word in response to the DUCMD 309 command. If the ATMP6 -output ~ign~l is a ON~ then the rounding constant is applied to the m~st aigni~icant word in response to the second DUCM`D 309 command.
Th8 ATMP 7-9 ou~put signal3 are inverted by inverter 730-147. The A~ 7-9 output sig.nals are selected by the ZDSC ~witch 732 and provide the binary shift count to the shifter 730-156.
The ZPKR switch 730-164 i-q enabled in response to the first DUCMD 309 comm~nd if the rounding character is added to the lQa~t signi~ic~nt word and enabled in re~pon~e to ~4~i~5 . . ~,g, the second DUCMD 3ng commDnd i f tha rounding ~harL:cter i~
~ed to th~ ~D8t signi~leant word. In either case the bin~ry 5 output fro~ po~ltion 3 of the 2PK 730-160 switch i~ tr&nsferred to th~ execution unit 714 through the ZPKR
-5 8wlt~h 730-164, thQ 2DS ~hifter 730-156, position 0 of the ZID ~wltch 730-150, position O'of ZDOD switch 730-152 and th2 ~DOD ~egist~r 730-154.
In the lonq operand ~tore operation the decimal unit 730 ro~pond~ to tha ~ir~t DUCMD 309 command with a pointer to tho word in ~csatchp~d to which the rounding constant i~ addod and ra3pond8 to the qecond DUCMD 309 command with the rounding conJtant. The ATMP 0-6 output signals whlch ind$cat~ ~he word to which the rounding constant is ~dded ~e aeleotQd through po~ition 3 of the ZLZC switch 730-76, position 3 of tha ZID switeh 730-156, position 0 of the 2DOD ~w~tch 730, the RDOD register 730-154 to the ax~cution unit 714. The rounding constan~ binary 5, is tran~ferred to the ~x~cution unit 714 d~ring the second DUCMD 309 op5ration a~ in the short operand above.
-~50~i~

~' ~59C
.
~8 each oporand i2 ~eceived by the decimal unit 730 during the load op~tion the sign character is exan~ned if it i~ not an ove~punched sign character. The decimal S unit 730 verif~e~ t~at it is a legal sign character.
An P~CPS 0-2 regi~ter 730-126 stores the character loc~tion within the word of the sign character. A ZCPS
switch 730-124 801ec1:~ the position of the si gn character.
The ZCPS switch position 0 identifies the leading sign position for 9 bi~ character opexand~. Switch position 1 identi~ies th~ l~ading si~TI position for 4-bit character operand~. Switch po~$tlon 2 identifies the trailing sign position for 9-bit dla~acter operands. Switch position.
identifies the ~rai~.ing sign po~ition for 4-bit operands.
rh~ RCFS 0-1 output ~ignal~ ~elect the position of a ZCH swit~h 730-170 that could contain the sign character.
No attempt is m~de to select the trailing or leading word of the oper~nd in ~e ZCH switch 730-170. An operand word rec~ d from cache 750 ov2r the ~ 0-35 signal bus is stored in the ~15 register 730-158 and is applied to the ZCH switch 730-170. ~e ZCH 1-8 output signal is applied to a ZCHL swltch 730-172 and to sign extraction logic 730-174~ Position.l o~ the ZCHL ~witch is selected for 9-bit operands and 4 ~it operand~ having an odd character pointer.
The sign extraction logic 730-174 selects either the Qign charactQr rom the trailing word or from the leading word. If t~e s~gn cha~acter is coded a~ an illegal character then a SET I~EGAL logic signal forces a fault indication ~or the ~oftware. If the ~ign c~aracter is coded as a corsect sign then the SE~ SIGN logic ~ignal sets an indication for the software. The ZCH 1-8 output signals to the sign extsaction logic indicate 8-bit E!3CDIC sign charactar~. The 2CH 1~8 output 9ignals to the Z('HL switch _ .

5~S~

7~

indica~e 4-bit ~ign characters in ~he lower half of the 9-bit character (bit po~ition 4-8) position :~r ~-bit char8cter op~rand~. For 4-bit operand words, even pointers indicate the 1Q~t 4-bit~ tbit positions 1-4) and odd pointers indicate the right 4-~lts t~it positions 5-8).
Control ign~ls ~lZCPS and [2ZCPS are applied to the terminsl8 1 and 2 s~lQct inpu~s of ZCPS ~witch 730-124.
The boole~n expr~8sions are:
[lZCPS ~ (ZTNSA0 FDUACT FRDPl + ZTNSB0 ~ FRDPl) ~2ZCPS - ~NSAl ~TNSA2 FDUACT ~g~FI +
ZTNSBl ~ ZTNSB~ FRDPl) The RCPS r~gi~tor i~ enabled by a ~$RCPS control signal whose boole~n expre~sion i~:
[SRCPS ~ (FDUACT ~PI) + SFOP2LD) s~s~

Opcrands m~da up oi words having 9-bit chaxa~srs msy have ~Qparst~ 8~gn~ ln either a leading or trailing character po~it$on or tha operand may have a sign included in th~ decimal dlgit çode ln a ~ingle character position.
mi8 roqui~e~ th~t a ~orraction be made to ~he decimal digit to includ~ ~h~ ov~rpunched sign. Assume that operand 1 requires an ouerpun~hed sign correction. An ROPl 'ogic signal i~ ~ent fro~ eh~ control store 704-2 to the decode 10 logic 730-3a. I~ the ZT~SA 0-2 output signal from the RTNS2 re~i~ter of r~gistor bank 730-32 ~nd the ZTNSA switch 730-36 i~ coded to a blnary 000 or 011 indicating 9-~it characters w~ th l~adlng ign or trailing sign, a Dl~QOVP
loglc Jlgnal output o~ decode lo~ic 730-38 i~ forced high.
The DlE~OVP loglc 8ignal 8el~ct~ the 1 position of a ZSSC
switch 730-1~8 ~or a t~ail$n~ slgn operand. The 0 position of the ZSSC switch 1e 3~1ected for the leading sign. The RLMP 4-6 9iqnal3 ara coded to point to the character position - of the loading ~ign ~n~ ~he R~MP 4-6 ~ignaLs are coded to ~0 point to the charact~ ~osition of the trailing sign.
. Th~ ZSSC 0-2 shi~t count signal~ are applied to a shi~tar 730-145 to ~h~t a D~IT$ logic signal the number of bit3 specifi~d by ~ha ZSSC 0-2 count. The DBITT loqic slgnal i3 ~orced to ~ Z~O ~or the overpunched ~ign operations during tho crclo ln whlch the m~st significant word or the lea~t sign$~1cant wo~d 1~ Eead f~om cache 750 for the leading ~lgn or tralllng ~gn correction respectively. The shifter 730-145 output 3ignal~ i~RD~M 0 7 ar~ pplied to the ZID
switch cont~ol loyic 730-188 ~o select po~ition 2 of the ZID
switch for ~he chaxact~r po~ition that i~ indicated by the one ~ignal of tha ~ 0-7 ~ign~ls that i5 at a ZERO
which point~ to tho ov~rpunched sign po~ition.

~s~

The RSGN register 730-134 is loaded with the corrected overpunched sign character for operand 1 under firmware control. The REXP register 730-138 is loaded with the corrected overpunched sign character for operand 2 under firmware control. A ZCRDG switch 730-136 selects the RSGN
5-8 output signals for the operand 1 overpunched sign correction character. The ZCRDG 0-3 signals are inverted by an inverter 730-186 and are applied to position 2 of the ZID switch 730-150. When the word to which the corrected overpunched sign is added is received ~rom cache 750 and is switched through the decimal unit 730 to be stored in the RDOD register 730-154. The character in the sign position is replaced by the ZCRDG 0-3 corrected overpunched sign character.
The boolean expression for the DBITT signal is:
DBITT - (FOPlLD ~ DlEQOVP ~ (ZTNSAl ~ FFD0 ZTNSA(l) ~ DMPEQ) + FOP2~D ~ D2EQOVP
(ZTNSBl . FFD0 ~ ZTNSA(l) DMPEQ)) where DMPEQ is at logical ONE when the contents of the RI~IP
register 730-102 equals the contents of the RTMP register 730-100.
The above equation indicates that the DBITT signal is set to logical ZERO when operand 1 or oPerand 2 requires an overpunched sign correction during the load operation.
ZTNSAl FFD0 indicates a leading overpunched sign and ZTNSAl DMPEQ indicates a trailing overpunched sign.
DlEQOVP = (DBITX ROPl ZTNSA0) D2EQOVP = (DBITZ ROPl ZTNSB0) During the store operation the sign character is placed in the RSGN register 730-134 and inserted in the operand word through position 1 of the ZSMR switch 730-180 as previously described.

5~54 -~ e ~lr~ase 1~31tiat~J a DUCMD 203 Load STC Maqk into ~DOD conanan~l ~u~lng the 3tore Character in-Accumulator and Quotlant R~qls~x In~tructions (STCA and STCQ). The dec~m~l unit 730 re~l~s the RC~U 30-35 output signals from the character u~it 720 which are applied to posi~ion 1 of the ZID ~witch 730-150 through the buffer 730-16 8 . Each of the RC~IU 30-35 output sigr~als at a ONE results in ~he corresponding 6 bit~ o~ poqition 1 of the ZID switch 730-150 belng orced to a ONE. These groups of 6 bits are stored in thQ RDOD ragi~ter 730-154 through ~he ZDOD switch 730-152.

-~*

Flgur~a 4 shows t~l~ rela~lon~hi~ between t~e decimal unit 7~0 hardwa~:~ and the ~irnwax~ in the execution control 3tore 701-2. Th~ ex~¢ut~on address and branch circuits 701~ nd the c:on~l stors addres~ locations ZECSA 0-12 5 to the elxacution ~ont~ tora 701-2. The microword at that addro~ location ~8 re d out and bit posi~ions RSCR
88, 39, 94-97 ir~pu~ a dec:imal unit 730 decode logic 730-204 - which con~l~t ~f coJ~ven~ional decode logic circuitry .
Table 1 ~how~ the RSCP~ 88, 89, 94-97 bit configurations for 0 the reBpect~ DU~D 200-206, 300-315 co~nands.
ThQ DUC~ID 2û0-20C 300-315 con~nands input a status flag control logic 730-202. ThiR unit is made up of conventional :~lop~ sQt and reset in a conventional manner.
5~o I cycl~ col~t~ol state circuits 704-102 describ~d in the aforementio3-0d ~pplication serial nulTber 853,944 genesat~ the F~Qa ~POP HOL~N 2nd ~he lHOL~E signals to time the decimal un~t 730 to the pipeline operations of the contsol unit 704O Th~s~ signals also input the status flag control loglc 730-202 whos~ output input~ a decimal unit control logic ?30-200 ~ w311 a3 inpu~ting the sta~u~ flag control logi~ 730-202 and the dec~mal unit control logic 73û-20û. Al~o appi~ed to the d~cimal unit control logic 730-20~ ~ra the DUC~D outputs of the decimal unit decode logic 730-2û4 and ~h~ d~8criptor information received from control unit 70~-1 o~r 9~gnal lines RSIR 21-35 and ASFA 33-36 i~ tho rag~stors shown in Figure 3.
Op~r~nd~ stored ln csche 75û are tran-~ferred to the operand pro~o~ g.unit 730-206 a ~ord at a time over ~ignal linea 2S~ ` 0-35 . Th~ op~rand proc~s~ing unit 730-206 is con-dltlon~d by th3 do8criptor infoxmatlon, the status flag~ignsl9 and th~ r~gi~tar and 8witch control ~ignal~, rec~iving tho oporan~ word ~rom cache 750 to ~trip non-operand ~5~5~

and non-decImal digit characters from the word, convexting the word into 4-bit decimal digits, aligning the four 4-bit decimal digits into words of up to eight 4-bit decimal digits and transferring the completed word to the execution unit 714 over signal lines RDOD 0-35. outputting the logic 730-200 unit are the PK-VCTR 0-3 signals and the RRLTRD, R~EQRD, ADSZ and ZAMO conditional branch signals which generate branch addresses in the execution address and branch circuits 701-1.
A clock signal times the relationships between the logic units of Figure 4.
Figure 4 shows the flow of logic through tne system.
Where the portions of the logic blocks of Figure 4 rel2te to the inventions, they are shown in further detall in Figure 3.

51~59 12~
_ffl~

Figure 5 show~ two typical in~tructions processed through tha decimal Ulsit 730. The AD2D instruction -add u~ing two decimal operands, add~ the operand from the addres-~ location and in ~he format defined by descriptor 1 to ~he operand ~rom the address location and in the format defined by d~criptor 2 asld places the re~ulting operand in the` format and addro3~ loca~ion dafined by de~criptor 2.
The AD3D ln~t~uetlon~ - add using 3 decimal operands add~ tho operand from the address Location and in t:he lo formnt defln~d by d~cript~r 1 to the operand from ~he addren~ loc~tion ~nd in the format defined by descriptor 2 and pl~ce~ the resulting operand in the format and address locatlo~s de~in~d by descriptor 3. The instruction word is mad~. up of 36 blt positions 00-35.
Th~ instruetlon ~orm~t includes a P bit defining E3CDIC data wh~n a ZE~O, and ASCll data when a ONE.
Fi~ld8 MFl, MF2 and MF3 describe the address modifications to ba par~orm~d on de8criptor 1, 2 and 3 respectively.
~he T bit enable~ tha truncatlon fault.
The ~D bit ~ble~ the rounding operation.
The OP CODE sp~ci~ies the operation to be performed.
In Figure 5 thc OP CODE 202-1 specifies the AD2D instruction and O~ CODE 222-1 spe~l~les the AD3D in~txuction.
I i~ tho lntQrrup~ inhiblt bit.
For th~ dasc~ptor ~rm~ts, Yl, Y2 and Y3 are the main n~amory word location~ o~ the ~st significant character o~
the op~rand sp~cl~d ~y dascrlptors 1, 2 and 3 r~pectively.
Tha O/E bit ld~ntifies the m~in mem!)ry word addr~s~ as belng eithar an odd ~ddr~ss or an even address.
CNl, CN2 and, CN3 are codeY that define the position of the moot aignif~c~t charactex within the main memory word o~ tho op~and ~p~ci~iod by descriptor~ 1, 2 and 3 respQctlv~ly. Code~ dQpend on the data type a~ 3hown b~low:
Codes Character Numbers 35 9 blt chaxacter3 000 0 1~0 2 .~450S~

~r--Codes Character Number~
4 bi~ character~ O O O O

10 TNl, TN2 and TN3 are code~ that dafine the numeric data typo for descriptor~ 1, 2 and 3 r~sp~ctively. A ZERO
speclfle~ 9-bit data ~nd a ONE specif ie~ 4-bit data .
Tho Sl, S2 an~ S3 fle~ds identify the sign and decimal type o~ dc~c~i~tor 1, 2 and 3 resp~ctlvely.
UnP~ck~d D~ta Packed Data TNSl ~ ~ie~
s s ~0 LS, OVP, s~aled ~0 ~loating point, LS
01 LS, ~c~led 01 LS scaled 10 TS, scaled 10 TS scaled ll TS, OVP 9 ~cal~d ll No qign , scaled ~S ~ L~ading TS ~ Tra~ l~ng S$gn OVP ~ Overpunched Sign S~l, 5~2 and SF3 ~p~cl~y the ~cale ~actors of descriptors l, 2 ~nd 3 ra~pectiv~ly. The declmal point i~ located aft~r the l~Jt slgn~loant digit. A positive scale factor mov~ the d~cim~l po~t that m~ny po~itlon~ to the right.
A n~gatlva ~c~le ~acto~ mo~es th~ decimal point that many po~itlon3 to tho l~t.
Nl, N2 ~nd N3 ~r~ tha numbor of characters in the operand dofined by t~crlptors 1, 2 and 3 respectively, Nl, N2 ~nd N3 may b~ 4-blt code~ which specify registers that contains the length of the ~espective operand. However, for descsl~ng th~ invontlon Nl, N2 and N3 are the number of 35 charactsrq in the oporand.

~ s~

Decimal Unlt 730 ~ - or 0ranch Data Referring ~o Flgtlre 3, the d~cimal unit control logic 730-20 g~ner~te~ control signals [lPKVCTR, [2PKVCTF~
and ~4PKVC~ in re ponse to decimal unit 730 D~CMD co~mand 5 signals as descri~ad qupra. The vector branch logic 730-15 haR applied to lt ~ignal~ indicative of the charac~eristics of the operand. The output qlgnal~ of decode logic 730-38 and 730-40 which are d~cribed infra define the oparand as a floatlng polnt or overpunched ~ign and as a scaled operand lf made up o~ 4-~it or 9-~it decim~l charactexs. The ZTNS~l and Z~NS~l ~ign~ls lndic~te an operand with a trailing sign if at loglcal ON~ ~nd an operand with a leading sign if a logic~l ZERO. The AINS 3-5 and the Al,NDA 0 3 and the ALNDB 0-3 31gnal~ ld~ntify the operand as having an adjusted length of greatQr.than 63 decimal digits or a length of less than or equal to 63 decimal digits. The detailed logic is shown in Figure 8.
The,vo~tor bran~h logic 730-15 output signals PK-VCTR
0-3 arc applied to th~ oxecution addre~s and branch circuits 701-1 in r~ponsa to tha liPXVCTR, [2PRVCTR and ~4PKVCT~
control signal~ to lndlcste to the execution control store 701-2, Figur~ 1, the next mlcroword to be processed by the 9y8tem-~ s~

I2~

~ eferring to Figure 8, a PK~VCT~ ~witch 15-72 a-d gen~rates v~ctor branch ~ignal PX VCTR 0-3 ln response to microword signals Whlch are applied to the decimal unit 730. The microwo~d ~ign~ls generate DUCMD command ~ignals, S which when combined w~th Rtatus fl~g signal~ generate conl rol slgnals llPXVC~ , t2P}CVC~P~ and ~4PKVCTF~. These control signal~ ~8 ~ppli~d to the 1, 2 and 4 input select termlnals of ~wltch 15-72 and select 1 of 8 input signals from each of 4 sQctions of the ~witch 15-72 a-d.
Durlng the proc~sing of non-decimal numeric instructions the doclmal unlt 730 ~ lnoperat~ v~ thereby activating ~nput termln~l 0 of 3witch 15-72 a-d.
Th~ typ~ length vsctor signals are applied to input tenninal 1. o~ ~wlteh 15-72 a-d. rhe ~ ~igrlal is applied 15 to input termlnRl 1 of swltch 15-72 a~ If th~ ALNS add~r 730-24 lndicate~ the ~d~u~ted length of the operand as greater th~n or equal to b$~ary 16 then one or more of the input signal~ A~N5 3-5 to AND/NAND gates 15-32, 15-34 and 15-36 ro8p~ct~ y is ~t logic~l ONE. ~ne or more of the 20 output ~ al~ at loglc~l ZERO is applled to ~che inputs o ~ AND/NAP~D gata 15-3~ . The output sig~al ALNSGTE 16 is applied ~o the l~put o~ an AND~NAND gate 1S-50. If thi~
is not a d~almal mulkiply/divide in~truction then the output signal ~5D~ is orced to logical ZE~O. This signal~
25 applied to tho inpu1: o~ an AND~NAND gate 15-74 forces the ~F ou~?u~ L to logical ZERO. Sigrlal~ C~Al, 3~, A~ ~nd ~i= are ~ppli~d to the inputs o~
AND/NAND g~tos lS-40, 15-42, 15-44 and 15-46 re~pectively.
Logical ONE 18 ~ppll~d to ~he ot~er input terminals. The output ~$gn~1~ o~ ~ND/NAND gates 15-40 and 15-42 are applied to th~ lnputs o~ an ~ND/NAND g~te L5-52 and the output signals o~ AND~N~ND ga~e~ 15-44 and 15-46 are applied to the nput9 o~ an AND/NAND gate 15-54. ~he output signals and ~ n~F~r~ at logical ONE indicate the .

5~35~

1~

length of operand~ 1 and 2 are le~ than 16 declmal digits.
I f the op~rands are not floating point operand~ and the adjusted langth including scale fac.tor adjustment are less thsn 16 docimal dl~lt~ then signal DLONG, the output of AND/NAND gate 15-74, at logical ONE indicates that both opcrand~ ~r~ proc~ d as sho~t oper~ds. The DLON~
3ignal i~ appLiad to the input o an AND/NAND gate 15-56.
The output 8ignal ~3~ , at logical ONE, indicates that the op~rand belng p~oc~s~ed i~ a long operand. Signal ~ i~ appli~ to the othe~ input of AND/NAND gate 15-56 and when at logical ONE indicate~ that neither operand 1 nor op~ran~ 2 ha~ an overpunched ~ign character which i~ the r~qu~ t for a short operand.
The DSHORT slgn~l at lcgical ONE indicating a short opesand i~ applied to th3 input o~ a AND/NAND gate 15-58.
Signal ZT~SA0 at loglcal ONE indicating a 9-bit per character operand i8 applied to the other input of NAND
gat~ 15-58. The output signaL D~O~T 9 at logical ZERO
is applled to aR lnput of ~n AND/NAND gate 15-62. The 20 output ~ignal DI~GOP~8T 9 at los~ical ONE is applied to the lnput t~rminal 1 of switch 15 72 ~ indicating a short 9-bit per character op~rand. ~ogical ZE~O i~ applied to input tarm~nal 1 of switeho~ 15-72 c and d.
Sig~al~ TDB0 and ~DE~l ars applied to input terminals 25 2 and 3 of switch. 15-72 b an~ 15-72 c re~pectively. The bool~ expre8910n~ describ~d supra and indicate the nun~ar o~ cycl~3 o~ d~lay batwe~n the cycle on which the read roqu~t i~ OX cach~ 750 and a complete word is receiv~d by ~ ~xocution unit '114. 'rhe ARWC adder 730-60 30 signal A~WC 6 18 appl~od to inpu terminal~ 2 a~d 3 of switch 15-72 d and $ndicates a one word operand if at logical ZERO and a two ~ord operand i f at logi cal ONE .
Input termlnal~ ~ and 6 of switch 15-72 a-d are selected for the dQscriptor 1 ~rector and ~tore vector operations, .

~5~S~

~ .

re~pecti~ely. Signal ROP 1 from control store 704-2 at loqical ONE indicating an overpunched sign operand is applied to an inpu~ of an AND/NAND gate 15-2. The ZTNSA0 signal indicating a 9-bit per character operand when at logical S ONE, is applied to th~ other input of AND/NAND gate 15-2.
Either input at logic~l Z~RO forces the signal Dl~EW 9 whlch i~ ~pplled to an input of an AND~NAND gate 15-14, to logical ONE. S~g~al~ ~TN~A1 and ~ , at logical ONE, are applied to the other inputs of AND/NAND gate 15-14.
Output slqnal ~ F at logical ZERO, indicating a floating .
point ope~&nd, is ~pplled to the input of an AND~NAND gate 15-64. . The output 3ignal DlFLPORTSO at logical ONE is forcod to logical ONE indicating a floating point operand.
If signals ~lOP-l and ~ ~re at logical ONE, the DlN~w9 signal output o~ AND/NAND gate 15-2 is at logical ONE. If signal ~r~ is at logical ONE then the output signal ~ o~ an AND~NA~D gate 15-Z2 is at logical ZERO.
This force~ the output, signal D12EQOVP, of an AND/NAND gate 15-30 to logical ON~. If ~ignal ZTNSAl is at logical ONE
indic~ting a tr~iling sign then the output signal Dl EQTSO
of a NAND ~ate lS-26 at logical 2ERO forces the DlFLPORTSo signal output o~ AND/NAND gate 15-64 to logical ONE.
Signal DlF~PO~SO at logic~l ONE ~9 applied to input terminal3 4 and 6 o~ ~witCh 15-72 b indicating a floating point or ov~rpunched trailing sign opersnd.
Signal DlEQOVP, th~ output of AND/NAND gate 15-22 is applied to lnput termln~l3 4 and 6 of switch 15-~2 a ind~cating an overpuY~ d sign operarld.
Slgnal ~ i~ at logical ONE if signals ZTNSAl and 30 ZTNSA2 at logical ONE ~re applied to an AND/NAND gate 15-4 indicatlng an operand with no sign or an overpunched trailing slgn or 8iqnzll8 Z'r/N~, ~i3~ and 2TNSA~ are applied to an AND/NAND gat~ 15-5 lndicating a 9-bit per character floating point or overpunched leading sign operand. Output _ s~

I~Z

qignal ~ of a~ AND~NAND gate 15-6 at logical ZERO
forces ~ignal D3~, tha output of AND/NAND gata 15-16 to logic~l ONE.
Lo~ical ZE~O~ ~r~ selected rom terminals 4 and 6 of qwitche~ 15-72 c and d. The firmware generates a result equals 2ero and an overflow check during the store vector operation. The d~scr~ptox 2 vector Qelects input terminal 5 of switch 1S-72 a-d. Signal D2EQOVP is applied to terminal 5 of switch 15 72 a and when at logical ONE
in~icateq an operand wlth an overpunched sign. The D2EQOVP
signal i9 generatsd in a Rimilar manner as the DlEQOVP
sign~1 whlch indicates an operand 1 with an overpunched sign.
Signal D~LPORTSO ~enerated in a Qimilar manner as signal DlFLPOR~SO th~ough AND/NAND gates 15-28 and 15-66 and is applied to terminal 5 of ~witch 17-72 ~ indicating a flo~ting point operand er an operand with an overpunched trailing 8~
Swltch 15-72 c, d input ~erminal-q 5 are at logical ZERO.
Th2 long input vector ~elect~ input terminal 7 of qwitch 15-72 a-d. Signals DlEQFLP and D2EQ~LP are applied to the input~ o~ an AND/NAND gate 15-48. The output slgnal ~ is appli~d to the input~ of AND/NAND gates 1S-60 and 15-70 and when ~t logical ZERO, indicating a floating point operand, forco~ 8$gnal3 D12FLPOREL and D12FLPOROVP
to logical ONE. The input termtnal 7 of switch 15-72 a and 15-72 b at logl~l ONE in~icate~ to the firmware to execute the d~sc~iptor 1 and de~criptor 2 vector~
I~ s~gnal ~ is at logical ONE indic~ting ~calod oporands, th~n ~ig~l A~NS~E63 at logical ZERO
indic~ting ~ longth of 1~8 than or equal to 63 decimal digit3 is applisd to ~he lnput of AND/NAND gates 15-60 and 15-68. Thn Output ~ignals D12FLPOREL at logical ONE

45~5~
~_ f . . ,33, _~3 ". ~7--,~ ' lndlc~t~ both op~rand8 having a length of lesR than or ec~ual to 6 3 deci~l d~ . Signal D12EQOVl? i~ applied to the~ other input og AND~NAND gate 15-6a~ The outp.ut signal Dl2OVP~63 at loglcal ZE~O is applied to the input of AND~
5 NAND gato 15-~70.. ` 'rh~ output ign81 D12PLPORO~IP at logical ONE ind$cAto~ thst both op~rarlds ~r~ scaled with an overpunchod ~qs~ and tho l~ngth~ are 1~9 than or equal to

6~ tacl~l char~c~Drs.
Sign~l AI.NSr,~6 3 at logical ZE~O is generated as the lû output o~ ND/NAND.g~tQ 15-B. Th~ input signal ALNS3 at loglc~l .ON2: lndlcalt~ ~ langth o ~ grsa~er than 6 3 decimal digits. ~mv i~ ~ loglcal ONE since thi~ is not a mult~ ply/divida op~tion. iiI~a~F i~ at logical ONE
since n~$~r operand ~ a ~loatlng polnt oper~nd.

____ .

Claims (66)

1. A data processing system comprising:
a cache memory for storing operands and instructions, each instruction including an operation code portion and also including descriptor information for describing characteristics of said operands;
an execution control unit for storing microwords, said data processing system being responsive to said micro-words for executing operations specified by said operation code portion of said instructions;
a control unit coupled to said cache and to said execution control unit, said cache and said control unit being responsive to said microwords for transferring one of said instructions and said descriptor information specifying a decimal numeric operation to said control unit from said cache, said execution control unit being responsive to said microwords for transferring said operation code portion of said one of said instructions to said execution control unit, said execution control unit being responsive to said operation code portion of said instruction for selecting a series of said microwords, said data processing system being responsive to said series of said microwords for executing said decimal numeric operation;
a decimal unit coupled to said control unit and said cache, said decimal unit storing signals indicative of said descriptor information in response to said series of said microwords, said descriptor information signals conditioning said decimal unit in advance of receiving said operands to align said operands when said operands are transferred to aid decimal unit from said cache; and an execution unit coupled to said decimal unit for receiving said aligned operands from said decimal unit in response to said series of microwords and performing said decimal arithmetic operations.

2. The system of claim 1 wherein said decimal unit comprises:
decimal unit control means coupled to said control unit and responsive to control state signals for storing said descriptor signals in said decimal unit, said decimal unit control means including adder means responsive to said descriptor signals for generating register and switch control signals; and operand processing means coupled to said cache and said execution unit and responsive to said series of said microwords for receiving said operands from said cache, and responsive to said register and switch control signals for aligning said operands for transfer to said execution unit.

3. The system of claim 2 wherein said decimal unit control means comprises:
decode means coupled to said execution control unit, and responsive to said plurality of selected signals from said microwords, for generating a plurality of command signals;
status means coupled to said decode means, and responsive to said plurality of command signals, said status means being further coupled to said control unit, and responsive to a plurality of control state signals, for generating a plurality of status flag signals; and control means coupled to said control unit, said status means and said decode means, and responsive to said plurality of control state signals, said descriptor signals, said plurality of status flag signals and said plurality of command signals, for generating said register and switch control signals, said control means being further coupled to said status means, for generating said plurality of status flag signals.

4. The system of claim 3 wherein said control means comprises:
storage means coupled to said control unit and responsive to said plurality of control state signals for storing descriptor signals indicative of said descriptor information; and adder means coupled to said storage means and responsive to said status flag signals and said descriptor signals, for generating and storing, receive count signals indicative of the number of words of said operands to be received by said decimal unit from said cache, send count signals indicative of the number of words to be transferred to said execution unit by said decimal unit, and for generating and storing shift count signals indicative of the number of decimal digits said operands are to be shifted in said decimal unit.

5. The system of claim 4 wherein said descriptor information for describing characteristics of said operands includes a first descriptor for describing a first operand and a second descriptor for describing a second operand, said first and second operands being aligned by said decimal unit for transfer to said execution unit, said execution unit being responsive to said series of said microwords for executing said decimal numeric operation using said first and second operands;
wherein said descriptor information includes signals representative of a scale factor for indicating the position of the decimal point of said operand, signals representative of a length of said operand to indicate the number of decimal characters in said operand, signals representative of a character pointer position to indicate the position within a word of the most significant character of said operand and whether said word has an odd address or an even address, and signals representative of the decimal type of said decimal characters of said operands to indicate the number of bits contained in said decimal characters received from said cache, the location of a sign character and whether said operand is a floating point or scaled operand.

6. The system of claim 5 wherein said storage means include a first scale factor storage means for storing signals representative of said scale factor of said first operand and a second scale factor storage means for storing signals representative of said scale factor of said second operand, signals representative of said first and second scale factors being received from said control unit in response to said plurality of control state signals.

7. The system of claim 6 wherein said adder means includes scale factor adder means coupled to said first and second scale factor storage means for calculating a scale factor difference.

8. The system of claim 5 wherein said storage means further includes a first length storage means for storing signal representative of said length of said first operand and a second length storage means for storing signals representative of said length of said second operand, said signals representative of said first and second lengths being received from said control unit in response to said plurality of control state signals; and said storage means further including a first decimal type storage means for storing signals representative of said decimal type of said first operand and a second decimal type storage means for storing signals representative of said decimal type of said second operand, said signals representative of said first and second decimal types being received from said control unit in response to said plurality of control state signals.

9. The system of claim a wherein said adder means further includes a first operand adjusted length adder means and a second operand adjusted length adder means, said first operand adjusted length adder means being coupled to said first length storage means and to said first decimal type storage means for calculating a first operand adjusted length; and said second adjusted length adder means being coupled to said second length storage means and to said second decimal type storage means for calculating a second operand adjusted length, said first and said second operand adjusted length indicating the number of decimal digits in said first operand and said second operand respectively.

10. The system of claim 9 wherein said adder means further includes a scale factor switching means coupled to said scale factor adder means and responsive to a signal from said scale factor adder means for indicating the operand with the larger scale factor.

11. The system of claim 10 wherein said adder means further includes length scale factor adder means coupled to said scale factor switching means and to said scale factor adder means for calculating the adjusted length of said operand with the larger scale factor.

12. The system of claim 11 wherein said adder means further includes an adjusted length switching means coupled to said length scale factor adder means, said first operand adjusted length adder means, and to said second operand adjusted length adder means, for selecting said operand adjusted length;
said adjusted length switching means selecting said first operand adjusted length from said length scale factor adder means and said second operand adjusted length from said second operand adjusted length adder means if said first operand has the larger scale factor, and said adjusted length switching means selecting said second operand adjusted length from said length scale factor adder means and said first operand adjusted length from said first operand adjusted length adder means if said second operand has the larger scale factor.

13. The system of claim 12 wherein said adder means further includes send word count adder means coupled to said adjusted length switching means for calculating the number of words of said operand sent from said decimal unit to said execution unit.

14. The system of claim 13 wherein said adder means further includes send word count storage means coupled to said send word count adder means for storing signals representative of the number of words of said operand to be sent from said decimal unit to said execution unit.

15. The system of claim 14 wherein said storage means includes a first character pointer storage means for storing signals representative of said character pointer position of said first operand and a second character pointer storage means for storing signals representative of said character pointer position of said second operand, signals representative of said first and second character pointer positions being received from said control unit in response to said control state signals.

16. The system of claim 15 wherein said adder means further includes character pointer word count adder means coupled to said first character pointer storage means, said first length storage means and to said first decimal type storage means, for calculating the number of words of said first operand received by said decimal unit from said cache, and coupled to said second character pointer means, said second length storage means and to said second decimal type storage means for calculating the number of words of said second operand received by said decimal unit from said cache.

17. The system of claim 16 wherein said adder means further includes receive word count storage means coupled to said receive word count adder means to store the word count of said operand received by said decimal unit from said cache.

18. The system of claim 17 wherein said adder means further includes character pointer adder means coupled to said adjusted length switching means, said first character pointer storage means and said first decimal type storage means for calculating the number of decimal digits said first operand is shifted in said decimal unit, and coupled to said adjusted length switching means, said second character pointer storage means and said second decimal type storage means for calculating the number of decimal digits said second operand is shifted in said decimal unit.

19. The system of claim 18 wherein said adder means further includes digit shift storage means for storing the numbers of decimal digits said operand is shifted in said decimal unit.

20. The system of claim 19 wherein said operand processing means comprises:
receiving means coupled to said cache for storing words of said operands transferred from said cache in response to said series of said microwords;
shifting means coupled to said receiving means and to said adder means and responsive to said shift count signals for aligning said words of said operands; and sending means coupled to said shifting means and to said execution unit for transferring said aligned words to said execution unit in response to said series of said microwords.

21. The system of claim 20 wherein said receiving means comprises:
input register means coupled to said cache for storing said words of said operands received from said cache in response to said series of said microwords;
input register switching means coupled to said input register, and responsive to said signals representative of said decimal type for receiving said words from said input register for stripping zone bits from said words; and word enabling means coupled to said input register means and to said adder means and responsive to said receive count signals and said send count signals for enabling said words of said operands for alignment, said register and switch control signals including said receive count signals and said send count signals.

22. The system of claim 21 wherein said sending means includes sign and exponent stripping means coupled to said shifting means and responsive to signals indicative of the location of the most significant decimal digit and the least significant decimal digits within their respective words of said operand for stripping said sign and said exponent from said operand received from said shifting means.

23. A data processing system comprising:
memory means for storing operands and instructions, each instruction including an operation code portion and also including descriptor information for describing characteristics of said operands, said instructions including an operation code portion specifying a decimal numeric operation performed by said system;
a decimal unit coupled to said memory means for receiving said operand words and signals indicative of said descriptor information, in response to signals indicative of said decimal numeric instruction;
said decimal unit including decimal unit control means, responsive to said instruction signals and said descriptor signals for generating register and switch control signals, said decimal unit further including operand processing means, responsive to said instruction signals, for receiving said operands from said memory means, and responsive to said register and switch control signals, for aligning said operands; and executing means coupled to said decimal unit for receiving said aligned operands for performing numerical operations specified by said decimal arithmetic instruction.

24. The system of claim 23 wherein said control means comprises:
storage means coupled to said memory means and responsive to said instruction signals for storing said descriptor information; and adder means coupled to said storage means, and responsive to said instruction signals and said descriptor signals for generating receive count signals indicative of the number of words of said operands to be received by said decimal unit from said memory means, send count signals indicative of the number of words to be transferred by said decimal unit to said executing means, and shift count signal indicative of the number of decimal digits said operands are to be shifted in said decimal unit.

25. The system of claim 24 wherein said adder means being responsive to said descriptor means includes scale factor adder means for calculating the scale factor of said operands and indicating an operand with a larger scale factor.

26. The system of claim 25 wherein said adder means, coupled to said scale factor adder means and being responsive to said descriptor signals, includes operand adjusted length adder means for calculating the adjusted length of said operands, said operand with said larger scale factor having said scale factor included in said adjusted length.

27. The system of claim 26 wherein said adder means include send word count adder means coupled to said adjusted length adder means for generating second word count signals indicative of the number of words of said operands sent from said decimal unit to said executing means.

28. The system of claim 27 wherein said adder means, being responsive to said descriptor signals, includes receive word count adder means for generating receive word count signals indicative of the number of words of said operands sent to said decimal unit from said memory means.

29. The system of claim 28 wherein said adder means, responsive to said descriptor signals, includes digit shift adder means for generating shifting signals indicative of the number of decimal digits send operands are shifted in said decimal unit.

30. The system of claim 29 wherein said operand processing means comprises:
receiving means coupled to said memory means and responsive to said instruction signals for storing said operands, said receiving means being further coupled to said adder means and responsive to said receive count signals and said send count signals for enabling said operands for alignment; and shifting means coupled to said receiving means and to said adder means and responsive to said shift count signals for aligning said operands, said send count signals, said receive count signals and said shift count signals being included in said register and switch control signals.

31. A data processing system comprising:
a cache memory for storing operands and instructions, each instruction including an operation code portion and also including descriptor information for describing characteristics of aid operands;
an execution control unit for storing microwords, said data processing system being responsive to said micro-words for execution operations specified by said instructions;
a control unit coupled to said cache and to said execution control unit, said cache and said control unit being responsive to said microwords for transferring one of said instructions and said descriptor information specifying a decimal numeric operation to said control unit from said cache, said control unit being responsive to said microwords for transferring said operation code portion of said one of said instructions to said execution control unit, said execution control unit being responsive to said operation code portion of said instruction for selecting a series of said microwords, said data processing system being responsive to said series of said microwords for executing said decimal numeric operation;
a decimal unit coupled to said control unit and said cache and storing said descriptor information in response to said series of said microwords, said descriptor information conditioning said decimal unit to align said operands when said operands are transferred to said decimal unit from said cache;
an execution unit coupled to said decimal unit and in response to said series of microwords, receiving said aligned operands from said decimal unit, and performing said decimal arithmetic operations thereby generating a resultant short operand for transfer to said decimal unit;
said decimal unit receiving said resultant short operand, and in response to said microword, assembling said short operand into data words, in response to said descriptor signals, for transfer to said cache.

32. The system of claim 31 wherein said decimal unit comprises:
decimal unit control means coupled to said execution control unit and to said control unit, and being responsive to a plurality of selected signals from said microwords from said execution control unit, and said descriptor signals for generating register and switch control signals; and operand processing means coupled to said execution unit and said cache and responsive to said series of said microwords for receiving said short operand from said execution unit and responsive to said register and switch control signals for aligning and merging said short operand for transfer to said cache.

33. The system of claim 32 wherein said decimal unit control means comprises;
decode means coupled to said execution control unit, and responsive to said plurality of selected signals from said microwords, for generating a plurality of command signals;
status means coupled to said decode means, and responsive to said plurality of command signals, said status means being further coupled to said control unit, and responsive to a plurality of control state signals, for generating a plurality of status flag signals; and control means coupled to said control unit, said status means, and said decode means, and responsive to said plurality of control state signals, said plurality of status flag signals, said plurality of command signals, and said descriptor signals for generating said register and switch control signals, said control means being further coupled to said status means, for generating said plurality of status flag signals.

34 The system of claim 33 wherein said control means comprises:
storage means coupled to said control unit and responsive to said plurality of control state signals for storing descriptor signals indicative of said descriptor information; and adder means coupled to said storage means, and responsive to said status flag signals and said descriptor signals, for generating and storing, send count signals indicative of the location of the most significant word of said short operand to be transferred to said cache from said decimal unit, and for generating and storing shift count signals indicative of the number of decimal digits said short operand is shifted in said decimal unit for transfer to said cache.

35 . The system of claim 34 wherein said adder means includes scale factor means, operand length adder means, and sign and decimal type indicating means, coupled to said storage means and responsive to said status flag signals and said descriptor signals for generating and storing said send count signals.

36. The system of claim 35wherein said adder means includes character pointer adder means, said scale factor means, said operand length adder means, said signal and decimal type indicating means coupled to said storage means and responsive to said status flag signals and said descriptor signals for generating and storing said shift count signals;
wherein said send count signals and said shift count signals generate said register and switch control signals.

37. The system of claim 36 wherein said operand processing means comprises:
receiving means coupled to said execution unit for receiving signals indicative of a first and a second word of said short operand in response to said plurality of command signals;
selection means coupled to said register means and responsive to said register and switch control signals, for selecting signals indicative of said first or said second word, or for selecting signals indicative of a word comprising numeric zero digits:
shifting means coupled to said register means and responsive to said shift count signals for shifting signals indicative of said first or second word, or said word comprising said numeric zero digits, a number of digit position specified by said shift count signals; and merging and sending means coupled to said shifting means and responsive to said register and switch control signals for forming said short operand words for transfer to said cache.

38. The system of claim 37 wherein said adder means further includes decrementing means responsive to said command signals and said status flags for decrementing said send count signals when said short operand word is transferred from said decimal unit to said cache.

39. The system of claim 38wherein said selection means is operative for selecting signals indicative of said word comprising numeric zero digits in response to said shift count signals and said send count signals being coded to specify a number whose value is greater than or equal to a first predetermined value;
wherein said selection means is further operative for selecting signals indicative of said second word in response to said send count signals being coded to specify a number whose value is equal to a second predetermined number;
wherein said selection means is further operative for selecting signals indicative of said first and said second words in response to said shift count signals and said send count signals being coded to specify a number whose value is equal to a third predetermined number;
wherein said selection means is further operative for selecting signals indicative of said first word in response to said shift count signals and said send count signals being coded to specify a number whose value is equal to a fourth predetermined number;
wherein said selection means is further operative for selecting signals indicative of said word comprising numeric zero digits in response to said shift count signals and said sent count signals being coded to specify a number whose value is less than said fourth predetermined number.

40 . The system of claim 39wherein said successive predetermined numbers starting from said first predetermined number are generated by decrementing said successive pre-determined numbers.

41. A data processing system comprising:
a cache memory for storing operands and instructions, each of said instruction including an operation code portion and also including descriptor information for describing characteristics of said operands;
an execution control unit for storing microwords, said data processing system being responsive to said microwords for executing operations specified by said instructions;
a control unit coupled to said cache and to said execution control unit, said cache and said control unit being responsive to said microwords for transfer-ring one of said instructions and said descriptor information specifying a decimal numeric operation to said control unit from said cache, said control unit being responsive to said microwords for transferring said operation code portion of said one of said instructions to said execution control unit, said execution control unit being responsive to said operation code portion of said instruction for selecting a series of said microwords, said data processing system being respons-ive to said series of said microwords for executing said decimal numeric operation;
a decimal unit coupled to said control unit and said cache for storing said descriptor information and receiving said operands in response to said series of said microwords, said decimal unit being conditioned by said descriptor infor-mation for determining if said operands are to be processed as short or long operands and for aligning said short and long operands;
an execution unit coupled to said decimal unit for receiving said align-ed short and long operands in response to said series of microwords and performing said decimal arithmetic operations;
wherein said decimal unit is further conditioned by said descriptor information and a plurality of status flag signals generated in response to a selected field of said microword of series of said microwords for generating a plurality of vector branch signals for predicting, in advance of said decimal unit receiving said short operands from said cache, the number of words, each of said short operands, said decimal unit will send to said execution unit, and further predicting the number of cycles between said short operands being requested from cache by said microwords, and a first word of said short operands being received by said execution unit;
said execution control unit being further coupled to said decimal unit, and being responsive to said plurality of vector branch signals for branching to a subroutine of said series of said microwords, for processing said short operands.

42. The system of claim 41 wherein said decimal unit comprises:
decode means coupled to said execution control unit and responsive to said selected field of said series of microwords for generating a plurality of command signals for indicating the operation said decimal unit will perform;

status means coupled to said decode means and responsive to said plural-ity of command signals, said status means being further coupled to said control unit and responsive to a plurality of control state signals for generating a plurality of status flag signals, said status flag means being responsive to said plurality of status flag signals for generating a sequence of status flag signals for controlling said decimal unit operation;
control means coupled to said control unit for receiving said descriptor information in response to said plurality of control state signals for generating a plurality of descriptor status signals; and said control means being further coupled to said status means and re-sponsive to said sequence of said status flag signals and to said plurality of said descriptor status signals for generating said plurality of vector branch signals.

43. The system of claim 42 wherein said descriptor information for describ-ing characteristics of said operands includes a first descriptor for describing a first operand and a second descriptor for describing a second operand, said first and second operands being aligned by said decimal unit for transfer to said execu-tion unit, said execution unit being responsive to said series of said microwords for executing said decimal numeric operation using said first and second operands;
wherein said descriptor information includes signals representative of a scale factor for indicating the position of the decimal point of said operand, signals representative of a length of said operand to indicate the number of decimal characters in said operand, signals representative of a character pointer position to indicate the position within a word of the most significant character of said operand and whether said word has an odd address or an even address in said cache, and signals representative of the decimal type of said decimal charac-ters of said operands to indicate the number of bits contained in said decimal characters received from said cache, the location of a sign character and whether said operand was a floating point or scaled operand.

44. The system of claim 43 wherein said control means comprises:
storage means coupled to said control unit and responsive to said plurality of control state signals for storing descriptor signals indicative of said descriptor information; and adder means coupled to said storage means and responsive to said status flag signals and said descriptor signals for generating said plurality of descrip-tor status signals.

45. The system of claim 44 wherein said storage means includes a first scale factor storage means for storing signals representative of said scale factor of said first operand and a second scale factor storage means for storing signals representative of said scale factor of said second operand;
said storage means further including a first length storage means for storing signals representative of said length of said first operand and a second length storage means for storing signals representative of said length of said second operand; and said storage means further including a first decimal type storage means for storing signals representative of said decimal type of said first operand and a second decimal type storage means for storing signals representative of said decimal type of said second operand.

46. The system of claim 45 wherein said adder means includes send word count adder means coupled to said first scale factor storage means, said first length storage means and to said first decimal type storage means for receiving said signals representative of said first operand scale factor, said first length and said first decimal type for generating a first one of said plurality of descriptor status signals indicative of the number of words said decimal unit will send to said execution unit for processing a first short operand; and said word count adder means being further coupled to said second scale factor storage means, said second length storage means and said second decimal type storage means for receiving said signals representative of said second oper-and scale factor, said second length and said second decimal type for generating said first one of said plurality of descriptor status signals indicative of the number of words said decimal unit will send to said execution unit for processing a second short operand.

47. The system of claim 44 wherein said storage means further includes a first receive character pointer storage means for storing signals representative of said character pointer position of the most significant character of said first operand and a second receive character pointer storage means for storing signals representative of said character pointer position of the most significant charac-ter of said second operand.

48. The system of claim 47 wherein said adder means further includes receive character pointer adder means, coupled to said first receive character pointer storage means, and to said first decimal type storage means, and being responsive to said signals representative of said character pointer position of the most significant character of said first operand and being further responsive to sig-nals representative of said decimal type of said first operand, for generating receive digit pointer signals, indicative of the position of the most significant digit of said first operand; and said receive character pointer adder means, being further coupled to said second receive character pointer storage means, and to said second decimal type storage means, and being responsive to said signals representative of said character pointer position of the most significant character of said second oper-and, and being further responsive to signals representative of said decimal type of said second operand, for generating receive digit pointer signals indicative of the position of the most significant digit of said second operand.

49. The system of claim 48 wherein said adder means further includes send character pointer adder means, coupled to said first scale factor storage means, said first length storage means and to said first decimal type storage means, for receiving said signals representative of said first scale factor, said first length and said first decimal type for generating send digit pointer signals indicative of the position of the most significant digit within said first oper-and word transferred to said execution unit from said decimal unit; and said send character pointer adder means being coupled to said second scale factor storage means, said first length storage means and said second deci-mal type storage means, for receiving said signals representative of said second operand scale factor length and decimal type for generating said send digit point-er signals indicative of the position of the most significant digit within said second operand word transferred to said execution unit from said decimal unit.

50. The system of claim 49 wherein said adder means: further includes send digit pointer adder means coupled to said receive character pointer adder means, and to said send character pointer adder means, and responsive to said receive digit pointer signals and to said send digit pointer signals for generating first signals indicative of the difference in digit position of the most significant digit of said first operand received by said decimal unit, and the digit position of the most significant digit of said first operand sent to said execution unit from said decimal unit, and said send digit pointer adder means being further responsive to said receive digit pointer signals and to said send digit pointer signals for generating shift signals indicative of the difference in digit posi-tion of the most significant digit of said second operand received by said deci-mal unit and the digit position of the most significant digit of said second oper-and sent to said execution unit from said decimal unit.

51. The system of claim 50 wherein said control means, being responsive to said short operands, includes word count vector means responsive to said first one of said plurality of descriptor status signals for generating a word count vector branching signal indicating a one word transfer from said decimal unit to said execution unit when said word count vector branching signal is a binary ZERO
and indicating a two word transfer from said decimal unit to said execution unit when said word count vector branching signal is a binary ONE.

52. The system of claim 51 wherein said control means being responsive to said short operands includes two cycle delay vector means coupled to said status means and responsive to selected ones of said status flag signals, said signals representative of said character pointer position and to said shift signals for generating a two cycle delay vector branching signal for said first and second operands respectively.

53. The system of claim 52 wherein said control means being responsive to said short operands includes one cycle delay vector means coupled to said status means and responsive to selected ones of said status flag signals, said signals representative of said decimal type, said shift signals and to said signals representative of said character pointer position for generating a one cycle delay vector branching signal for said first and second operands respectively.

54. The system of claim 53 wherein said execution control unit is res-ponsive to said one cycle delay vector branching signal, said two cycle vector branching signal and said word count vector branching signal for generating selected sequences of microwords for processing said short operands.

55. A data processing system comprising: a cache memory for storing operands and instructions, each instruction including an operation code portion and also including descriptor information for describing characteristics of said operands; an execution control unit for storing microwords, said data processing System being responsive to said microwords for execution operations specified by said instructions; a control unit coupled to said cache and to said execu-tion control unit, said cache and said control unit being responsive to said microwords for transferring one of said instructions and said descriptor informa-tion specifying a decimal numeric operation to said control unit from said cache, said control unit being responsive to said microwords for transferring said operation code portion of said one of said instructions to said execution control unit, said execution control unit being responsive to said operation code portion of said instruction for selecting a series of said microwords, said data processing system being responsive to said series of said microwords for executing said decimal numeric operation; a decimal unit coupled to said control unit and said cache and storing said descriptor information in response to said series of said microwords, said descriptor information conditioning said decimal unit to align said operands when said operands are transferred to said decimal unit from said cache; and an execution unit coupled to said decimal unit and in response to said series of microwords, receiving said aligned oper-ands from said decimal unit and performing said decimal arithmetic operations thereby generating a resultant long operand for transfer to said decimal unit;
said decimal unit being responsive to said series of microwords for generating start write signals and send data signals; said execution control unit being responsive to said start write signals and said send data signals for generating said series of microwords for storing said long operand in said cache.

56. The system of claim 55 wherein said decimal unit comprises: decimal unit control means coupled to said execution control unit and to said control unit, and being responsive to a plurality of selected signals from said micro-words from said execution control unit and said descriptor signals for generating said start write signals, said send data signals and register and switch control signals; and operand processing means coupled to said execution unit and said cache and responsive to said series of said microwords for receiving said long operand from said execution unit and responsive to said register and switch control signals for aligning and merging said long operand for transfer to said cache.

57. The system of claim 56 wherein said decimal unit control means com-prises: decode means coupled to said execution control unit and responsive to said plurality of selected signals from said microwords for generating a plural-ity of command signals; status means coupled to said decode means and res-ponsive to said plurality of command signals, said status means being further coupled to said control unit and responsive to a plurality of control state signals for generating a plurality of status flag signals; control means coupled to said control unit, said status means and said decode means, and responsive to said plurality of control state signals, said plurality of status flag signals, said plurality of command signals and said descriptor signals, for generating said start write signals, said send data signals, and said switch and register control signals, said control means being further coupled to said status means, for generating said plurality of status flag signals.

58. The system of claim 57 wherein said control means comprises: storage means coupled to said control unit and responsive to said plurality of control state signals for storing said descriptor signals; adder means coupled to said storage means and responsive to said descriptor signals, shift signals and said status flag signals for generating said start write signals, said send data signals and said switch and register control signals.

59. The system of claim 58 wherein said adder means includes: shift count means coupled to said storage means and responsive to said descriptor signals for generating said shift signals representative of the number of decimal digits position said operand is shifted in said operand processing means.

60. The system of claim 59 wherein said adder means includes: receive word count register means coupled to said decode means and said status means and responsive to said command signals and said status flag signals for generating and storing signals representative of the number of significant words said decimal unit will receive from said execution unit.

61. The system of claim 60 wherein said adder means further includes:
send word count adder means coupled to said storage means and responsive to said descriptor signals for generating and storing signals representative of the number of words said decimal unit will send to said cache.

62. The system of claim 61 wherein said adder means further includes:
comparison means coupled to said receive word count register means and said send word count register means and responsive to a first plurality of signals respresentative of the number of significant words said decimal unit will receive from said execution unit, a second plurality of signals representative of the number of words said decimal unit will transfer to said cache, and said shift signals, for generating said register and switch control signals; said comparison means being further coupled to said status means and responsive to said status signals, said shift signals and said first and second signals for generating said start write signals and said send data signal when said first and second signals are in a predetermined relationship with each other.

63. The system of claim 62 wherein said operand processing means comprises:
receiving means coupled to said execution unit for receiving signals indicative of said long operand words in response to a first series of microwords, said execution control unit being responsive to said send data signals for gener-ating said first series of microwords; merging means coupled to said receiving means and responsive to said register and switch control signals for aligning and merging said long operand words for transfer to said cache in response to a second series of microwords, said execution control unit being responsive to said start write signal for generating said second series of microwords.

64. The system of claim 63 wherein said comparison means is responsive to said first and second plurality of signals for generating comparison signals indicative of the relationship between the binary numbers represented by said first and second plurality of signals.

65. The system of claim 64 wherein said receive word count register means includes receive count down means responsive to said status flag signals for decrementing said signals stored in said receive word count register means each time said operand word is received by said decimal unit.

66. The system of claim 65 wherein said send word count register means includes send count down means responsive to said descriptor signals, said status flag signals, said comparison signals, for decrementing said send word count register means each time said operand word is transferred to said cache.