DE3000045A1 - DATA PROCESSING SYSTEM - Google Patents

Description

DIPUINCHEINZBARDEHLE WiBfHBX * Jan. 2, 1980

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Reference number: My reference: 2988

Honeywell Information Systems Inc. 200 Smith Street
Waltham, Mass. V.St.vA

data processing systems

03002Θ / Ο881

SS P 2988

description

The invention relates generally to processing of commands in decimal-numerical form by means of a micro-programmed data processing system syst ems.

Microprogrammed data processing systems included a main memory and a central memory. The main memory stores operands and commands or instructions. The operands can be stored in various forms, including decimal-numeric Forms, the instructions for specifying the processing of the decimal-numeric instructions include descriptors, which define the properties of the operands that contain the decimal-numeric characters.

The control store stores a variety of microwords. Each microword consists of a specific one Number of bits with which it enables certain functions in the data processing system. A row of Microwords is called a microprogram subroutine, which when processed sequentially, the data processing system enabled to perform a specific operation.

If the data processing system has a decimal-numeric Reading instruction from memory, causes a field in the instruction which indicates the type of the decimal-numeric Operation, for example the addition of two operands and the storage of the resulting = » the operand, the selection of the first microword of a subroutine from the control memory, the relevant Microword begins the addition process "

300Ö045

In previously known systems, then ₉ x iexm the subroutine their Yerarbeitung finishes called "another subroutine ₅ determine su _p where Pro = process the system as a next process executes ,, This next selected process depends on their own sheep = - th of the operand from _o If the operand is a 4-bit decimal point _s then a micro-programmed subroutine is selected _s and if the operand is a 9 ° = bit decimal point, a further micro-programmed subroutine is selected. The continuous checking of the properties of the operand when the respective subroutine is terminated reduces the overall throughput of the system considerably. Many decisions are made during the processing of a particular decimal number command. Each decision point requires a subroutine to check the operand to determine the location of the first microword of the next subroutine used in the sequence, thereby enabling the control store to branch to that first microword.

In US-PS 35 70 006 an arrangement for execution a multiple branch operation in which a large number of branch addresses with corresponding test conditions is specified in advance and for which the Results are stored in the course of the determination of a "branching and storage tsf" signal.

The branch address registers store digital information corresponding to an address or a part an address within an associated memory. A flip-flop is associated with each of the branch adder registers, which is set as a result of the successful fulfillment of the conditions set within the system exist, and when it is set, the branch operation is brought into a corresponding state.

3 ο ο :: c /: ■ 5

Such a known system, however, involves a considerable amount of hardware in order to carry out the relevant functions _{or the like}

Digital © computer systems execute commands "which call the processing of Bqsisaal operands" The deci = mal ~ Gper®nd © 2i consist of a multitude of words, each of which contains a multitude of special characters lia ttet Izwn, £ qt & gt one ! »Formation that is not contained in the © psranden _o The decimal characters contain desimal digits in the form of 4-bit decimal digits which are put together or packed up to eight decimal digits per word ^ or; 9 ° bit ~ ASCII ~ or -EBCIC = Decimal digits, which are composed of up to four decimal digits per word or where they are packed o The .decimal characters also contain signs and exponent characters for floating point instructions.

The operands are stored in memory; In the previously known arrangement, they are transferred to an arithmetic unit or arithmetic unit in which the words · are freed from the signs, exponent and non-operand characters freed and inserted into words or ₀ packed together, with up to eight decimal digits per word being put together _o This enables a simple decimal calculation, in which operands that contain 9 = bits = decimal digits are followed by 4-bit decimal digits on the command which calls a decimal arithmetic operation of the two operands.

Before the resulting operand is returned to memory is saved, however, the required prefix = sign, exponent and non = operand characters must be added as are the zone bits, if the resulting operand must consist of 9 = bits = characters <

'© is 1

300004

In the Honeywell 6000 reimer system, the mixing of the signs = ^ zone bits = _esrponent and Might operand characters together with the numerical characters in the form of words of the resulting operand is carried out with the use of a considerable cohabitation logic

Micro-programmed computers carry out ο, Ιθοθ mixing operations by using mikroprograoaisrtea Siabroutinen from., through which the D © siE © lsiffrn the reehen result be pushed into the correct position within the word and through which the sign, exponent, zone bits and adding non-operand information. Since the micro-programmed subroutines are in a serial Manner, system throughput was degraded.

Data processing systems process data stored in a memory in Ferm of decimal digits _o Some commands or instructions lead when they are processed by the Datenveracbeitungs system, to the fact that arithmetic operations are performed on the basis of decimal digits. For example, a decimal-numerical instruction can be processed by the computing system in that a series of decimal digits - operand 1 from a group of memory locations is added to a further series of decimal digits from another group of memory locations - operand 2 - and the result - Operand 3 - is accommodated in a third group of memory locations.

Descriptors belonging to the command or instruction define the properties of each of the operands _o An operand can be a floating point number or a fixed value number. Each decimal digit can be four bits or nine bits. The descriptor also specifies the number of decimal digits in the operand, the position of the decimal

030028/0881

doho the scale factor _s the character position within a word of the character of the highest value of the operand and the position of the sign fixed _P if the operand contains a sign, either in the character position of the highest value = leading sign - or in the character position of the lowest value for a Fixed value operands - following sign = sign «, The command b2W _o the instruction supplies a display In the case ₅ that the operand is in ASCII code or in EBCDIO code» and if the sign is part of an over-hole character ₀

In the previously known computer systems “for example in the case of the Honeywell 6000 family of computers, the operands are right-aligned in the arithmetic unit, and so = Then if the operands run through a sequence of logic operations, by which the operands are aligned in such a way that the arithmetic operations are carried out can be.

Data processing systems that are controlled by firmware have been provided to provide systems with less hardware to perform the same functions. These microprogrammed systems require however, a large number of firmware steps including branching to firmware routines in order to align the operands for the purpose of performing arithmetic operations.

The solutions shown above for executing the operand alignment have led to a ¹ limitation of the performance of the computer system when decimal search commands have been executed? because of the large number of computer cycles that were required to align the operands ,,

The invention processes an operand 3 in accordance with its descriptor for storage in a memory.

In the previously known systems, such as with the computers of the Honeywell computer family 6OOO> an operand 3 is stored in a register bank, where sets a combination linkage arrangement pointer so that the number and positions of leading and trailing zeros as well as the character size, i.e. four bits or nine bits, and the position of the sign, the back or the front are designated.

Microprogrammed systems have been developed to perform the same functions as are performed by the hardware systems of the Honeywell computer system 6000 the microprogrammed systems concerned have reduced manufacturing costs. In certain areas as during the processing of decimal-numeric instructions, but was a significant number of firmware steps required to provide the resulting operand J5 for storage in memory, whereby the system throughput was reduced during the processing of the decimal-numeric instructions.

In normal processing, the maximum number of decimal points in an operand is 64 characters. In the Honeywell computer system 6000, there are hardware registers that were able to store the 64 characters in question. They were very seldom Operands 64 characters long. Much of the operands require 15 decimal digits or fewer decimal digits during normal data processing.

Micro-programmed computer systems have been developed

to reduce the amount of hardware required in Systems such as the Honeywell computer system 6000 is required to convert the words of the operands under the To process firmware control, through the Using firmware subroutines in a serial fashion. The micro-programmed system would merely Hardware registers need to store a maximum of 15 decimal digits, with the remainder in stored in a notepad memory. Operands comprising one to five words stored in main memory stored can have fewer than 16 decimal digits (up to four 9-bit decimal digits or eight 4-bit decimal digits are stored in one word). The firmware therefore requires a considerable number of firmware steps to load the maximum 16 decimal digits into the register for processing., This will be considerable Time spent by the firmware going through loops and waiting for words from the Main memory.

The invention is accordingly based on the object of providing a data processing system with an increased throughput or to create an improved data rate.

The new data processing system to be created is also intended to increase processing throughput of decimal-numeric instructions *

The object indicated above is achieved by the invention covered in the patent claims.

According to the invention there is provided a data processing system which includes what is hereinafter referred to as a cache memory Contains notepad memory, which is used to store operands and commands or instructions, their each an operation code part and also a descriptor

030028/0881

information that is used to describe the properties of the operands. It is also an execution control unit intended for storing micro words. The relevant data processing system is responsive to the microwords concerned to perform the operations identified by the opcode portion of the instructions in question. With the cache or scratch pad memory and with the execution control unit a control unit is connected. The cache memory and the control unit speak to the relevant micro-words in such a way that the transmission of a Instruction and the descriptor information designating a decimal-numeric operation to the control unit from the cache memory. The execution control unit responds to the microwords such that the operation code portion of the relevant one instruction is transmitted to the execution control unit. the relevant execution control unit responds to the opcode portion of the instruction to select one Row of microwords. The relevant data processing system speaks to the relevant series of Microwords for performing the decimal-numeric operation. With the control unit and the cache memory is further connected to a decimal unit which stores signals which are characteristic of the descriptor information, the relevant storage taking place upon the occurrence of the relevant series of micro-words. The descriptor information signals cause the decimal unit to take up the operands, the relevant ones Align operands when transferring those operands from the cache to the decimal unit. Furthermore, an execution unit is connected to the decimal unit in order to obtain the aligned operands from the relevant Decimal unit to include the occurrence of the relevant series of micro-words and the decimal arithmetic operations to execute.

030028/0881

-jar- 300Qi) 'iS>

The invention also provides a data processing system with a cache memory which is used to store operands and commands or instructions, each of which contains an operation code part and also descriptor information which is used to describe the properties of the operands. An execution control unit for storing microwords is also provided. The data processing system concerned is responsive to the microwords to carry out operations indicated by the instructions. With the cache memory and the execution control unit, a control unit is also connected, which responds with the cache memory to the relevant micro-words to one of the instructions or one of the commands by the descriptor information, which designates a decimal-numerical operation, from the cache memory to the relevant control unit to be transmitted. The control unit in question responds to the micro-words in order to transmit the opcode portion of one of the instructions to the execution control unit. The execution control unit is responsive to the opcode portion of the instruction to select a series of microwords. The data processing system responds to the relevant series of microwords in order to carry out the decimal-numeric operation. A decimal unit connected to the control unit and the cache memory stores the descriptor information on the occurrence of the relevant series of micro-words. The descriptor information causes the decimal unit to align the operands when the operands in question are transferred from the cache memory to the decimal unit. An execution unit connected to the decimal unit, which is responsive to the relevant row of micro-words, receives the aligned operands from the decimal unit and performs the decimal arithmetic operations, whereby a resulting short operand for transmission to the decimal unit

BATH ORIGINAL

wirdo generates The Beziaaleinheit concerned shall the resulting course operands and adds to the on = contact of the microswitch to tough Mn relating to the ICurg = Gperan = make memory to a ₀ and that = the descriptor signals Mn ₂ su in Datemförter to transfer the cache ,,

Is by the invention a Datenvararbeitungs · = systGm is further provided with a cache memory ^ the "for storing Won operands and instructions bzwo Be = serves missing _s each of which an operation code part further raid a Daskriptorinformation ₉ comprises the Eigensesaf = th operand concerned describes _o Further An execution control unit for specifying micro-words is provided _o The data processing system speaks to the appropriate a Müsr-o ^ arter Ba ₀ vn by the commands Ö2x-7o InstruSrfcionen bezeicbaete operaadon is executed . With the cache executor further comprising a control unit connected to the cache memory and the control unit ₉ to transfer one of said instructions and a decimal numerical operation characteristic descriptor from the cache memory to the control unit / loci talk thereby to Mikrov. the control unit is responsive to the micro- = words to to find the opcode part of the n to transmit an instruction to the execution control unit. The execution control unit is responsive to the opcode portion of the instruction to select a series of microwords. The data processing system responds to the relevant series of microwords to perform the decimal-numeric operation. A decimal unit is connected to the control unit and the cache memory and is used to store the descriptor information on the relevant row of microwords. The relevant descriptor information causes the decimal unit to align the operands when the

300004

Corresponding operands from the cache memory to the decimal unit would be carried out ₀ The decimal unit is linked to an execution unit _p the R®iii © of the microwords that are aligned with the on = teats® of the microwords © » , Op © Rånö © n of dor Dozinal © content receives öio DozinQX "EocJxö2ioporQti @ nsn executes _p which ο in Ία®βο $ · OporaM for transmission to the IIIo owBOVißt uIäU Dio BoaioaloiBhoit dm £ filo feotroffoEiäo Moiho aor I-Ekrot / örter & n _s ua 815 05 ³ SQ ^ OB MBd ίο Datoncignale off

öio OtlOP ^ SGi ^ OiltiaiGC ^ S " ^{0 1} ^ CKsf dio

C3OO iQEgOa G ^ Q ^ QCOOQ iß ÖQD

the Erfinduag further provides a data processing = system with einee Cachsspeicher created _s of for storing operands and instructions or _o instructions serves _s whose ^ ed © an operation code part and ₉ further comprising a descriptor includes the properties of the respective operand describes "Further, an Off = master controller provided for storing microwords the data processing system responsive to the particular micro words anj to execute the or by the commands "instructions operations designated ,, A control unit is coupled to the cache memory and the execution control unit connected to the cache memory and the control unit are responsive to the particular micro words of _P in order to transfer one of the instructions and the descriptor information designating a decimal = numeric operation to the control unit from the cache memory The execution control unit also responds to the relevant operation code part of the instruction in order to transfer a number of the

Mikroi / loci select ,, The DatemrerarbGitungssystem responsive to dlo concerning © Esllie of ³ microwords to _s the dezisal-BUHSPisciie operation OMSSMfübren _o Further, sine decimal unit is provided di © ß ± * fe of the control = unit verbündea lo "ö _P uoboi ÖSF bet ^ offöMe Spelehsrplota the StGuoifQiiiÄoit υκώ öof CcQfeQopQiofeos ⁵ sRA storage ögf BacIi ^ S.poQP-IafornGtioa u :: cl swf Λπί & οΐΏΟ elojr OpoFandOE on ÖIG ΐ) θ "ο ^ οί £ θΕ: ΐο doiko üop PAlJFQVuFtOi? (SIgsoKo Bio feo = troff GUUo SosicalcÜDlioi-ö ö £ ocö 5οι? Γ; οσ? - ohi? AMorielituBß dop

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fa ^ matiosi mä diireii Qiao ¥ 3. © 2salil vöbs signalers, which darcii an output field of the respective number are generated by Mkrov / localers ₉ to generate a large number of vector _{branch signals 8} by which the execution control unit = unit the properties of the relevant operands are displayed. The relevant execution control unit responds to the plurality of vector branch signals to branch to a subroutine of the relevant series of microwords for processing the operands »

The invention also provides a data processing system with a cache memory for Storage of operand words and commands or instructions is used, each operand word encoded in this way is that it denotes a number of types of information, the relevant number being the types of information Includes decimal digits, signed characters, exponent characters, and non-operand information, and each of the respective Instructions comprises an opcode portion which is a decimal-numeric one executed by the system Operation, and also a descriptor information

030028/0381

30UuC-S

tion "has a describes the properties of the operand words in question _ο An execution control unit is also provided which is used to store micro words ο The data processing system responds to the micro words in question _p to carry out the operations identified by the operation code part of the instructions o With the cache memory and the execution = control unit further comprises a control unit connected to the cache memory and the control unit are responsive to the respective Mikroiförter to _s for one of the relevant commands and else dszimal-iauEierische operation speaks designating Deskriptorinforaiation from the cache memory to the control unit to be transmitted, the control unit on the HikrouÖrter For the purpose of the transmission OQO.: 0pQrationscodeteiles of one of the relevant commands eh to the execution control unit to _o The execution = stauereialieife -spri <sllt to the operation code part of the relevant command = to a number of Select micro-words. The data processing system responds to the relevant row of microwords "in order to carry out the decimal = numerical operation". A decimal unit is also connected to the control unit and the cache memory and stores the descriptor information received by the relevant control unit and that from the cache forth recorded operand words stores ₀ the descriptor causes well ₉ for for the decimal digits of the operand words decimal \ fählen ₉ when the operand words from the cache memory to the decimal = unit is transferred _o the respective decimal = unit, an execution unit is further connected ^ for receiving the Decimal digit η serves on the relevant row of micro words and which executes the relevant decimal numerical command ₉ v / o by means of the decimal digits defining a calculation result are generated and transmitted to the decimal unit in order to generate the resulting operand words for transmission to the cache memory. The decimal unit also includes a sliding device

processing for generating Register = and switch control DC signals ,, which are used for selection of Deziaalziffern the Opera "= denwörter ^ soft from the cache memory aufgenom = men are and which further sur formation of the resulting öperandenwörter used t / erdsiir, viQloh® won d @ r guide unit in the cycle sat up in welsliem the Gperandeni- / © rt © r from the processed ü

A preferred embodiment of the present invention comprises a data processing system having a cache memory or _o storing instructions _p comprise _s the instructions, the descriptors and operands "also includes the respective Da = tenverarbeitungsanlage a control unit ₉ which receives the commands and descriptors from the cache memory, sov / ie a execution control unit, which receives the commands from the control unit ago ₉ "to a series of micro words to generate _s which release the data processing system for executing the commands" the system further includes a decimal, the-Reehenoperationen decimal is ifirksam during the processing of and receives the descriptors and operands from the cache memory under microprogram control and thereby aligns the operands; that an interpretation is made of the descriptor fields which define the operand. Furthermore, an execution unit is provided which receives the aligned operands from the decimal unit and which executes the decimal arithmetic function which is identified by the instruction.

The decimal unit takes a descriptor specifying an operand 1 and a descriptor specifying an operand 2 Descriptor at the beginning of the load operation. The decimal unit saves the scale factors for operands 1 and 2. The scale factor is the position of the decimal point. A scale factor of zero denotes the decimal point to the right of the least significant position.

030026/0881

Sin scale afaktop- of +2 shifts the decimal point by two digits to the right, whereby two zeros are added to _{the operand 0} A scale factor of oinus three adds the decimal point three positions to the left _s in the thousands position., The decimal unit further stores the descriptor = - and descriptor = ^ - = - information, which includes the operand length, data type, the Vorz © ichentyp ~ bits, the position of the character = pointer, d _o h _o the character position within the word of the most Character, in the registers of the decimal unit.

The decimal unit calculates the number of words of operand 1 that are accepted by the decimal unit * and the number of words of operand 1 that are sent out for execution ₀ This enables the decimal unit to determine when operand 1 has been processed by the decimal unit in order to be able to carry out the above calculations for operand 2 before it is included o

The firmware controls the loading of the descriptor information defining the operands into the decimal unit “Die Firmware tells the decimal unit that each operand is to be read through the decimal unit “The decimal unit indicates to the firmware the number of words of the respective operand, which for the purpose of execution from the decimal unit is to be transferred.

The decimal unit ~ as in the preferred Aus = Execution is described - increases the throughput considerably by putting the link in the decimal unit for parallel processing before the operand is added and then each operand "im In the course of the transmission or «the occurrence" stops if this is transmitted by the decimal unit »This

030028/081

Process can be compared with a form of the known arrangements in which the operand is in a Register was saved right-justified and when manipulations were made with regard to the operand, to align this correctly. The firmware solution checked the operand, branched to different ones Microprogram subroutines and performed serial control of the hardware to set the operand align properly.

In the decimal unit, the operand characters are _{freed from the zone bits, sign s} if applicable, and exponent characters, if applicable, and inserted into words, with a maximum of eight decimal characters being packed into one word.

The operands are fixed; they are processed as short operands or as short operands, if each operand detected in the decimal load operation has fifteen decimal digits or fewer digits. The operands are defined as long operands and processed if each operand that is in the decimal « Load arithmetic operation involved has more than fifteen and less than 64 decimal digits.

The invention includes, among other things, the processing of short operands. Short operands are in the cache stored in the form of one to five words. For example, operands are fifteen decimal digits and a preceding sign and composed of 9-bit ASCII or EBCDIC characters in four decimal digits one Word saved. If the sign is in the second, third or fourth position of the most significant Word is stored, then are the operand, fifteen decimal digits and the leading sign stored in five words. In the decimal unit, the five-word operand is compressed into two words, each of which

030028/0881

aeht decimal digits bz ^ / _{0 has} seven decimal digits ^

which are submitted to the execution unit for the purpose of processing _ö

The Äa © rdmmg Iu of the D © zisaaleinheit calculates the number of ficsr words j> which are given to filq Atssfüferuagseinlaeit =, Whom toside upeT & n & en ₀ the desiaal unit has taken from Caeläöspsieher ₈ short operands then the Begimal unit calculates the number of cycles between the Time ₉ at which the first read command is sent to the cache memory, and the time at which the first data word is sent to the execution unit »

It is now assumed that the first word received from the cache memory contains the sign in the fourth word position “If the relevant word could fill a register for transmission to the execution unit, the firmware would require a zero = cycle delay "The second word picked up from the cache contains four 9 = bit = characters _o If the first and second words could fill a register for transmission to the execution unit, then the firmware would require a 1 = cycle = delay" In the above For example, the first word and the second word do not fill the register because they only contain four characters. O The third word taken from the cache contains four 9- ^=> bits = characters5 if the first word _{0 is} the second word and the third word is the register then the firmware would actually require a 2-cycle delay _{or similar}

The arrangement in decimal units predicts the number of words for the short operand that to be sent to the execution unit, and with regard to the number of delay cycles that the firmware are required. This prediction = information is sent to the

Wirdρ execution control unit with the aid of PKYCTR signals ausgesendetρ by a branch of a microprogram subroutine caused the DI® exact firmware steps of ₀ which are needed _s to process the operands tfodurch unnecessary looping and branching is avoided _o

An ARWC adder (730-60) shows the number of words in the operand at _P that the decimal unit sends to the execution unit. In the case of a short operand, the ARWC 6-bit position indicates that the decimal unit stored a short operand. Cycles for four bits and nine bits per operand character. The information regarding the number of words in the short operands and regarding the number of delay cycles required by the firmware is available to the firmware in response to firmware commands.

The invention also provides the alignment and mixing of the resulting short operand, by the decimal unit from the execution unit is recorded here. The resulting operand is given in decimal units in accordance with a descriptor which is stored in the decimal unit, describing the properties of the resulting operand are how to store it in memory.

If the value stored in the registers of the execution unit resulting operand contains fifteen decimal digits or less, show firmware signals to _s that the resulting operand is treated as a short operand, although the descriptor describes the result operand as a length of more than fifteen decimal digits comprising.

030028/0881

The desimal unit responds to a firmware command to ₅ which designates a memory _{operand operation 9} by transferring words in the correct format to the cache memory »The execution unit and the control unit form the write address under firmware control and the write commands for the cache memory ₉ around those from the decimal unit to write the transferred words into the cache memory «, After commissioning, the transfer of words between the decimal unit and the cache memory continues without any further firmware intervention by the decimal unit _e

The execution unit sends under the firmware control first of all the digit of the lowest value to the decimal unit in which it is stored in an RPK = register (730-162) stored v / irdp and then sends the unit concerned sends the word with the highest value to the buffer (730 = 168) of the decimal unit. If the short resulting operand reads only one word length, then the word with the highest value would be ins = total zeros included

A send word count = RRWC = register (730 = 88) in decimal unit saves the internal digit of the data word with the highest value, from the decimal unit to the Cache memory is to be transferred = the value of the second word count register is reduced each time when a word consisting of 4-bit = characters is sent out to the cache memory o The send word count register is reduced in value whenever a word consisting of 9-bit characters is followed by an odd Address in the cache memory is sent out in response to a firmware command.

030028/0881

000045

The contents of the second ¥ © ortzäMr glsters is determined by the generated Deslcriptorinforraatioa _s stored in the decimal *,

A shift count RDSC register (730-58) stores one Information showing the number of decimal digit positions in which the resulting operand is in the decimal unit is pushed. A negative shift count indicates a left shift, and a positive one Shift count indicates a right shift.

The decimal unit sends words that contain a total of zeros to the cache memory in response to firmware commands or commands out until the send counting register signals stores which provide an indication that the operand word containing the most significant character is about to is to be transferred to the cache memory. The word can have decimal digits or contain the operand word, or it can only contain a leading sign.

The data words are aligned in the decimal unit and merged and transferred to the cache. If the number of words specified by the descriptor of the operand is equal to the number of words transferred to the cache as indicated by an RWC register (730-84), the firmware ends the store operation and the system begins processing or processing of the next instruction.

The relationship between the counter positions shown in the RWPC register and stored in the RRWC register, triggers register and switch control signals through which the output signals of the ZPKR switch (730-164) and of the ZPKL switch (730-166) in a specific sequence

03002Ö / 0881

to be selected _o

The present invention also aligns and mixes the with the decimal unit resulting received from the execution unit long operands ,, "The resulting operand is stored in the Decimal unit processed in accordance with a descriptor stored in the decimal unit and describe the properties of the resulting operand as operands to be cached.

The decimal unit responds to a firmware command by counting the number of significant words of the resulting operand and by storing the relevant counter position in a RWC receiving word count register _o The decimal unit also calculates the number of words _ρ from the descriptor = information that the decimal unit is sent to the cache memory will send out ₉ and the unit concerned also stores the value in an RRWC ~ send word ~ count register o

The long operand store operation begins with the execution control unit retrieving the Execution control memory reads out a microword "which signals encoded in this way includes "that denotes an operation is, according to which "an operand is stored in the decimal = hext" «, reads on the next cycle the execution control memory a microword resulting in a System ^ est of the decimal unit start write signal line The DSTRT-WRT start write signal line led from the Register and the switch controller (730 = 91) shows the relationship between the counter position in the RWPC register (730-84) and the RRWC register (730 = 88) » The start write signal line carries a logic signal zero when the counter is in the RWPC register is greater than the counter reading in that

1/0881

^ 3 O O O? A.

tv

RRWC register indicating the number of operand words in the execution unit is greater than the number of operand words that are allowed by the Descriptor is designated. This is normal because the execution unit Stores 64 decimal digits or eight words while specifying a long operand Descriptor would display three to eight words for the long operand. The decimal unit gives zeros containing words from decimal to are processed by the contents of the RWPC register as long as is decreased until the counter of the RWC register is equal to the count of the RRWC register. As a result, a link signal is sent to the start visual write signal line 1, provided that a complete operand word is in the Decimal unit can be composed. When a complete word is not composed in decimal units then the firmware initiates the transfer of the next word from the execution unit the decimal unit out, and towards the cycle in which a complete word is composed in the decimal unit a logic signal 1 is sent to the start writing signal line, and the operand word is aligned j, merged and transferred to the cache memory.

The send data signal DSSND-DATA is used as a link = signal 1 issued when the decimal unit requests the next word from the execution unit. If the Descriptor describes a 9-bit decimal digit that is to be an operand for storage in the cache memory, then the send data signal is used as a link signal 1 occur in alternating cycles because two operand words in decimal units on each of Word recorded by the execution unit can be generated.

03O028 / O881

BATH ORIGINAL

■. C -> i J

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The decimal unit calculates the position of the most significant decimal digit within the operand word of the resulting operand, which is received by the execution unit combined to determine the number of decimal digits in the resulting operand which is accepted by the execution unit to be shifted in the decimal unit. This shift is stored in an RDSC register (730-58). The shift direction controls the sequence of the storage operation. "For a positive shift, for which the RDSCO signal is a logic signal zero, the sequence runs as described _{above o} In the case of a zero -Shift or in the event of a negative shift, the RDSCO signal appears as logic signal 1, which means that the above sequence must be delayed by one cycle until the data word of the highest order and the data word following this data word are stored in the decimal unit »

The store operation is terminated when the number of opprand words specified by the descriptor is from The execution unit is transmitted via the decimal unit, ρ is aligned in the relevant operand words and are desired, and if the relevant operand words are written into the cache «

The system also includes a decimal unit, di «while the processing of the decimal arithmetic instructions in operation and the one under the microprogram control the descriptors from the control unit and the further the Takes operands from the cache memory “In dor The operand characters from the zone bits and, if applicable, from the sign,

030028/0881

BATH

Exponent and non-operand characters freed and combined into words, di--? up to eight decimal digits per word include in order to an execution unit to be transferred. The operand word is different from the 4-bit decimal digit information Information freed in the cycle in which the operand word is processed by the decimal unit will.

The execution unit carries out the decimal calculation, which is designated by the instruction, specifically in response to the two operands, and also transfers the resulting one third operands to the decimal unit in the form of words consisting of 4-bit decimal digits.

The decimal unit processes the third operand as indicated by a descriptor describing the third operand. The descriptor ^{enables the link f j} device in the decimal unit during a store operation to mix the sign, exponent, zone bits and non-operand characters with the decimal digits and transfer the mixed words to the cache at an address specified by the Descriptor is designated under microprogram control. The information is shuffled into the operand word in the cycle in which the word is processed by the decimal unit.

The arrangement comprises a plurality of switches and j-jin directions to control the switch, lan 4- ^ ibenen-ZSMR switch (730-180) adds sign, exponent and non-operand characters (rewrite) to the operand when the decimal digits of the third operand are added by the processing unit, in the decimal unit processed and transferred to the cache memory.

030028/0881

BATH ORIGINAL

Level 0 of the ZSMR counter causes an expansion the 4-bit decimal digit from a 32-bit word to a 36-bit word. The leading or following signs are assigned to the operand via level 1 of the ZSMR switch added "A level 1 position of the ZSMR switch is selected when the descriptor is 4-bit characters and two adjacent ZSMR level 1 positions are selected when the Descriptor 9-bit characters designated The selection is made by the SIGNM output signals of the shifter (730-118).

The exponent is added to the third operand, as indicated by the descriptor, as Floating point operand, which is done via level 2 of the ZSMR switch (730-180) "Two adjacent signals on the link Input 0 of the EXPM slide device (730-122) selects the two EXPMO-7 output signals to control the activate both selected exponent positions of the following word of the third floating point operand »

The rewrite information is added to the leading word and the following word, if necessary, via level 3 of the ZSMR switch 740-180. The REWUM shifter (730-149) selects the non-opera positions of the leading operand word, and REWLM the shift means (730-114) selects the non-Operan denpositionen the following definition for transmission of Neuschreibinformation over the ZEWR switch (730-178) and the selected positions of the ZSMR switch (730-180) from ₀

During the load operation, doh »then if the decimal unit takes the operand from the cache for alignment, the sign and exponent signs become from the operands in the ZID switch (730-150) solved, under the control of the ZIDML sliding

030028/0811 BATH ORIGINAL

device (730 = 128) and the ZIDMU-Schiebeiarichtung (730 = 130) ρ xfodureh the information to the right of the decimal digit with the lowest value is masked in the word of the operand that contains the decimal digit with the lowest value ₀ In addition, the information to the left of the digit is the highest Value masked

During the loading operation, the ZCRBGM = SoM ebeeiarich- = tung (730 = 145) selects the St> ene = 2 = position of the ZID = ScMlter (730 = 150) for the replacement of the overlaid prefix = sign with the designated ddiscial digit in eine® ASCII or 2üBCDIC = 0peranden from _o about punched 2eiehen ~ £ Bezi aalgeicheH is © is single 9 ° Bii t / hich is encoded so that it _c aia Yorseiefeen and

The descriptor information stored in the decimal unit describes the properties of the operand _0. The descriptor bit position 21 defines the operand as an operand containing 9-bit characters in the event that a link value of 0 is present, and as a 4-bit character if a Link value of 1 is present. Bit positions 22 and 33 define the operands as follows:
Bit positions normal Overlapped sign

22j 23 Leading prefix Leading sign,
Floating point

0 0 Leading leading sign

sign, in scale scale

1 0 following subsequent sign,

Sign, in scale scale

1 1 no sign, subsequent sign

The length field, descriptor bit positions 30 to 35 and the scale factor field, bit positions 24 to 29

030028/0831

together with the field _S which is defined by dio bit positions 21 to 23 _s liofern The output signals indicate the set length dos Opera Dess field on _o the input signals for a ALMS = adder (730 = 24) ₀

A Yektorverzt / eigungs = switch gate (13-72) in the vector = branch logilt (730-15) gives signals PK ~ ¥ CTR 0 = 3 on the order © t © 5ä from Sigmlsn 1PKVCTR _P 2PKVCSR and 4PKVCTR out the certain DUCMD -Command signals and status ICaize pull signals are generated.

In response to a firmware request for the type length vector, the firmware's decimal unit indicates whether the Operand is a short operand or a long operand, whether there are 4-bit characters or 9-bit characters and whether if there is a short operand, an overlayed sign in the descriptor-1 operand or in the descriptor-2-0 operand is available.

On a firmware request for the descriptor 1 vector the decimal unit provides an indication in the event that operand 1 is a floating point or fixed value or a fixed value. Scale operand, an over-punched leading or trailing sign scale operand or which Firmware provides an indication that the descriptor 2 vector is to be carried out.

In response to a firmware request for the descriptor 2 operand, the decimal unit is returned an indication in the event that operand 2 is a floating point or fixed value or scale operand with a is overlaid leading or trailing sign.

030028/0881

"δ S ^

On the occurrence of the Firiawere request for the storage vector Mn, the Bssioaleinheit provides an indication ia. the case ₁ that the resulting operand is equal to zero or that there is an overflow _c

On the occurrence of a FirBMare request aaeh a long input selector Mn shows the decimal display the comparison between the operand lengths and 63 with regard to scale ™ or * fixed value operands, and also provides an indication of execution of the descriptor 1 and descriptor 2 vectors.

030020/0081

30000A5

"won Zsleteamgsa t-tfird as an invention

Figo 1 shows a main processor _{p with} which a gear storage unit and a system integration unit are connected

Figo 5 shows in a detailed block diagram a Figo 4 -gigt in a © ® Gesamtblockdiagrasasa the decimal = Figo 5 gsigt - Instr-Ätions »und Beskriptorf © mate £ Ur Figo € gsigt © in ^ © sfeaupfussgsdiagri ^ a of counting circuits

Figo 7 gsigt in © INSM wiring diagram effective i ^ nscnaltung © n _o
8 shows in a diagram a vector delay =

General description of the processor 70 0 ° Fig o 1

From FIG _o 1 ergichtlichj is that a main processor 700 an execution control unit 701, a control unit 704, an execution unit 714 _5, a drawing unit 72o _9, an auxiliary arithmetic and control unit (AACU) 722 ₉ a multiple = IUividiereinheit 728 and a decimal 730 containing this Units are interconnected as shown. In addition, the control unit 704 has a number of connections with the illustrated cache memory or scratch pad memory 750 at ₀

The execution control unit 701 includes an execution = Control store addressing = and branching in · =

called 701-1 and an execution control memory 701-2. The memory 701-2 and the unit 710-1 are via bus lines 701-3 and 701 = 6 in the manner shown interconnected

The control unit 704 contains a control logic unit 704-1, a control memory 704-2 _? an address formation unit 704-3 »a data = and address output circuit 704-4 and an XAQ register area 704 = 5 _s , the relevant devices being connected to one another in the manner shown, _{or the like}

The control unit 704 provides the necessary control for the execution of the address formation operations, the command call Z execution operations and the sequential control for the various cycles of operation and / or for the machine states “The control is through the logic circuits of block 704 = 1 and by the execution control unit 701 with respect to the different = those areas of the control unit 704 caused or »executed

The XAQ register region 704 = 5 contains a number of program Sichtregisternj, ifie index registers ^ an accumulator and a quotient register _o Other so-called program summary register or, for the Programmjsichtbare Re = gisterj, such as the program counter and the address register ₉ are in the address formation unit 704 = 3 included

As is apparent from Figure "1 _9, the area 704-5 accepts signals from the unit 704-3 on _o These signals _B which are characteristic for the content of the instruction counter enter via lines RIC 00-17o In addition, the lines ZRESA give 00-35 output signals from the execution unit 714 from ₉ , these output signals corresponding to the results of the operations carried out on different operands

030028/0881

iiTerden «Area 704 = 5 also takes an output from the auxiliary = rake = and control unit via the lines RAAUQ-8 to "

The area 704 = 5 indicates signals which are characteristic of the content of one of the registers contained in the area, the relevant signals as input signals for the address formation unit 704-3 via the lines ZX0 = 20 and ZXA 24 = 35 are issued ,, The address formation unit 704 = 3 outputs the information via a switch to the execution unit 714, namely via the lines ZDO 0 = 35o In a corresponding way, the Contents of certain registers of the registers contained in the area 704 = 5 to the execution unit 714 via the Lines ZEB 00 = 35 can be transmitted, finally the content of selected registers of these registers from the area 704 = 5 to the multiplication-division unit 728 can be transmitted over the lines ZAQ 00-35 =

The address generation unit 704 = 3 generates addresses from the contents of various registers contained in the relevant unit5 it outputs the resulting link addresses, the effective addresses and / or absolute addresses for distribution to the other units via the lines ASFA 00 = 35 ₀ The address generation unit 704 = 3 receives the results of operations that are carried out by the execution unit 714 with regard to two operands, namely via the lines ZRESB 00 = 35 ο The unit 704 = 3 receives the signals from the control logic unit that identify the content of two base pointer registers 704 via the lines RBASA and RBASAO = I aufo The output signals from the multiplication / division = unit 728 are transmitted to the address generation unit 704 = 3 = ultimately the content of a secondary command register (RSIR) is used as an input variable via the lines RSIR 00 = 35 to the a =

030028/0881

30000Λ5

called 704-3.

The data and address output circuits 704-4 generate the cache address signals corresponding to the respective Deliver circuits to cache memory unit 750 via lines RADO / ZADO 00-35. These Address signals correspond to the signals associated with a number of the series of input lines ZDI 00-35, ASFA 00-35 and ZRESB 00-35 are supplied, the relevant row being selected by switches that Included in the circuits of block 704-4 are word address signals over the lines ASFA 32-33 submitted «

Control logic unit 704-1 provides data paths that interface with various units contained in cache unit 705 are. The lines ZIB 00 = 35 represent an interface with a command buffer that is in the cache = memory 750 is included. The lines ZDI 00-35 are used for this, data signals from the cache = memory 750 to the control logic unit 704-1.

As can be seen from Figure 1, the control logic unit 704-1 provides a number of groups of output signals. These output signals contain the content of certain registers, for example a basic instruction register (RBIR), the content of which is supplied as an input variable to the control store 704-2 via the lines RBIR 18-27 will. The control logic unit 704-1 receives certain control signals from the control store 704-2 have been read out via the CCSDO 13-31 lines.

The control logic unit 704-1 also includes a secondary or second instruction register (RSIR), which parallel to the basic command register at the beginning of the

030028/0881

Processing of a command or an instruction loaded is «The content of the second command register RSIR 00-35 is, as mentioned above, as an input variable the address formation unit 704 = 3 supplied “In addition becomes part of the content of the relevant second instruction register as an input variable of the auxiliary arithmetic control unit 722 via lines RSIR 1 = 9 and 24-35 and the decimal unit 730 via lines RSIR 21 = 35 fed »

The control memory 704-2 is used, as explained here, for initial decoding of a program instruction opcode j, which is why the memory in question is designed in such a way that it contains a number of memory locations (1024) one for each possible command or where Instruction = operation code "

As mentioned, the signals given to lines RBIR 18-27 are fed as input signals to control store 704 = 2. These signals select one of the possible 1024 memory locations. The content of the selected memory location is sent to lines CCSDO 13-31 and CCSDO 00 = 12 delivered _p as illustrated in FIG. 1. The signals delivered to the lines CCSDO 00-12 correspond to the address signals that are used to address the execution control unit 704, as explained "

The execution unit 714 provides the instruction execution, the unit 714 rakes = and / or shift operators functions on operands out executes that out from the various input signals \ ^ are ählt _o The results of such operations are issued to selected outputs ,. The execution unit 714 receives data from a data input bus line which corresponds to the lines RDI 00 = 35, the signal source of which is the control logic unit 704 = 1 ₀ The contents of the

030028/0881

300004

Accumulator and quotient registers <contained in the area 704-5 are ₉ , as mentioned above _9, via the lines ZEB 00 = 35 to the execution unit 714, the output from the address generation unit 704 = 3 to the input bus lines ZDO 00- 35 ab = reproduced signals ^ x ground over in the execution unit 714 switches given as output signals to the lines ZRESA 00 = 35 and ZRESB 00 = 35 leave, as is illustrated in Figo 1 ₀ in addition, the execution unit accepts 714 · a series of note "Block memory = address signals from the auxiliary = arithmetic unit and control unit 722, which are output via the lines ZRESPA 0Q-Q6," In addition, the unit 722 sends shift information to the unit 714 via the lines ZRSC 00 = 35 from ₀

The drawing unit 720 to _P herangszogen the characters = command or instruction, as well execute ^ require such operations ^ as the translation and editing will be explained data fields As ,, these types of commands or _o instructions as extended instruction set instructions (EIS ) are designated o Such commands or _o instructions _p that the character unit 720 executes; include displacement = or move = ρ scanning = and comparison commands _o Signals identifying the operands are output via the lines ZRESA 00 = 35 The type of character position within a place and the number of bits are sent to the character unit 720 via the input lines ZDB 00 = 07

Information that is indicative of the results of certain data operations is transmitted via the lines ZOC 00-08 Such information supplied to unit 722 includes exponent data and data in hexadecimal format, the

Character unit 720 outputs output operand data and control information to unit 722 to which Unit 730 and to unit 728 via the lines RCHU 00 = 35 abο

The HiXfs arithmetic and control unit 721 carries out arithmetic operations on a tax information. off as on exponents used in floating point operations are calculated, where operand lengths and, pointers are calculated and counting information is generated ,, The Results of these operations are sent to execution unit 714 via lines ZRSPA 00-06 and via the Lines ZRSC 00 ~ 06 released as previously mentioned ! "/ orden isto The information signals that correspond to characters xtfie 9 = bit ~ character, 4-bit character, in decimal data converted input hexadecimal data, a quotient = Information and a sign information sent via the lines RAAU 00-08 to the area 704-5

As can be seen from FIG. 1, the unit 722 receives a number of input signals “The character pointer information is supplied or output via the lines ASFA 33 = 36”. Numerical scale factor information EiS is sent to the unit 722 via the lines RSIR 24-35 Other signals issued relating to the calling of special commands are issued via the lines RSIR 01 = 09. Exponent signals for floating point data are issued to the unit 722 via the lines ZOG 00 = 08, while floating point exponent data = signals from the unit 704-1 "sliding Zählinformationssignale be given the lines RDI 00 = 08 for certain commands or ₀ instructions (for example, for binary shift instructions) are" delivered to the unit via the lines RDI 11-17 With regard to the votes on the lines RCHU 00 = 35 input signals it should be noted that lines 24-35

Output signals ^ the length of the EIS command fields correspond, while lines 18-23 provide address modification signals to unit 722 ,,

The multiplication / Bivisions = unit 728 causes execution of multiply and divide instructions = ₀ at high speed This unit can be regarded as built in a conventional manner; they may have the shape of the multiplication unit, as indicated in the US = PS 40 41 292, is the unit 728, v / IE in FIG _o 1 indicated "takes multiplier ™, Dividend = and divisor input signals via lines RCHU 00 = 35 on o The multiplicand input signal from the register area 704 = 5 Xtf is fed via the lines ZAQ 00 = 35 ,, The results of the calculations carried out by the unit 728 are output as output signals to the lines ZMD 00 = 35 ,,

The decimal unit 730 is under firmware control during processing of the decimal numeric In = constructions effectively ₀ The instruction or command = format and its associated Deskriptorxförter will be explained in detail with reference to Figo 5 * The instruction word and the descriptor \ </ location information are received from the decimal unit 730 via the lines RSIR 21 = 35 and ASFA 33- = 36. The signals in question cause the decimal unit 730 _{9 to} receive the operand described by the descriptor word from the cache memory 750 via the line ZDX 0 = 35. The decimal unit 730 removes the sign and exponent = characters from the operand word, packs the data in up to eight 4-bit characters per word, stores the data in 32-bit words, aligns and transfers the data words to the execution unit 714 via the lines RDOD 00-35, ZMD 00-35 and ZDO 00-35. The data words stored in the cache memory contain up to four 9-bit characters of eight

03 0 028/0881

4 = bit characters in a 36 = bit = word _o The 9 = bit = character contains five zone bits and four data bits “The zone bits are separated from the 9 bit = character, and the remaining data bits are stored in a 32 = bit register a = led, which can contain up to zxtfei cache memory data words, which consist of 9 = bits = characters, or where a cache memory data word consists of 4-bit = characters processed with the decimal = numeric command The operand that represents the desired result of the numeric command is supplied to the decimal unit 730 via the lines ZRESA 00 = 35, the character unit 720 and then to the decimal unit 730 via the lines RCHU 4-35 the operand is processed in accordance with the coded information in a descriptor word. The operand is to a certain extent unpacErt, with the required signs and exponents are added, via the lines ZADSP 0-11, and wherein the EBCIDC = or = ASC11 Zonen2eichen be added if 9 ~ bit decimal point indicated by the coded information in the Deskriptorxrort ₀ Further, is again a Einspeicheruag in the cache memory 750 under an address which is identified by an address field in the descriptor word _o The data stored in the cache memory 750 via the lines RBOD 00 = 35, ZMD 00 = 35, ASFA 00 = 35 and RADO / ZADO 00 = 35 The decimal unit 730 is under Firnrorare = control via the lines MEM = DO 88, 89, 94 = 97ο The signals PK = VCTR 0 = 5 "Won of the decimal unit 730 show the execution addresses · = and branch circuit 701 = 1 the status information depending on Firmware = commands to _p that are received by the decimal unit 730 via the lines MEM = DO 88, 89, 94 = 97 _o The from the execution = Ädr essen- = and branching unit 701-1

* Λ 9.

Recorded signals PK-VCTR 0-5 lead in the execution control memory 701-2 to branch to a particular microprogram subroutine. The execution control store 701-2 associated branching logic is described in more detail elsewhere (see U.S. Patent Application, Serial No. 853 937).

The data and control signals are passed between cache memory 750 and a system interface unit Via the data interface line 600 and between the Cache 750 and processor 700 over the lines the interface device 704 transmitted. Finally, the cache unit 750 receives addresses and data signals from data and address output circuits 704-4 over lines RADO / ZADO 00-35 and via the lines ASFA 32-33.

Execution Unit 714 - FIG. 2

The unit 714 contains, as main units, addressable short-term register banks 714 = 10 and 714-12, an arithmetic logic unit (ALU) 714-20, a ^{shifter 0} 714-24 and a notepad memory 714-30. In addition, the unit 714 contains a number of data selection switches 714-15, 714-17, 714-22, 714-26, 714-28, 714-34, 714 = -36 and 714-38 µm which can be set to a plurality of positions to provide for flexibility in the selection of operands and output results _o

During operation, the operands are set using the ZOPA switch 714-15 and the ZOPB switch 714-17 from one of the Re = registers of register banks 714-12 and 714 = 10 or from other input lines, such as the services shown ZEBO-35 or RDIO-35 selected Die ALU = Ein ~ hext 714-20 and the sliding device 714-24 Operations on selected operands Mn, and the

Results are selected using switches 714-24, 714-36 and 714-38 to the output bus lines ZRESA 0-35 and ZRESB 0-35 »In a corresponding way the contents of a notepad space saved by the signals that have been output by the AACU unit 722 via the lines ZRSPA 0-6 is selected can be read using switches 714-34, 714-36 and 714-38 »

The selected output results, or other data is then loaded into the other registers within the processor 700, including the short-time register banks 714 and 714-12 = 10 or the scratch pad memory 714 to 30 of the execution unit 714 _O

In detail, the sources of the operands for both ZOPA and ZOPü switches 714-15 and 714-17 are identical The selection of the switch position for the ZOPA switch and for the ZOPB switch is under the control of the Microinstruction word “The ALU unit 714-20 performs logic operations Decimal and binary operations Operations on the selected operand data under the control of the microinstruction word from »

The shifter 714-24 is a combination link network which is used for this purpose, binary data align, move, or rotate under microprogram control The input data signals from the ZSHFOP and ZEIS switches 714-28 or 714-22 can be viewed as concatenated so that a single double word input signal is formed “The Slider 714-24 provides a 36-bit output signal, which is shifted in accordance with the shift counter position »The ZSHFOP switch 714-28 is controlled by the microinstruction word, while the shift counter setting is controlled by the sequence control Kor.stantenfeld of the microinstruction word is determined which

Ü30 020/0801

in a suitable manner via the auxiliary arithmetic control unit 722 is selected. For the purposes of the present invention, the ALU unit 714-20 and the Sliders 714-24 can be considered to be constructed in a conventional manner. The micro command fields, which control the operation of execution unit 714 are described in more detail elsewhere (see U.S. Patent Application, Serial No. 853 944).

The notepad memory 714-30 provides a working space for the storage of various data. those for the execution of certain commands or instructions as well as for various constants and Descriptor values are required. For example, the octal digits 10-15 are used to create a pressure preparation command table value required to perform print editing operations. Writing to the notepad memory 714-30 first involves loading the RSPB buffer register 714-32 with input data that are supplied via the ZRESB switch 714-38. During a next cycle, the content will of register 714-32 are written into the memory location designated by the signals that are on the lines ZRSPA 0-6 are output from the AACU unit 722. The registered mail takes place if that Bit 22 of the micro command word (RSP field) occurs as binary signal 1.

With regard to the other switches that have been mentioned, it should be noted that those supplied by the unit 714 Results via the ZALU switch 714-26, the BSPI switch 714-34, the ZRESA switch 714-36 and the ZRESB switches are issued under microprogram control. The Sehalter ZALU and ZSPDI are laying a first Selection level for the ZRESA and ZRESB switches, which define a final selection level. There the two

030028/0801

Switches ZRESA and ZFlESB have identical input signal sources, they can have the same output data deliver,,

Operands from the decimal unit 730 are received over lines ZDO 00-35 and selected RTRL O-3-registers 714-12 and RTRH registers 714 = 10 is stored as described above _o Lange operand are employed in the scratch pad memory 714 = 30 saved. The resulting operand is read out via the ZRESA switch 714-36 into the RCHO register 720-10 of the character unit 720 and into the decimal unit 730 via the RCHU 0-35 line »

Decimal unit 730 - General description - System

Referring to Figure 3, the decimal unit 730 operates under firmware control; it processes decimal-numeric commands and accepts data words from cache memory 750 made up of 4-bit characters or 9-bit EBCDIC or ASCII characters exist ,, The data word can contain a subsequent sign or a leading sign, which can be part of an overlaid mark; it also contains an exponent if the data word is part of a floating point operand.

The decimal unit 730 removes the sign and / or the exponent from the data word, compresses the data words from 36-bit words to 32-bit words, both packs 4-bit and 9-bit decimal digits in data words, consisting of 4-bit decimal digits are made up and transmits the resulting 32 »bit data words to execution unit 714 for processing as indicated by the instruction or is determined by the instruction "

The words most significant and least significant

of the operand picked up from the cache memory 750 can contain information that is not part of the operand. This rewriting information is stored in registers and assigned to the words of the highest and lowest values of the Operands are added if this is required during the storage operation.

The decimal unit 730 processes operands that consist of decimal digits and that are either short operands or are long operands. Short operands have a length of 15 decimal digits or a shorter length, Long operands have a digit length of 16 to 64 decimal digits. Operands with more than 64 decimal digits are not processed in the decimal unit 730, rather, they are processed by the firmware.

Short operands with one or two data words become the short-term registers RTRL 0-3 714-12 and RTRH 4-7 714-10 transferred in execution unit 714. Long three to eight word operands become the scratch pad memory 714-30 in execution unit 714.

The decimal-numeric commands include a command word which specifies the execution of an arithmetic operation, also a descriptor-1 word, which contains the properties of an operand 1, a descriptor 2 word, which defines the properties of an operand 2, and a descriptor 3-word, which the properties of a resulting operand 3. Some commands or instructions use the descriptor 2, to define the properties of the two operands 2 and 3. The command and descriptor formats are

illustrated in fig.

The decimal unit 730 takes place under firmware control Operands 1 and 2 from cache 750 erect, align, and transfer to execution unit 714. The two operands are used with regard to an impermissible sign or an impermissible digit checked. The resulting operand 3 is transferred from the execution unit 714 to the decimal unit 730, in which it is, as it were, unpacked from 32-bit data words to 36-bit data words, with ASCII or EBCDIC zone characters can be added for 9-bit words. If necessary, exponent signs and sign added. The operand-2 or the operand-3 rewrite information previously stored can be added. The operand is checked for zero / overflow states, rounded down or shortened, if necessary, and stored in the cache memory 750 again.

The descriptors defining the operands are in the RSIR register (not shown in the drawings) of the control logic unit 704-1. The RSIR bit positions 21 to 35 corresponding to the bit positions of the descriptors shown in Fig. 5 become the decimal unit 730 and stored in registers of this unit. The RSIR bit positions become 17-20 transmitted to the decimal unit as signals ASFA 33-36, which are also in a register in the decimal unit 730 can be saved.

As shown in Fig. 5, the descriptor fields are defined as follows:

ASFA 33 is the least significant bit of the address of the most significant word of the operand which specifies an odd or even word address.

03002? / Όββ1

ASFA 34-36

RSIR 21

RSIR 22-23

RSIR 24-29

RSIR 30-35

points to the digit position within the word most significant of the most significant Sign of the operand. shows an operand of 4-bit characters in the case that a 1 or 9-bit character is present at a zero, defines the operand type and the sign position.

00 leading sign, floating point or over-holed leading sign.

01 leading sign in scale.

10 following sign in scale.

11 no sign in the scale or the following perforated sign.

indicates the scale factor, i.e. the position of the decimal point. A negative one Number moves the decimal point to the left of the least significant digit. One positive number shifts the decimal point to the right of the least significant digit.

indicates the number of characters in the operand. The characters contain the decimal digits, Signs and exponents.

The firmware controls the decimal unit with the signals RCSR 88-89, 94-97. The signals represent output signals of the execution control memory 701-4. With the exception of the fields CLK, ZAM, MPYREG and DUCMD, the firmware word described in more detail elsewhere (see U.S. Patent Application Serial No. 853,944).

03OÜ26 / O881

-λ;

Table 1

Linkage

RCSR signals Description name of the

Firmware

88, 89 »94, 95, 96, 97 controlled signals

Type F CLK, ZAM, MPYREG

10 0 0.00 Set FMYDV if DUCMD-200

FP0P1D, otherwise zero

10 0 0 0 1 Select result = zero- DUCMD-201

Display 1

10 0 0 10 selection 0P1 = zero, DUCMD-202

OP2 = zero displays

10 0 0 1 1 Loading of STC MASK DUCMD-203

in RDOD

10 0 1 0 0 Selection of the DU-over- DUCMD-204

running and cancellation indicators

10 0 10 1 Reset the zero / over DUCMD-205

run test logic

10 0 1 10 Set FCMPJM, DUCMu-206

if FPOPlD

10 0 1 11 Not used

Type F DUCMD link name

11 0 0 0 0 Set FMVN if DUCMD-300

FP0P1D, otherwise zero

110 0 0 1 Read the operand via DUCMD-301

YOU

110 0 10 Delivery of the full charge DUCMD-302

permanent status

110 0 11 Saving the operand DUCMD-303

about YOU

110 1 0 0 Checking zero / overflow DUCMD-304

11 0 1 0 1 Transfer of data from DUCMD-305

RCHO to RPK

11 0 1 10 Loading of new enrollment DUCMD-306

data

11 0 1 11 Load the DU sign DUCMD-307

Register (RSGN)

1110 0 0 Loading the DU exponent DUCMD-308

Registers (REXP)

1110 0 1 Insertion of the rounding DUCMD-309

Constant in RD0D

11 1 0 10 Insertion of the leading DUCMD-310

Zero counting of the

Operands in RD0D

/ 00

Type F. 1 1 DUCMD 1 1 1 1 1 O O O 1 1 1 1 O 1 1 1

11 1110 11 1111

30000A5

description

Insertion of the operand word counter position in RD0D Not used

Selection of descriptor vector displays

Display memory op vector selection

Selection of long op vector ads

Link name

DUCMD-311

DUCMD-313 DUCMD-314 DUCMD-315

It should be noted that RSCR bit positions 88 and 89, the Type F field, defining the fields identified by the RSCR bit positions 94-97 are designated. If the field type F contains a "10", then the microword fields CLK, ZAM and MPYREG selected. If the field type F contains an "11", then the microword field DUCMD is selected.

DUCMD 200 sets the FMYDV indicator during a

Multiplication or division decimal

Instruction.

DUCMD 201 selects the ADSZ condition branch. DUCMD 202 selects the RRLTRD condition branch

show if the operand 1 is equal to zero,

and the RREQRD conditional branch indicator

is selected if the operand is 2

Is zero.
DUCMD 203 transmits the output signals RCHU30-35, which are in

the STC mask are saved to the RDOD-Re-

register 730-154.
DUCMD 204 selects the RRLTRD conditional branch indication

for an overflow and the RREQRD condition

branch display for an abort operation

tion.

DUCMD 205 resets the FCRD and FDOFL flags. DUCMD 206 sets the FCMPN flag if the FP0P1D-

Indicator set to link value 1

is.

3 O O ΰ 0 A

DUCMD 300 sets the FMV code, provided that

FP0P1D identifier for the link value 1 is set »

DUCMD 301 starts the operand load operation in decimal unit 730 _{or similar}

DUCMD 302 promotes the completion of the load operation by setting the flags FLDCOMPL and FRDP1 _{or the like}

DUCMD 303 starts the storage result in or through

the decimal unit 730 by setting the flags FOPSTR and FMSDRN.

DUCMD 304 sets the FCZO flag for a check of zero / overflow of the in the RCHO register 720-10 stored word,

DUCMD 305 sets the indicators FCZO and FRPK.

DUCMD 306 sets the FLDREWR flag and selects the RREQRD state branch display for an abort operation off,

DUCMD 307 causes the sign register RSGN 730-134 to be loaded.

DUCMD 308 causes the exponent register REXP 730-138 to be loaded and also to load the RSF3 scale factor register of register bank 730-4 during a floating point »FP0P3 cycle.

DUCMD 309 controls the loading of the rounding constant stored in the ZPK switch 730-150 the correct character position of the RDOD register 730-154 and sets the indicator FRCMD.

DUCMD 310 controls the loading of the leading zero count of the operand into the RDOD register 730-154.

DUCMD 311 controls the loading of the operand location counter = position in the RDOD register 730-154 "

/ 04

DUCMD 312 not used.

DUCMD 313 selects the descriptor 1 vector and

Descriptor 2 vector displays off and

sets the indicator FDVC1. DUCMD 314 resets the FCRD indicator and dials

the memory vector displays. DUCMD 315 selects long input vector displays.

The decimal unit 730 responds to the firmware requirements with the signals PK VCTR 0-3 given below.

Table 2 Vector branching data

PK-VCTR

0 12 3

Type length

0 0 0 0 Short operand and 4-bit data. 0 10 0 Short operand and 9-bit data

10 0 0 Short operand and (4 or 9-bit data) and perforated sign

110 0 Long operand

De scriptor-1 vector

0 0 0 0 Execution of the descriptor 2 vector 0 10 0 Descriptor 1 = floating point,

10 0 0 Descriptor 1 = perforated leading sign, true to scale

110 0 Descriptor 1 = over-punched following Sign, true to scale

Descriptor 2 vector

0 0 0 0 Descriptor 2 ^ floating point or perforated sign

0 10 0 Descriptor 2 = floating point

10 0 0 Descriptor 2 = perforated leading sign, true to scale

110 0 Descriptor 2 = punched subsequent sign, true to scale

030028/0831

300Q0A5

Vector branch data PK-VCTR
12 3

Memory vector

0 0 0 check for result = zero, overflow 10 0 floating point result = check result = ses = zero, upper course

0 0 Overpunched s leading sign · = output = signal - check for result = zero, overflow

0 Punched sign below = initial ~ signal - check the result = zero, overflow

Long input signal

0 0 0 Both operands are true to scale and the set length of the descriptor 1 ^ 63 and the set length of the descriptor 2463 as well as the perforated sign 10 0 Both operands are true to scale, with the set length of the descriptor 1 "L x 63 and the set length of the descriptor 2 <. 63 and a perforated sign are present ο

0 0 Both operands are true to scale and set Length of descriptor 1> 63 or set length of descriptor 2 > 63 »1 0 0 Execution of the descript © r ~ 1 vector and des

Descriptor 2 vector "

Predicted number of delay cycles for processing descriptor = 1 = or De scriptor-2 operands

Data words delay cycles

0 0 0 1 0

0 0 12 0

0 10 1 1

0 112 1

10 0 1 2

10 12 2

The following Boolean expressions illustrate the firmware selection of the vector branch data:

[j PKVCTR = FDUACT (DUCHM 315 + DUCMD 313 * FDCV1 + FRDP1 (DUCMD 313, DUCMD 314 DUCMD 315))

[2 PKVCTR = FDUACT (DUCMD 314 + DUCMD 315 + DUCMD 301 + DUCMD 313 * FRDP1)

J4PKVCTR = FDUACT (DUCMD 313 + DUCMD 314 + DUCMD 315)

! PKVCTR = 1

iPKVCTR = 2 or 3

[PKVCTR

[PKVCTR = 5

selects the type-length vector that indicates to the firmware whether the operand is a short or long operand, these are 4-bit characters or 9-bit characters, and whether, if a short operand is present, there is a perforated sign in the descriptor 1 or descriptor 2 operands is.

selects the number of delay cycles required for short operands are after the first read command to the cache memory 750 on the delivery of the first data word to the execution unit 714 was sent out. This prediction simplifies firmware processing of short operands selects the descriptor 1 vector that contains the Descriptor 1 is defined as a floating point operand, an operand with a perforated leading or trailing scale sign or indicates to the firmware to execute the descriptor 2 vector is.

selects the descriptor-2 vector that Descriptor 2 as a floating point or scaled operand with a perforated leading or trailing sign specifies.

Ö3UG2S / GSS1

105 3 O Ü O O A

PKVCTR = 6 selects the storage vector that the

Firmware indicates that a specific check regarding the resulting Operand is to be made that is equal to zero.

JPKVCTR = 7 selects the long input vector and

shows the firmware the comparison between the operand lengths and 63 with regard to scaled operands _o The vector also shows the firmware the execution of the descriptor 1 and descriptor 2 vectors,

The decimal unit 730 gives a number of conditional branch indications to the execution addresses = and branch circuit logic 701-1 from "

Condition Branch Displays Name Source

START WRT RRLTRD Send data RREQRD OPI = NuIl RRLTRD 0P2 = zero RREQRD Overflow RRLTRD Abort RREQRD Result = NuIl ADSZ Data AVA ADSZ CK-STR-VECT ZAMO

The RRLTRD signal is generated as follows %

1. During a DUCMD 202 instruction when the F0P1Z flag is set indicating that operand1 is zero _c

2. During a DUCMD 204 command, if the FDOFL flag is set, which indicates ₉ that an operand overflow has occurred,

881

30000 ^ 5

3. during a startup write operation to the firmware indicate that write commands are to be sent out to the cache memory 750.

The RREQRD signal is generated as follows:

1. During a command DUCMD 204 or DUCMD 306, the abort signal occurring as logic signal 1 and indicates that the lowest significant digits of an operand are lost,

2. during a DUCMD 202 instruction when the F0P2Z flag is set, indicating that the operand Is zero,

3. during a send data operation to indicate the firmware, that data is to be transferred to the decimal unit 730 from the execution unit 714.

The ADSZ signal is generated:

1. During a DUCMD instruction, if the operand is zero,

2. if data is not available, but with the exception of a DUCMD 201 command.

The ZAMQ signal is generated to test a memory vector function display like a floating point, a punched character, an overflow, result = null operand.

The condition branch displays are called by the firmware and they result in an execution control memory 701 -2- branch.

The description of the decimal unit status indicators follows, including the Boolean expressions for setting and resetting the indicators: F3DESC Set for processing operand 3,

which is determined either by descriptor 2 or by descriptor 3. The Boolean

? 30001U5

Expression reads:

F3DESC Set: (FPOP RDBSCO RDESC1J F3DESC reset: (FPOA)

FALT Set during the save operation in

alternative cycles. The decimal unit forms one word for the RDOD register 730-154 in one Cycle and transmit the word to execution unit 714 on the next cycle »by the set The FALT signal enables the storage of a word in the RDOD register. Of the Boolean expression reads

Set FALT ((DUCMD 303 + FOPSTR) FlEf.FPOT) reset FALT (FOPSTR ^e FALT + FPOA)

FCMPN Set for a firmware command DUCMD 206

regarding a comparison of a numerical instruction. The Boolean expression is % FCMPN set: (FP0P1D-DUCMD 206) FCMPN reset: (FPOA)

FCPCO Set when loading or saving

9-bit data words from odd addresses in the cache memory 750 are made. The Boolean Expression reads:

Set FCPCO: ((ZCPAO »(FDUACT« FRDP1 + SF0P2LD + FLDCOMPL ^ (DUCMd 303 + FOPSTR)) ■ '+ FCPCO. (F0P1LD.SF0P2LD

+ F0P2LD) »(FDID + FDFD) + FCPCO

• (DUCMD 303 + FOPSTR) STRDOD)

• FPOA)

FCPCO reset: (ZCPAO ° (FDUACT ' FRDP1

+ SF0P2LD + FLDCOMPL

.DUCMD 303 + FOPSTR)) + PCPCO • (F0P1LD.SF0P2LD + F0P2LD)

• (FDID + FDFD) + FCPCO

• (DUCMD 303 + FOPSTR) o SRDOD + FPOA)

FCRP1

FDADIS

Set during an operand load operation if one of the operands is long. This The second load DU operand instruction leaves the identifier CDUCMD 301) start a loading process. A long operand causes this Decimal unit to delete the first load DU operand instruction (DUCMD 301) to the firmware to allow it to be set to process a long operand. the Firmware always assumes a short operand operation. The Boolean expression is: FCRP1 Set: UDUCMD 301 »FRDP1. (D1EQQVP

+ D2EQ0VP + LONG)) FPOA) FCRP1 Reset: (FPOA)
Set by a firmware command DUCMD 305 or by an FCZO flag for a check zero / overflow operation, and reset by a command DUCMD 205 or 314. Remaining in the set state during the entire operation processing. The Boolean expression is:

Set FCRD: UDUCMD 305 + FCZO) FPOA) Reset FCRD: (DUCMD 314 + DUCMD 205 + FPOA) Set by a firmware command DUCMD 304 or 305 to check for zero / overflow of the word stored in the RCHO register 720-10. The Boolean expression reads:

FCZO Set: ((DUCMD 305 + DUCMD 304)) «FPÖÄ) FCZO reset: (SFCZO + FPOA) Set for 9-bit decimal digit operand loads in alternating cycles to get two 4-digit words from cache 750 and stored in the RDOD register 730-154 as an 8-digit word.

n3QO2Ö / O8Öi

FDATA-AV

The Boolean expression is;

FDADIS setting ((ZTNSAO »FRDP2 + ZTWSBO

• FRDP2). DATA-AV FPOA- SF0P2LX)) FDADIS reset (SFDÄDIS * (SRDI-PC + SFDFD

+ FDFD'RFDFD) + SF0P2LD)

is set to load the RDOD register 730-154 by controlling the sampling signal SRDODA. ₀ The Boolean expression is

FDATA-AV set (DATA-AV ° FPÜA) FDATA -AV reset SFDATA = AV + FPOA) is set during a load operation to indicate that the complete operand has been taken from the cache memory 750 by the decimal unit 730 "fe ₀ The Boolean Expression reads
Set FDFD (DFCO-FDID (RFDFD) -TOS (F0P1LD

• SF0P2LD -t- F0P2LD)) FDFD reset (FPOA + DFCO ° FDID · DTECO

"fSRDODA + DFCO ° FDID-FDTED + DTECO. SKDÜDA «FDFD)

Set if operand data in the RDID register 730-158 can be loaded. The Boolean expression üaitets

Set FDID ((SRDI-PC'FLDREWR ^ FRDPI) FDID reset (SFDID) Set if an operand overflow during determined by a check zero / overflow operation and reset by DUCMD 205 »The Boolean expression is?

FDOFL set ((DUCMD 305 + FCZO) οDOFL-FPÖÄ) FDOFL reset (DUCMD 205 + FPOA) Set when all decimal digits of the operand have been sent to execution unit 714 and not all of the operand information has been accepted by the decimal unit; For example, the exponent = or sign information, _etc.

FDUACT

FDZERO

The Boolean expression is: FDTED Set: (DTECO SRDODA (RFDFD) FPÖT • (F0P1LD'SF0P2LD + F0P2LD)) FDTED Reset: (FRDFD)
Set during FPOP control logic unit 704-1 cycle to indicate decimal unit 730 operation. The Boolean expression is:
Set FDUACT: (FPOP)
FDUACT reset: (FPOA)

Set when the firmware sends out a DUCM ⁰ 313 command after descriptor 1 information, so that descriptor 2 information is sent out in response to the next DUCMD 313 command. The Boolean expression is: FDVC1 set: (DUCMD 313'FPÖT) FDVC1 reset: (FPOA)

Set if the operand check with the check zero / overflow commands DUCMD 304 or 305 equals zero. The Boolean expression is: FDZERO Set: ((DUCMD 305 + FCZO) .DZERO'FPOT) FDZERO reset: (FPOA + (DUCMD 305 + FCZO)

. DZERO fcl5)

Set when the first word of the operand is loaded from cache 750 into decimal unit. The Boolean expression is:
Set FFDI: ((FDID'DFCÖ (F0P1LD + F0P2LD))

'WUK)

FFDI reset: (SF0P2LD + FPOA) Set when the first word of the operands in stored in RDOD register 730-154 prior to transfer to execution unit 714. The Boolean expression is: Set FFDO: ((SRDODA & (F0P1LD + F0P2LD)

• DTECO) -FPOA)
FFDO reset: (SF0P2LD + FPOA)

030028/0801

FFOSD

FILLY

FLDCOMPL

Set when the first data word to be stored in the cache = memory 7i? O in the RDOD register 730-154 is loaded. The Boolean expression is Set FFOSD ((FOPSTR + DUCMD 303) ° SRDODA

.FPOA)

Reset FFOSD? (FPOA) Set if an impermissible digit or an impermissible length is recorded by the decimal unit 730 vrirdo This signals an error to the system ₉ and the FLDGR flag is reset one cycle later The Boolean expression is:

Set FILLDIG ((SRDODA (FOP1LD + F0P2LD)

• DZIDEQID + ILLEGALLENGTH ° (SF0P1LD + FCZO)). (FLDGR + FPOA))

FILLDIG reset (FLDGR + FPOA) Set when both operands have been transferred to the _{execution unit 714 o} The Boolean expression is % FLDCOMPL set (((F0P1LD ° FMYN + F0P2LD

'FM!). (DFCO · FDID.DTECO ⁰ SRDODA + DFCO «FDID ° FDTED + DTECO ° SRDODA · FDFD) + DUCMD 302) -FPOA) FLDCOMPL reset (FPOA)

Set at the point in time at which the FILLDIG = identifier is included in the decimal unit 730, doho then, if an illegal digit or an illegal length is included there "FILLDIG is reset one cycle later _e The Boolean expression is?

FLDREWR

FLDREWRH

FMSDRGTE

FMSDRN

FLDGR set; ((SRDODA '(FOP1LD + F0P2LD) • DZIDEQID + ILLEGALLENGTH' • (SFQP1LD + FCZO)). FPÖÄ) FLDGR Reset: (FPOA)
Set by the firmware by a load rewrite data signal DUCMD 306 to start the sequence by which the first or last word specified by descriptor 3 in REWR 0-3 register bank 730-177 is stored. The Boolean expression is:
FLDREWR Set: (DUCMD 306) FLDREWR Reset: (DUCMD 306) Set one cycle after setting the FLDREWR flag to transfer the first or last word to register REWR2 or REWR3 of REWR O-3 register 730-177 during a descriptor 2 memory operation. The Boolean expression is: FLDREWRH Set: (FLDREWR) FLDREWRH Reset: (FLDREWR) Set during a memory operation in response to a firmware command DUCMD 303 if the word counter position in the RRWC register is greater than or equal to the word counter position in the RWPC register is at the time the command DUCMD 303 is used. The Boolean expression is: FMSDRGTE Set: (DMSDRGTE · DUCMD 303) »FÄLT

• \ DUCMD 303 · RRWCO + FMSDRN) .FPOA)

FMSDRGTE reset: (FPOA)

Set on the firmware command DUCMD 303, for the storage of a long Operands if the word count in the RRWC register is initially negative. The Boolean expression is:

030028/0881

_ 1

3OGU (KS

FOP1LD

FMSDRN Set: CDUCMD 303 RRWCO-FPOA) FMSDRN Reset: (FPOA)
Set during a memory sequence to store a long operand when the word count in the RRWC register is equal to the word count in the RWPC register. The Boolean expression is? Set FMSEQ: (DMSEQ (FSWRT.DMSDRGTE + FSWRT

• (ZTNSAO + ZTNSAO FCPCO))

• (DUCMD 303 + FOPSTR) .FALT

• (DUCMD 303-RRWCO + FMSDRN) .FPOA)

FMSEQ reset (FPOA)

Set for a numerical shift

Command (Move). The Boolean expression is:

Set FMVN: (DUCMD 300.FP0P1D)

Reset FMVN: (FPOA)

Set for multiplication and division instructions. This indicator is suppressed

the scale factor alignment and does the

Right-justified operands on a load operation

there. The Boolean expression is:

Set FMYDV: (DUCMD 200-FP0P1D)

FMYDV reset: (FPOA)

Set for the operand 1 load operation «Der

Boolean expression is:

F0P1LD Set: (DUCMD 301 «FRDP1.FPOA · (D1EQOVP .DJEQOVP LONG + ECRP1))

F0P1LD reset: (FPOA + F0P1LD.DFC0.DTEC0

»FDID.SRDODA + F0P1LD-DFCO ° FDID FDTED + F0P1LD-DTECO • SRDODA-FDFD)

Set if the operand 1 is equal to zero, _etc.

The Boolean expression is:

F0P1Z Set: (SRDODA-F0P1LD.DZIDEQZ »FPÖÄ)

F0P1Z Reset: (FPOA)

FOPSTR

FOP 2F

F0P2LD

000045

Through the Speieheroperand DUCMD 303 over

the firmware command of the decimal unit 730

set. The Boolean expression is:

Set FOPSTR: (DUCMD 303'FPOA)

FOPSTR reset: (FPOA)

Set for an operand-2 load, and for

the case that the first data word in the

RDID register 730-155 is included. Of the

Boolean expression is:

F0P2F Set: (FDID «FOP2LD.FPOA" * DFCT5)

F0P2F Reset: (FPOA + DFCO FDID)

Set for the operand 2 load operation.

The Boolean expression is:

F0P2LD Set: ((FOP1 LD FTITfJ. (DUCMD 301

+ FRDP2) · (DFCO.FDID · DTECO • SRDODA + DFCO · FDID.FDTED + DTECO. SRDODA.FDFD) ^ OPILD • FM · DUCMD 3O1.FRDP1) .FPÖT)

FOP2LD reset: (FPOA + F0P2LD (DFCO.FDID

• DTECO.SRDODA + DFCO · FDID • FDTED + DTECO · SRDODA · FDFD)) Set upon an operand 2 load operation when the second word in RDID register 730-158 is stored. The Boolean expression is: F0P2S Set: (F0P2F'FDID-FPUA) F0P2S reset: (FPOA)

Set when operand 2 is zero. The Boolean expression is:

F0P2Z Set: (SRD0DA «F0P2LD · DZIDEQZ-FPOA)

F0P2Z reset: (FPOA)

Set if operand 1 or operand 2

is designated as a floating point operand. Of the

Boolean expression is:

Set FPFL: ((D1EQFLT + D2EQFLP) FOP1LD »FP5A))

Reset FPFL: (FPOA)

030028/0831

FRDIDH

FRDP2

Set by a firmware command DUCMD 309 to read the rounding constant into the RDOD register 730-154. The Boolean expression is s Set FRCMD: (DUCMD 309 "FTOA) FRCMD Reset % (FPOA)
Set to indicate that the requested information 750 ge = is not in the cache memory stores and that the cache memory has to request this information from the auxiliary memory _c If the data is recorded in the cache memory and sent to the decimal 730, the FRDIDH linked = Plate the recovery signal for keying in the data in the RDID register 730 = 158 "The Boolean expression is:

FRDIDH set % ([SRDI-PC)
FRDIDH Reset? (FRDIDH) Is set by the firmware commands DUCMD 301 or DUCMD 302 to indicate that the command for reading out the first operand has been given to the decimal unit 730 ₀ The Boolean expression is %

FRDP1 set! ((DUCMD 301 (D1EQOVP ° D2EQ0VP • LOTiG + FCRP1) + DUCMD 302) ° FPOA)

FRDP1 reset? (FPOA)

Set by a Firmxvarebef ehl DUCMD 301 when the FRDP1 »flag is set to indicate that the command for reading out the second operand has been given to the decimal unit» The Boolean expression is:

FRDP2 set (DUCMD 301 ° FRDP1ofPÖA) FRDP2 Reset (FPOA)

FREWR2

F3DESC

FP0P3D

3Ü0Q045

Is set by the FLDREQRH flag in the cycle that follows the setting of the FLDREQRH flag. The identifier is used to cause the rewrite data to be read out from REWR2 and REWR3 during the operand storage process. The Boolean expression is.
FREWR Set: (FLDREWRH.
FREWR Reset:
Is set by the two set indicators FREWR and FLDREWRH. The command causes the REWR3 register to be used to provide the rewrite data for the last word of operand 3. The Boolean expression is: FREWR2 Set: (FLDREWRH · FREWR.FPÖÄ) FREWR2 Reset: (FPOA) Is set for the descriptor 3 operation. The Boolean expression is:

F3DESC Set: (FPOP'RDESCO-RDESC1) F3DESC Reset: (FPOA) Is set for the cycle that follows the FP0P3 cycle of the control logic unit 704-1. The Boolean expression is:

FP0P3D Set: (FPOP RDESCO RDESC1)

FPOP3D Reset: (FPOA + FP0P3D (DUCMD

+ FCZO))

Is set for the status that the set length, the length plus the scale factor difference, is greater than 63 characters. The Boolean expression is: FPTL Set: (ALNSLTE63 FOP1 LD I ⁵ PC) S) FPTL Reset: (FPOA)
Is set to a data transfer command DUCMD 305 from the RCHO to RPK firmware command and for short operation storage

FSSFD

FSWRT

FP0P1D

r η ■ -. λ / ι ~ UU .. ^: J η

exploited The Boolean expression is? FRPK set? (DUCMD 305 ⁰ DIEQFLPoFPOA) FRPK reset? CFPOA + DUCMD 205) Is set when the send data bit is sent as a 1-bit _o The send data indicate to the firmware that a new word is to be loaded into the RCHO register 720 = 10 while a long operand is being saved ₀ Das FSND = * identifier causes the word previously stored in the RCHO = register ge = to be keyed into the RPK = register 730 = 162, the Boolean expression is? FSND set (FALTοSEND = DATA ° FPOA)

FSND reset? (FALToSEND = DATA + FPOA) Is set if the scale _{factor difference is negative 0} The Boolean expression is; FSSFD set? (ASF2o FDUACT = FRDP1) FSSFD reset? (ASF2 · FDUACT.FRDP1 + FPOA) Is set if the signal STRT = WRT for the firmware is output as a 1 signal. The signal STRT = WRT is the firmware released to coincide with the release voft write commands to the cache memory 750 during the procedure to start _s the storage of a long operands concerns "The command FSWRT is the DU hardware controller about it in = formed, that the firmware issues write commands o The Boolean expression is? B ¹ SWRT set? (FTCToSTRT = WRT = (DUCiVlD 303

+ FOPSTR) ° FPOA) FSWRT Reset? (FPOA) Is the Boolean expression set for the cycle that follows the FP0P1 cycle of control logic unit 704 = 1?
FP0P1D set? (FPOP · RDESCO · RDESC1) FP0P1D Reset? (SFP0P1D)

^ήή *

FTDBO Are set as a 2-bit counter to indicate the number of FTDB1 delay cycles for keying

of the operand word in the RI) OD register 730-154 to be counted down for a transfer to

the execution unit 714. The Boolean expression is:

FTDBO Set: CTDBO'DUCMD 301.FPÖA) FTDBO Reset: CTDBO.DUCMD 301 + (FOP1LD

+ F0P2LD) .DUCMD 301 · SRDI-PC + FPOA) FTDB1 Set: ((TDBl-DUCMD 301 + FTDBO

• (FOPlLD + FOP2LD) -DUCMD 301 • [$ RDI-PC) -FPOA) FTDB1 Reset: (tdbI · DUCMD 301 + FTDBl

• (FOPlLD + F0P2LD) · DUCMD • [$ RDI-PC + FPOA)

FZCF Is set during the operand loading procedure when the first non-zero character is determined in the input data. It indicates the end of the number of leading zeros in the operand.
FZCF Set: ([$ RDODA · (FOPlLD + F0P2LD)

FZCF Reset: (SF0P2LD + FPCA))

The following are the Boolean expressions for functions not previously described:

SFCZO »(DUCMD 305 + DUCMD 304) · If ¹ POA

SFDADIS - (ZTNSAO «FRDP2 + ZTNSBO-FRDP2) · DATA-AV · FPÖÄ • SF0P2LD

SFDFD »DFCO · FDID · (RFDFD) -FPOA

SFDÄTA-AV - DATA-AV-FPOA

[SRDI-PC ■ ENABIZ + FTRF + FMT- (SRADOL- (RDIN.EQ. (1-11)) + TYPE · (MISREG.EQ.4) + TYPD- (IBUF.EQ.3)) + FMT ((IBPIPE.EQ.1) -PE12 + TYPBD (2) (MSKD.NEQ.0) + TYPBD (3) -STL) + FREQCA- (RMEM.EQ. (8-10)) + FREQDI + FDIDBL

030028/0331

- U

/ 11B 300004

SFDID «[$ RDI-PC · PIiDRBWR» FRDPl

DOFL indicates an overflow condition

DZIDEQID «(ZID4- (ZID5 + ZID6)) + (ZIDB- (ZID9 + ZIDlO)) + (ZID12 (ZID13 + ZID14)) + (ZID16 (ZID17 + ZID18)) + (ZID20 (ZID21 + ZID 22)) + (ZID24 • (ZID25 + -ZID26)) + (ZID28 · (ZID29 + ZID30)) + (ZID32- (ZID33 + ZID34))

ILLEGALLENGTH «ALNDAO + ALNDBO + ALNDAZ + ALNDBZ

DZERO indicates that the operand word contains only zeros »Decimal Unit - Logic

The scale factors for the operands 1, 2 and 3, also referred to above as scale factors, are recorded in the decimal unit 730 via a 4 = position switch ZSFN 730-2 from the control logic unit 704 = 1, namely via the signal lines RSIR 24 = 29 “Die scale factors in question are stored in the registers Rsfo, RSF1 or ₀ RSF2 the register bank 730 = 4 the signal lines ZÄDSP 3-11 indicate the scale factor to the position 1 of the switch then off when the scale factor is calculated by the firmware _o the signal lines ALNDA give set length of the operands at the position 2 of the switch during a floating point operation from ₀ the signals AEDC and ZEDC be _s supplied to the position 3 of the scarf = ters save su to the number of effective digits during a floating point operation ,, This process is as part of the Speicheropesation described in detail

The control signals 1ZSFN and 2ZSFN v / ground the scarf = settings 730 = 2 selected "The Boolean expressions are ί

= ((F3DESC + FMVN) FLDCOMPL ° FPÜP ° (D1EQFLP

+ DUCMD 305 + FCZO)) J2ZSFN = ((F3DESC + FMVN) -FLDCOMPL ⁰ FToF ⁰ DIEQFLP)

Ö30Ö2Ö / 08B1

-ys-

The Qperand-2 scale factor is used for non-floating point operands selected by the RSF1 position of a ZSFB switch 730-8 and an input of an ASF adder 730-10 supplied, in which the operand-2 scale factor of the Operand 1 scale factor is subtracted from the RSFO position of a ZSFA switch 730-6 is selected. If the operand 1 scale factor is greater than the operand 2 scale factor, then the signals are ASFO-9 indicative of a positive number, and the bit position ASF2 is given by a logic 0 signal. If the If the operand-2 scale factor is larger, the signals ASFO-9 identify a negative number and the bit position ASF2 carries a logic signal 1.

The length or the number of numeric characters for the operands 1, 2 and 3 is determined via the signal lines RSIR 30-35 received by the control logic unit 704-1 and in the registers RLNDO, RLND1 and RLND2 of a register bank 730-12 saved. An ALNDA adder 730-18 and an ALNDB adder 730-20 calculate the number of decimal digits in operand 1 or in operand 2. This is done by adding the number of non-digit characters in the operand, such as the sign and exponent, is subtracted from the length. The output of a decoding logic 730-38 and decoding logic 730-40 becomes an ALNDA adder 730-18 and an ALNDB adder 730-20, respectively to set the lengths of operands 1 and 2.

The sign and decimal type for operands 1, 2, and is received via the signal lines RSIR 21-23 from the control logic unit 704-1 and into the register RTNSO, RTNS1 or RTNS2 of register bank 730-32 loaded. A ZTNSA switch 730-36 selects this in the RTNSO register Operand 1 signs stored and those in this register stored decimal type and outputs the relevant information to the decoding logic 730-38. An under-

300004

An unsigned operand or operand provided with a scale factor leads to a zero = output signal, while a signed operand with a scale factor results in a 1 = output signal; a Floating point operand with 9-bit decimal digits leads to a 2-output signal, and a floating point operand with 4-bit decimal digits results in a 3-output signal from the decoding logic 730 = 38 "The output value \ fird of subtracted the operand 1 length in the ALNDA adder 730 = 18, in order to add the signals ALNDA 0-6 as the output variable which indicate the number of decimal digits in the operand 1. The number of decimal digits in the operand 2, which are indicated by the signals ALNDB 0 = 6, is calculated in a corresponding manner

The signals DBITX and DBITZ indicate as logic signals 1 that a binary signal 1 from the ALNDA adder 730-18 or from the ALNDB = adder 730 = 20 is subtracted. The Boolean expressions are loud

DBITX = ((ZTNSA1 »ZTNSA2) + (ZTNSAO · ZTNSA1 ° ZTNSA2)) DBITZ = ((ZTNSB1 »ZTNSB2) + (ZTNSBÜ * ZTNSBT ^ ZTNSB2) 7

The signals D1EQFLP and D2EQFLP indicate as logic signals 1 that a binary two from the ALNDA = Addie = rer 730-18 or subtracted from the ALNDB adder 730 = 20 will. The Boolean expressions are

D1EQFLP = (ZTNSA1-ZTNSA2 (ZTNSAO + ROP1)) D2EQFLP = (ZTNSB1 »ZTNSB2 ° (ZTNSBO + ROPT))

R0P1 indicates an overlaid sign command _{or similar}

A ZALND switch 730-22 selects the set length of the operand with the larger scale factor and sends the output signal to an ALNS adder 730 = 24, which adds the relevant signal to the absolute value of the scale factor output signal ASF 0 = 9 Ue a adder

ASF 730-10 added. The bit position ASP2 selects the operand with the larger scale factor. the Bit position ASF2 indicates, when it carries a logic signal 1, that the operand-2 scale factor is bigger.

From the output of a ZLMADJ switch 730-26, the set Length one ARWC counter 730-60 and one ACPR counter 730-62 supplied. The inputs or input signals for the ZLNADJ switch 730-26 are described below.

If the operand 1 scale factor is larger, then choose the switch turns off the input signals ALNS 0-9 for the operand and the input signals ALNDB for the operand 2. if the operand 2 scale factor is larger, then the selects Switch off the input signals ALNDA-0-6 for operand 1 and the ALNS input signals for operand 2. A Floating point operand or a multiply or divide instruction therefore does not require scale factor alignment, where the input signals ALNDA 0-6 and ALNDB 0-6 for operand 1 and for operand 2, respectively to be selected. The input signals RLZC1 become during the occurrence of a floating point memory operand selected; they provide the number of leading zeros in the operand.

The control signals 41ZLNADJ and 42ZLNADJ select one of four positions of the ZLNADJ switch 730-26. The Boolean expressions are:

[IZLNADJ - (FLDCOMPL.FRDPl. (FSSFD + FMYDV + 'DlEQFLP + 4 D2EQFLP + ALNS2) + vLDCOMPL (F3DÜSC + FMVN) · DlEQFLP · FDOFL)

[2ZLNADJ - (FDOACT-FRDPl-ÄSF2 ~ + FRDP1-FSSFD)

DlEQFLP. D2EQFLP + ALNS2 FLDCOMPL

+ FLDCOMPL- (F3DESC + FMVN) .DlEQFLP + DlEQFLP -FDOFL)

030028/0831

■■ ■ ■ 1Z3 300004

If the output signals of the ALNDA adder 730-18, of the ALNDB adder 730-20 and the ALNS adder 730 = 24 are all given by fifteen decimal digits or less, then this indicates that there are no floating point decimal instructions are or will be executed in short operand mode. This mode of operation leads to an increased System throughput with regard to the processing of decimal commands compared to the known arrangements, since most of the operand manipulation takes place using a logic arrangement, which executes many of the operand setting functions in parallel. There are many in the previously known arrangements of the functions executed serially «The Boolean The expression for the short operand is

Short = (ALNDAl.ALItDJQ *) (ÄLNDBl.ALMDB2) (ÄLNST = ÄLNSl • ALNS5 + FMYDV) (DlEQPQ? + D2EQFLP)

It should be noted that the scale factor = A ~ Position for multiplication = or division instructions or commands is not executed «

The ARWC adder 730-60 calculates the number of words those to execution unit 714 for short and long Operands to be transmitted o The ONE / ARWCB signal is fed to the minus input of the ARWC adder 730-605 if this signal occurs as logic signal 1, it is taken from the signal relating to the set length ZLNADJ 0-9 subtracted for a load operation This ensures that if the set length is Like it is indicated by the signals ZLNADJ 0 = 9 = was given by eight decimal digits, which means that the Signal ZLNADJ 6 a 1 signal v / ar, a one subtracted which causes the bit position ARWC6 to be zero and which loads the eight decimal digits into the first word will. Disregarding the bit positions ARWC7-9, the bit position 1RWC6 remains, which is the number of

0300 ^ 1/0011

Indicates words for the short operand. A one in bit position ARWC6 indicates a short operand of two words and a zero indicates a short operand of one word. The Boolean expression for the control signal ONE / ARWCB is:

[ONE / ARWCB - (FLDCOMPL + (ZTNJJAI {rOpI + ZTNS'AO

+ ZTNSA2)) + "(E ¹ RPK * ZLNADJ7 · ZLNADJ8 • ZLNADJ9 'FLDCOMPL))

The output signals ARWC 0-6 show the number of words in the operand available to the firmware when the execution control memory 701-4 has a firmware word which is decoded in the decimal unit 730 as a command or signal DUCMD 311 (add operand word counter setting into the RDOD signal). In addition, the word count is set via a ZLZC switch 730-76, via position 3 of a ZID switch 730-150, via which Position 0 of a ZDOD switch 730-152 for an RDOD register 730-154 is made available from which the relevant counter position to the execution unit 714 is transmitted.

The ACPR adder 730-62 subtracts the set length in decimal digits, which is indicated by the signals ZLNADJ 0-9 are decoded by the decimal value 64. The size 64 represents the maximum number of digits in an operand that processed by the decimal unit 730. The resulting output signals ACPR3-9 give the number of zero digits to the left of the most significant digit position for the 64-decimal-digit operand. This value will stored in an RLMP register 730-102. The bit positions RLMP4-6 store a binary code that represents the Indicates the number of significant positions in the first word of the operand recorded by the decimal unit 730 has been taking these positions to zero

03ÖÖ26 / 08Ö1

are doing. The signals RLMP 4-6 are used by a ZIDMU sliding device 730-130 fed «The number of high-order digits to the left of the Most significant digit positions that are to be set to zero are determined by the number of consecutive Signals are displayed that begin with the ZIDMU signal, which are output as zero signals. the Signals ZIDMU 0-7 are sent to an EZID link control device 730-132 delivered. The output signals EZID 0-7 suppress the output signals of the ZID switch 730-150 to zero, and also give it the digit positions of the ZID switch 730-150 starting with the digit position of the highest value are free. Of the Part of the RLMP register 730-102 which stores the bit positions RLMP 0-3 has the property of each Operand word to be increased or incremented, which is based on the decimal unit 730 on the Signal CNTUP-RLMPU is recorded * The Boolean expression is:

[CNTUPRLMPU »((FOPlLD + FOP2LD) · [$ RDODA-SFOP2LD) The Boolean expression for the ONE / ACPNBB signal is?

[ONE / ACPNBB - (ZTNSAl (ROTT + ZTNSAO + ZTNSA2) ((FDUACT.FRDPl) + FLDCOMPL-

• ZLNADJ7.ZLNADJ8.ZLANDJ9)) + (ZTNSBl (ROPl + ZTNSBO + ZTNSB2)) (FRDPl

• FLDCOMPL))

An ATMP adder 730-30 calculates the number of zeros to the right of the least significant digit of the operand with the larger scale or scale factor. The ZASFB switch 730-28 selects the set Scale factor binary signals ASF 0-9 from the size added if the operand-2-scale factor is larger, or there is a subtraction from size 63 if the operand 1 scale factor is larger.

030028/0881

The output signals ATMP 3-9 are stored in an RTMP register 730-100 loaded. The bit positions RTMP 0-3 store a binary count of the number of Words of the operand to the left of the word that has the digit position of the lowest significance. the Bit positions RTMP4-6 store a binary number which indicates the bit position of the lowest significance. The signals RTMP 4-6 indicate the number of zeros to the right of the least significant digit.

A comparator 730-104 compares the signals RTMP 0-3 and RLMP 0-3. The difference, which is equal to the number of Words of the operand is received from cache 750 by decimal unit 730. The binary word counter position RLMP 0-3 is increased or incremented every time a word of the operand is inserted into the RDOD register 730-154 is loaded. The difference between the binary signals RTMP 0-3 and RLMP 0-3 is Zero if the last word of the operand is included in the decimal unit 730, causing the output A = B of the comparator 730-104 is enabled. This makes the output signal TMSC 0-3 of the TMSC logic controller 730-106 released; this output signal is a binary counter signal of the number of zeros on the right side of the lowest significant digit. This counter setting becomes the TMSC link controller 730-106 fed by the RTMP 4-6 signals. The counter setting TMSC 0-3 becomes a ZIDML shifting device 730-120 supplied. The number of low-order digit positions to the right of the Least significant digits to be set to zero are determined by the number of consecutive Signals displayed that are brought to zero starting with the ZIDML signal. The signals ZIDML 0-7 are to the EZID 0-7 link controller 730-132 submitted. The output signals EZID 0-7 give the

030028/0881

Ill

30000A5

Signal states of the signals ZMIDL 0-7 and indicate the positions of high significance of the ZID switch 730-150 free, which means the lower significant positions on the right side of the digit are lowest Valence can be made zero.

The signals ASFA 33-36 are received by the address generation unit 704-3 for the operands 1, 2 and 3 and stored in the registers RCPO, RCP1 and RCP2 of a register bank 730-42.

The ASFA 33 signal indicates the least significant bit of the cache 750 address of the high order word of the operand, indicating whether this word comes from an odd or an even number Memory address space originates. This display is used when clustering operands with 9-bit characters that are in the decimal unit 730 are included, with 4 decimal characters per word up to 8 decimal characters per word, which is passed to the execution unit 714.

In the case of 9-bit character operands, the signals ASFA 34 and 35 show the position of the leading character in the high significance word of the operand. ₀ In the case of 4-bit character operand words, the signals ASFA 34 = 36 show the position of the leading character in the word high significance of the operand.

The operand pointer stored in the RCPO register is set via the RCPO position of a ZCPA switch 730 = 44 selected and fed to a ZCPNB switch 730 = 48. The position ZCPA 0-2 of the ZCPNB switch 730-48 is selected if the operand 1 contains 9-bit characters, and the position ZCPA 1-3 is selected if the operand has 4-bit characters. The OME / ACPNBB signal

030028/0831

Hi 3QÜÜÜ45

is fed to one input of the ACPNB adder 730-50 and, in addition, 0-2 is added to ZCPNB if operand 1 has a leading sign. this will indicated by the 1 bit of the RTNSO register as a zero bit. The output signal ACPNB 1-3 of the adder shows to the decimal digit position of the highest order of the word of high order of the operand 1, if this in decimal unit 730 from the cache storage unit is recorded here.

An ACPDF adder 730-52 subtracts the high order digit from the output signal ACPR 7-9 of the ACPR adder 730-62. A binary signal ACPR 7-9 shows the number of zeros to the left of the most significant digit in the high-order operand word, to be transmitted to execution unit 714. The subtraction of the binary signals ACPNB 1-3 from ACPR 7-9 in the ACPDF adder 730-52 leads to the output of a binary value output signal ACPDF 0-3, which is the size of the Is an operand that is picked up by cache memory 750 and shifted to be properly is aligned to be transferred to execution unit 714. This shift value is in a RDSC register 730-58 stored via switch 730-56. The output signal of the RDSC register 730-58 is transmitted via a ZDSC switch 730-72 delivered to a sliding device 730-156. The ACPDF adder 730-52 does a calculation separately for operand 1 and operand 2 and aligns the operands relative to one another, in order to be able to carry out numerical processing in the execution unit 714.

A ZCPWC switch 730-46 selects the operand character pointer for 4-bit and 9-bit character opepands from and gives the pointer in question to an ACPWC adder 730-66, in which a magnitude is subtracted from one

30OiJC

is, lim an output signal ACPWC 0 = 3 to Ii "A ZLNT switch 730-64 selects the operandea 1 length for loading operand 1 and the 0perands = 2 = length for loading operand 2 for the purpose of Input to an ASWC adder 730-68 from ₉ in which the relevant variables are added = added to the binary signal ACPWC 0-3 =, A ZSWC = switch 730-70 selects a switch position ASWC 0 = 4 for a 9-bit = character -Operands and a switch position ASWC 0-3 for a 4-bit character operand and outputs the binary output signal ZSWC 0-4 for storage in an RSWC = register 730-110.

The RSWC register 730 = 110 stores a binary count the number of words in the operand going from cache 750 to decimal unit 730 is transferred. The counter setting in the RSWC = register 730-110 is then changed by a signal CNTDWN = RSWC decreases when a word is included in RDID = register 730 = 158. The Boolean expression for the signal reads

[CNTDWH-RSWC ■ ('[LDROTC "(FDID. (FOPlLD + F0P2LD)

»Src © +. [$ RDODA ° (DUCMD 30 3 + FOPSTR))) [LDRRWC - (PDUACT "fSBFT + SF0P2LD

+ FLDCOMPL- (FOPSTr + DUCMD 303))

DFCO * IgWCTo ^ IcT = ISWcTo RgWcir »RgWcT [SRDODA β (FDATA = JW + DUCMD 20 3-! DUCMD 310 + DUCMD 309 + FRPK DUCM) 30 3 + FRPK-FALT • FSWRS) ο DUCMD 311

The RSWC = register 730 = 110 indicates, at zero, that all words of the operand have been taken up by the decimal unit the DFCO- = output signal sets the FDFD = identification = character in the status indicator = control logic 730 = 202 "

0300

The ARWC adder 730-60 gives the output signals ARWC 0-6 which are stored in an RRWC register 730-88 when the LDRRWC signal is a logic 1 signal. That RRWC register 730-110 stores the number of words in the operand given to execution unit 714 during the load operation is to be transferred. Every time a word of an operand is in RDOD register 730-154 is loaded, the contents of the RRWC register 730-110 reduced by one if the signal CüTDWN-RRWC is a logic signal 1 is. The Boolean expression is:

[CNTDWN-RRWC "(DTECO. (FOPILD + F0P2LD) * [$ RDODA + ((FOPSTR + DUCMD 30 3- (DMSdRÖTE + (DMSEQ.RDSCO))) - FALT- (FSWRT

• DMSDRGTE + (ZTNSAO · FCPCO + ZTNSAO)

• FSWRT)) «FRPK + FRPK-DUCMD 30.1

• (ZTNSAO · FCPCO + ZTNSAO)) DTECO - RRWCO · RRWCl · RRWC2 · RRWC3 · RRWC4 · RRWCf

The RRWC register 730-110, at zero, indicates that all of the decimal digits of the operand are sent to the execution unit have been sent out by the DTECO output signal by adding the FDTED identifier in the StatusKeimzeichen control logic 730-202 is set.

The FOPILD flag is set by the firmware, which triggers the output of a DUCMD 301 signal. This indicates an operation that involves reading an operand using the decimal unit. The F0P1LD-Kennze? 'Is chen reset when the output signals DFCO and DTECO show that the two registers, ⁴ namely the RSWC registers 730 to 110 and the RRWC registers 730 to 88, while the operand-1-load operation on Have been reset to zero. The FRDP1 flag series indicates that the DUCMD 301 command has been issued to the

ÖIÜÖ28 / Q881

3 O C 0 04

Read operand 1 via decimal unit 730,

The F0P2LD flag is set by dip firmware, to read operand 2 if the DUCIO command has been issued with the FRDP1 flag set o The F0P2LD flag is reset and the FLDCOMP flag is set to indicate that the load operation is completed when the two registers RRWC and RSWC during the operation ~ 2 = operation have been reset to zero, meaning that both operands 1 and 2 are processed in decimal unit 730 and transmitted to the execution unit 714 have been,,

An RLZCI register 730 = 96 and an RLZC2 register 730 = 98 are used to indicate to the firmware the number of zeros to the left of the non-zero digit of the highest significance in operand 1 or in operand 2, the register_ places RLZC1 1 = 3 and RLZC2 1-3 are loaded with the output signals ÄRWÜ 4 = 6 of the ARWC counter 730 = 60. This means that the word counter part of the registers RLZC1 and RLZC2 • is biased, with the bit positions RLZC1 and RLZC2 0-3 with the value of seven words minus the number of words that are to be sent to the execution unit (binary value of the bit positions ARWC 4 = 6 of the ARWC counter 730-60), xtfo when equated with the number of words that are not The number of leading zeros to the left of the respective operand is determined at the output of the switch ZID 730 = 150. The signals ZID 04 = 35 are sent to the load zero counting logic 730-132 en, and the output signal LZC 0 = 3 indicates the number of leading zeros in the word at ₀ The signal LZCO indicates as one that all decimal digits

of the word are zero; a one is added to the registers RLZC1 or RLZC2 in bit position 3, and the next word is picked from cache 750. If the word contains all zeros again, if the signal LCZO is a 1 signal, and a one is again added to bit position 3 and further the next word from the cache memory 750 is picked up. Assume that the next from the Cache 750 recorded word does not contain all zeros. In this case the signals LZC1-3 show the Number of zeros to the left of the first non-zero decimal digit. This becomes the FZCF license plate is set, indicating to the logic that the zero for the left counter position with respect to this Operand is completed. This counter will be via a ^ n ZEDC switch 730-82 to the registers RLZC1 and RLZC2 transmitted and stored in the bit positions RLZC1 4-b and RLZC2 4-6 for the operands concerned.

Those in the RLZC1 register 730-96 and in the RLZC2 register 730-98 stored binary values represent the counting or counting of the number of decimal digits to the left of operands 1 or 2 to fill in 64 decimal digits in the execution unit 714 are reserved for each operand.

The output signals of the registers RLZC1 and RLZC2 are controlled by the firmware via position 3 of a ZLZC switch 730-76 fed to the RDOD register 730-154. The input signal ARWC of the ZLZC switch 730-76 is the number of words ready to be transferred for a long operand. The input signal ATMP provides the word storage space to which the rounding constant is added. The RCZC1 register 730-96 and the RCZC2 register 730-98 for the purpose of loading the The following Boolean expressions controlling register positions of the relevant registers are:

030028/0881 ORiGINAL BATHROOM

¹³⁶ 300-045

(5RLZClL - ([$ RDODA. FOPlLD.FZcT + (DUCMD 305

+ FCZO) -BeScT)
t $ RLZC2L »(t $ RDODA. FOP2LD-FZCF + (DUCMD 305 + FCZO) · DEDCZ)

The Boolean expressions for loading the register position high value of the registers are

(LDRLZClU - SFOPlLD + (DUCMD 305 + FCZO) -DEDCZ [LDRLZC2U - SFOP2LD + (DUCMD 305 + FCZO) • DEDCZ DEDCZ -

The contents of the registers are incremented according to the following expressions:

[CNTUPRLZCIU »[$ RDODA-FOP1LD · FZCF · LZCO [CNTUPRLZC2U - ($ RDODA · FOP2LD · FZCF.LZCO SFOPILD- (DUCMD 301 FRDP 1 fPOA. (DlEQOVP D2 EQOVP

• L75HS "+ FCRPl))
SF0P2LD -. (FOPlLD WM (DUCMD 301 + FRDP2) (DFCO

• FDID · DTECO. [$ RDODA + DFCO-FDID · FDTED + DTECO * [5RDODA-FDFD) + FOPILD-FMVN

• DUCMD 301-FRDPl) PMS) DlEQOVP - (DBITk-ROPl-ZTNSAO) D2EQOVP - (DBITZ ¹ · ROPl · ZTNSBO)

LONG - ALNDAGTEl6 + ALNDBGTE16 + ALNSGTEl6

• FMYDV + DlEQFLP + D2EQFL? ALNDAGTE16 »ALNDAl + ALNDA2
ALNDBGTE16 - ALNDBl + ALNDB2
ALNSGTE16 - ALNS3 + ALNS4 + ALNS5

030028/0881

Decimal unit - load operation

Operands become the Decimal unit 730 via the signal bus line ZDI 0-35 and transferred to an RDID register 730-158 under firmware control loaded. The firmware triggers a command or a DUCMD 301 command, which reads of an operand is affected by the decimal unit. This sets the indicators FRDP1 and F0P1LD, to put the logic device of the decimal unit 730 in the state, the operand 1 from the cache memory 750 to include.

The number of words to be picked up from cache memory 750 is loaded into RSWC register 730-110. The number of words is entered into the RRWC register 730-88 to be sent out to execution unit 714. The RSWC register 730-110 is considered as to its content decreased by one for each word taken from cache 750. The RRWC register 730-88 is regarding its content is reduced by one for each word that is sent out to the execution unit 714 will. The Boolean expressions for loading and decrementing the contents of RSWC and RRWC registers 730-110 or 730-88 are:

[LDRSWC - ((FDUACT-FRDpT) + (FLDCOMRL · DUCMD 30 3 • FOPSTR) + SF0P2LD)

[CNTDWN-RSWC - ([LDRRWC (FDID (FOPlLD + F0P2LD)

• DPCO + [$ RDODA. (DUCMD 30 3 + FOPSTR))) [LDRRWC - (FDUACT-FRDPl + SF0P2LD + FLDCOMPL

(FOPSTR + DUCMD 30 3))
[CNTDWN-RRWC - (DTECO- (FOPILD + F0P2LD) - [$ RDODA

+ ((FOPSTR + (DUCMD 30 3 (DMSDRGTE

+ (DMSEQ-RDSCO)))) -FSCt "- (Fswrt

♦ DMSDRGTE + (ZTNSAO-FCPCO + ZTNSAO)

• FSWRT)) -FRPK + FRPK-DUCMD 30 3

(ZTNSAO-FCPCO + ZNTSAO))

030028/0881 ORIGINAL BATHROOM

3 O O υ C J 4

The FOPILD flag is reset in the cycle the counting down of the contents of the RSWC = and RRWC registers to zero by the output signals DFCO and DTECO appearing as logic signal 1

follows. The Boolean equations have been listed above. This indicates that all of the operand-1-words have been received by the decimal unit 730 and sent to the execution unit 71A _o The firmware solves another command DUCMD 301 which sets the F0P2LD plate, since the FRDP1 flag is still set , which causes the decimal unit to include the operand 2 words, the number of words that have been received from the cache memory 750 and which have been passed to execution unit 71A »Furthermore, the content of the relevant register is counted down to zero to indicate to decimal unit 730 that operand 2 has been received, processed and transferred to execution unit 714.« The F0P2LD flip-flop is then reset

The operand can contain 4-bit or 9-bit decimal digits. Operands that contain 4-bit decimal digits are processed differently using the decimal unit 730 than operands containing 9-bit decimal digits «Es assume that the operands contain words with 4 = bit ~ decimal digits and that the first word in the RDID register 730-158 is stored »The control signal 1ZPK is output as a 1 signal, which means that the position a ZPK switch 730-160 is selected. The output signal RDID 0-35 is derived from a 36-bit word in a 32-bit word in the selected position 1 of the ZPK switch 730-160 huddled together and over the signal bus line ZPK 0-31 submitted. This allows up to eight

030028/0881

4-bit decimal digits are displayed _a The negated bus line output signal ZPK 0-31 is stored in an RPK register 730-162. The decimal digits of said data word are the numbers of high value of the operand if the decimal digits of the first word of 730-160 output operands have a sufficient number of decimal digits to the ZPK switch to be sent to the execution unit 714, as shown by the linking means of the Decimal unit 730 is specified, then the required switches are caused by their corresponding control signals to load the RDQD register 730-154 _o In this case the output signals ZPKO-31 are selected via a ZPKR switch 730-164. The output signals ZPKRO-31 are fed to the shift device 730-156, in which they are shifted to the right by an amount, which is indicated by the binary shift counter output signal ZDSC 1 = 3 of the RDSC register 730 = 58 ₀ The output signals ZDS 0-31 are fed to a ZID switch 730-150, in Xfelchem Meht-Dezlmal = digits, such as signs and escponents and also non-operand exchange characters, under the control of the ZID switch enable output signal EZID 0 = 3 the EZID = control logic 730 = 132 are replaced by zero _o The output signals ZID 4 = 35 »ground in position 0 of the ZBOD = switch 730 = 152 selected. The output signals ZBOD 4 = 35 are stored in the RBQD = register 730-154 _β

If the data word _s, which consists of 4 = BIt = numbers, does not fill a sufficient part of the RBOD = register 730 = 154 for transmission to the execution unit 714, then the first word remains in the REK register 730-162 stored ^ and the next data word of 4-bit digits is transferred from the cache memory 750 to the RDID register 730-158 under firmware control «. The second data word is sent to the shifter 730-156 via the ZPK switch 730-160 and the ZPICR = Sehalter 730 = 164

030028/0081

30000Λ5

submitted. The first in the RPK register 730 = 162 ge = The stored data word is transmitted to the shifting device 730-156 via a ZPKL = switch 730 = 166, by the Shift counting signal ZDSC1-3 v / ground 32 of the 60 inputs of the shifting device 730-156 selected. The starting = signals ZDS 0-31 are in the RDOD register 730 = 154 via the ZID switch 730-150 and the ZDOD switch 730 = 152 saved. Necessary zeros left and right are assigned to the slider output signal zDS 0-31 under the Control of the enable signals EZID 0-7 is added while the operand word is added via the ZID switch 730-150 is switched »

If the operand passed from cache memory 750 to decimal unit 730 is a 9-bit decimal digit then the first data word, which contains a maximum of four decimal digits, is stored in the RDID register 730-158 saved. The 9-bit decimal digits are made up of the five Higher-order bits of each decimal digit are freed and as a compact word using the selected position 2 of the ZPK switch 730-160 switched through and either stored in the left 16 bits of the RPK O-15 register 730-162, provided that the relevant digits come from an even address in the cache memory 750, or the The digits concerned are stored in the right 16 bits of the RPK 16-31 register 730-162 if they are off an odd address in the cache come.

If a data word can be provided to be delivered to execution unit 714, then it is sent to the sliding device 730-156 via the ZPK switch 730-160 and the ZPKR switch 730-164 = given. It should be noted that the decimal digits are in the ZPK 0-15 and ZPK 16 = 31 switch positions be repeated because the digits are set via the switch ZPK 0 = 31

030028/0881

get away. The unrelated digits, the sign, the exponent and the rewrite digits, are removed from the data word in the ZID switch 730-150. The output signal ZDS 0-31 of the shifter 730-156 is in the RDOD register 730-154 via the Positions O of the ZID switch 730-150 and the ZDOD switch 730-150 and the ZDOD switch 730-152.

It is assumed that the first data word, which has 9-bit characters, of one has an even address having memory space of the cache memory 750 and stored in the RPK O-15 register 730-162 has been and that the second data word from a memory location having an odd address of cache memory 750 and stored in RPK 16-31 register 730-162.

The second data word is sent to the shifter 730-156 via the ZPK switch 730-160 and the ZPKR switch 730-164 issued after the relevant data word of the higher-order five bits of the respective 9-bit decimal digit freed and accommodated or packed in both halves of the data word ZPK 0-31. The first data word, which is stored in either the odd address half or the even address half of the RPK register 730-162 is connected via the ZPKL-Sehalter 730-166 the pusher 730-156 released.

The control signals 1ZPK and 2ZPK select one of four positions of the ÜPK switch 730-160. the Position 0 is selected for the store operation, position 1 is selected for the 4-bit digit operand, position 2 is selected for the 9-bit digit operand and position 3 is selected for the Rounding operations selected. The Boolean equations are:

030028/0881

[12PK ■ ZTNSÄO ° FOP1LD + ZTNSBO "FOP2LD + DUCMD [2 ZPK » Zra ^ ÄÖοFOPILD + ZTNSBO »F0P2LD + DUCMD

The control signal SRPKU releases the loading of the RPK register 730-162 _P, the positions RPK 0 = 15 for 9-bit operands from an even address of the cache memory 750 and for 4-bit = Qperands RPK register 730 = 162 free, namely the positions RPK 15 = 31 for 9 = bit ~ 0 operands from an odd address of the cache memory 750 and for 4 = bit operands.

The Boolean equations are

305 Ψ FDID- (ZTNSAO.FOPlLD

STNSBO »F0P2LD + ZTNSAO · FOPlLD

.FCPCO + 2TNSBO-FOP2LD = FCPCO)

Ψ FWfo-FOPSTR (FAXT FSWRT + FALT

. <Ρ8Ή & ΐ FSND))

DUCMD 3QS + FDID- {ETMSAO-FOP1LD

-S- gTHSB0oFOP2LD + 2SfMSAO-FOPlLD ■ FOP2LD-FCPCO)

·!> FSIf ο FOPSTR »(FÄ * LT ° FSWRT V FALS.FSWRT FSND))

The control signals OZPKL Mnd OZPKR give ZPKL = scarf = ter 730-166 or the ZPKR ₀ = switch 730 = 164 free 1ZPICL The control signal selected as Shortcut ungs signal 1 bit positions 4-31 ZPK = ZPKL from the switch 730 = 166 and di © Bit position RPIl 16 = 31 from the ZPKR = switch 730 = 164 o The control signal 1ZPKRU selects the bit positions RPK 0 = 15 of the ZPKR = switch 730 = 164 as logic signal 1 _o

[OZPKA »FOPlLD + FOP2LD + (FOPSTR + DUCMD 303) • (IRPK · (DMSDREQlO'RDSCO + DMSDREQOMl • RDSCO) + FlRPK FMSDRN · (DMSDRLTMl + FMSDRGTE * DMSDRLTM2) 'FMSEQ))

[OZPKR - FOPlLD + FOP2LD + (FOPSTR + DUCMD 303) . (FRPK * (DMSDREQ21 · RDSCO + DMSDREQ10

* RJDSCO) + fTRPK.FMSDRN (FMSDRGTE

• DMSDRLTMl + RRWCO) · DMSEQ) + DUCMD 309

+ DlEQFLP + (ATMP 0-6) * FRCMD

+ (ATMP 0.1 · 2 · 3.4 · 5 · 6) .FRCMD)) [IZPKL - (DMSDRQEQl · RDSCO + DTECO-RDSCO) 'FRPK · (FOPSTR + DUCMD 303)

[IZPKRU - (FOPlLD · ZTNSAO + FOP2LD · ZTNSBO)

• RDSCl + (FOPSTR + DUMCD 303) -FRPK

• (DMSDRWEQl'RDSCO + DTECO-RDSCO) DMSDREQ10 = DTECO + .DMSDRWEQl DMS D RWEQMl ° REWC 0 · FFWC1 · RRWC 2 · RRWC 3'RRWC 4 · RRWC 5 · RRWC DMSDREQOMl - DTECO + DMSDRWEQM2 DMSDRLTMl »RRWCO · DMSDRWEQMl

DMSDELTM2 ■ RRWCO · (RRWCl.RRWC2 · RRWC3.RRWC4 · RRWC5) DMSDREQ21 - DMSDRWSQ2 + DMSDRWEQl DTECO - S! 8? C0 '· RRWCl «RRWC 2» RRWCJ. RRWC 4. RRWCS "» RRWC ^ DMSDRWEQl ™ 1SWSÜ · RRWCl »RRWCT · RRWC3« RRWCl "» RRWC5 ° RRWC6 DMSDRWEQ2 ■ IUWCO · RÜWcT- KMC2 · RRWC3 · RT? WCT · RRWCS · HAWC ^

The Boolean expressions for the control signals, which indicate the operand words during the load operation and the store operation, are the following [IZID »DUCMD 203 + DUCMD 310 + DUCMD 311 + fWK

• FRCMD'DUCMD 309
[2ZID 0-7 - DUCMD 310 + DUCMD 311 + (FRPK-FRCMD • DUCMD 309) + ZCRDG-MASK

[IZDODO - ([STRPKD + [UNPKDLWR + [UNPKDUPR ([1ZSMRO + [2ZSMRO)

030028/0881

300004

(IZDODI => ([STRPKD + · [UNPKDLWR + [UNPKDUPR ([1ZSMR2

+ (2ZSMR2) [1ZDOD2 - ([STRPKD + [UNPKDLWR + [UNPKDUPR ([1ZSMR4

+ [2ZSMR4) [3.ZDOD3 - ([STRPKD + [UNPKDLWR + [UNPKDUPR ([1ZSMR6

+ [2ZSMR6)

[2ZDOD0 " (4STRPKD + [UNPKDUPR + [UNPKDLWR ([1ZSMRO

+ [2ZSMRO)) [2ZDOD1 - (4STRPKD + [UNPKDUPR + [UNPKDLWR ([1ZSMR2

+ [2ZSMR2)) [2ZDOD2 »(4STRPKD + [UNPKDUPR + [UNPKDLWR ([1ZSMR4

+ (2ZSMR4)) [2ZDOD3 »(4STRPKD + [UNPKDUPR + [UNPKDLWR ([1ZSMR6

+ (2ZSMR6)

[IZSMR 0-7 ■ SIGNMASK + REWUM 0-7 + REWLM 0-7 [2ZSMR 0-7 «EXPMASK + REWUM 0-7 + REWLM 0-7 [STRPKD =» (ZTNSAO (DUCMD 30 3 + FOPSTR)) [UNPKDLWR »(ZTNSAO (DUCMD 30 3 + FOPSTr) -FCPCO) [UNPKDUPR» (ZTNSAO (DUCMD 303 + FOPSTR) -FCPCO)

Sin ACPR adder 730-62 calculates the number of zero digits on the left side of the operand, which are required to fill a 64-digit block of memory » The output signal ZLNADJ, which is set in terms of length 0-9 of switch 730-26 is subtracted from 64, the maximum number of digits between the decimal unit 730 and execution unit 714 are transferred. That The output of the ACPR adder 730-62 is in the RLMP register 730-102. The output signals RLMP 4-6, these are the three low order bits, store the number of 4-bit decimal digit positions on the left Side of the word of high value, which are to be given as zeros. The relevant signal is sent to the shift count input a ZIDMU pusher 730-130. Those Output signals ZIDMU 0-7, which show zero digits on the left, are set to zero. Through this the displayed output signals of the EZID linkage

030028/0881

controller 730-132, namely the signals EZID 0-7, set to zero, whereby the selected digit positions of the ZID switch 730-150 must be set to zero with respect to the first word of the operand, the is recorded by the decimal unit 730. If the operand has a leading sign this would be through a zero in the ZID switch 730-150 has been replaced as the sign position count of the respective operand length in the ALNDA adder 730-18 or has been subtracted in the ALNDB adder 730-20. In addition, the rewrite characters in the operand word would have been replaced by zeros.

An ATMP adder 730-30 calculates the number of zeros on the right side of the digit position has the lowest significance of the operand with the larger scale factor. The ZASFB switch 730-28 selects the number of zeros on the right for operand 1 or for operand during the cycle in which the operand is transferred from cache memory 750 to decimal unit 730 will.

If the operand 1 scale factor is greater than the operand 2 scale factor, then the input signal is ASF 0-9 for the switch ZASFß 730-28 a positive number that is subtracted from 63 in the ATMP adder 730-30, and the difference, that is the output signals ATMP 3-9, are stored in an RTMP register 730-100. the Places RTMP 4-6 low order become a TMSC link controller 730-106 on the input side and the relevant signals on the output side as signals TMSC 0-3 to the shift counter input of a ZIDML sliding device 730-128 handed over. As a result, the output signals ZIDML 0-7 are issued, which the Show number of digit zeros on the right side of the operands. The output signals ZlDML 0-7 are

Ü3ÖQ28 / 0S31

- ι *

delivered to the EZID link controller 730 = 132. The output signals EZID 0 = 7 transfer the designated digit positions of low significance of the ZID-Sehalters 730 = 150 to NuIl _9, whereby the sign, the exponent and the rewrite = characters are removed from the operand word at the end

The signals RTMP 0-3 at the output of the register 730 = 100 and the signals RLMP 0 = 3 at the output of the register 730 = 102 indicate the cycle in which the operand word, which requires a transfer of the zeros to the right, from the Decimal unit 730 is transferred to execution unit 714. The maximum transfer of 64 = decimal digits is carried out using eight words with eight decimal digits per word. The signals RLMP 0 = 3 are a binary representation of the number of words on the left-hand side of the word which contains the most significant digit, which has a total of zeros. The signals RTMP 0 = 3 are a binary representation of the number of words at the maximum transmission minus the word "with zeros on the right side _o A plus 1 is added to the binary signals RLMP 0 = 3 when the register RDOD 730 = 154 is loaded o The signals RTMP 0-3 and RLMP 0 = 3 are compared in a comparator 730 = 104 ■ The signals TMSC 1 = 3 are emitted as zeros in the cycles in which the binary signals RTMP 0 = 3 are greater than the binary signals RLMP 0 = 3, with zeros on the right side in the ZID = switch 730 = 150 are issued on the transfer cycle, v / whether the comparison 730 = 104 indicates that the binary values of RLMP 0 = 3 and RTMP 0-3 are the same _{or the like}

The control signal SRTMP enables the input side loading of the RTMP register 730 = 100 and the bit positions RLMP 4-6 of the RLMP register 730 = 102 ₀ The control signal SRTMP gives the output bzvj »the output signal" of the bit positions

RLMP 0-3 of RLMP register 730-102 free,

The control signals ZERO / RLMPL enable the outputs of bit positions RLMP 4-6. The control signal CNTUP-RLMPU increments the bit positions RLMP 0-3. The Boolean equations are:

[SRTMP - (FDUACT «FRDP1 + SF0P2LD)

(ZERO / RLMPL «(FFDO + (FOPlLD + ■ FUP2LD) · [2ZIDA)) [CNTUP-RLMPU - ((FOPlLD + FOP2LD) · [$ RD0DA · SF0P2LD)

Decimal Unit - Figure 3 - Store Operation

In the FP0P3 cycle, the descriptor 3 information is loaded into the RSIR register 704-154 in response to a 3 descriptor instruction. In decimal calculation instructions, the descriptor 3 defines the field in which the results of the calculation of the descriptors - and Descriptor 2 operands are stored »Some instructions store the result of the descriptor 1 and descriptor 2 operand calculations in the field indicated by the descriptor 2. In each case, the RSIR register 704-154 stores the descriptor information and stores it put them in decimal unit 730 for the memory operand 3 operation. The decimal unit 730 receives the operand 3 from the character unit 720 via the signal bus line RCHU 0-35. The DeEimalunit unpacks the relevant signals, adds the sign and the exponent if necessary, positions the operand 3-digits within the word, provides the correct number of zeros on the left and right side of the operand, adds the required ASCII or EBCDIC zone bits and restores the state of the area of the first and last words of the operand ₉ which have not been specified as part of the operand. The decimal

unit 730 sets up the necessary controls in the logic device to accept operand 3, to manipulate it and store it in the cache memory 750, in accordance with its descriptor information.

The operand 3 scale factor signals RSIR 24-29 are the The input side of the ZSFN switch 730-2 is supplied and stored in the register RSF2 of the register bank 730-4 " In the event that the input operands are such that the decimal unit 730 does the scale factor alignments has made, the ZSFA switch 730-6 selects the contents of the RSF2 register and the ZSFB switch selects the Contents of either the RSFO register or the RSF1 register of register bank 730-4. The selected Register is the register that stores the smaller scale factor of operand 1 or operand 2, The FSSFD indicator, which is determined by the scale factor comparison is set during the load operation causes the selection.

The control signals 4WRRSF1 and 4WRRSF1 select one of the RSF O-4 register 730-4, in which the scale factor is stored. The Boolean expressions are: [WRRSFl «((F3DESC + FMVN) FLDCOMPL.FPOP-DlEQFLP) (DUCMD 305 · FCZO) + RDESCl-FPOP + (FMYDV

+ FPTL + FPFL) DUCMD 308 DlEQFLP (FMVN + F3DESC) FPOP FLDCOMPL [WRRSF2 - ((FMYDV + FPTL + FPFL) DUCMD 308-FPOP · FLDCOMPL • dTEQFLP (FMVN + F3DESC) + RDESCO-FPOP + (F3DESC + FMVN) FLDCOMPL'FPOP-DlEQFLP)

The output signal of the ZSFB switch 730-8 is from Output of ZSFA switch 730-6 in the ASF adder 730-10 subtracted. The output signal ASFO-9 becomes

fed to the input side of the ALNS adder 730-24 and also stored in the RSCLM register 730-144 in which the relevant signal is used as a pointer to the Lowest end of the data that is actually to be saved is used.

For a floating point store operation, the RSF3 register of register bank 730-4 stores this as to The output signal of the ALNDA adder 730-18 is set to the length, and the RSF2 register holds the effective digit counts of the internal results when the count is the first time, which means that the output signal of the AEDC adder 730-86 and the output signal ZEDC1-3 of the ZEDC switch 730-82 of the input side of the ZSFN switch 730-2. In this case, the content of the RSF3 register is transmitted via the ZSFA switch 730-6 is selected, and the content of the RSF2 register is selected via the ZSFB switch 730-8, and in the ASF adders 730-10 are subtracted from the fourth in question. In addition, the output signal ASFO-9 the input of the ALNS adder 730-24 and the RSCLM register 730-144 supplied. For the purpose of achieving zero or effective digit counting, if the operand is checked the first time, the contents of the RSCLM register 730-144 are overwritten by the input signals for the zero output and the overflow detector logic 730-80 can be formed. After the first count, if the number of effective digits is greater than the set length of operand 3, the decimal overflow indicator FDOFL set, and the calculation of the effective digit count from the contents of the RSF2 register minus the set length from the content of the RSF3 register, at the output of the RSCLM register 730-144 released for a subsequent zero and overflow test.

030023/0081

The length field signals RS1R3O = 35 are stored in the register RLND2 of the register bank 730 = 12 and via the position RLWD2 of the ZLi \! DA = switch 730 = 1 b to Input of the ALiMDA adder 730 = 18 switched through »

The control signals 1ZSFA and 2ZSFA select the outputs of the RSB "O» 3 register 730 = 4 for delivery to the plus input of the ASF adder 730 = 10 from ₀ The control signals 12SFB and 2ZSFB select the outputs RSF 0-3 for delivery the minus input of the ASF adder 730 = 10. The Boolean expressions are?

[IZSFA »FlDESC · FLDCOMPL ° (FMVN < > DlEQFLP) [2ZSFA - FSDESCoFLDCOMPL ■ * ■ FMVN -FLDCOMPL

fIZSFB - FKVN = FLDCOMPL + FMVN ^- -FSSFD -FLDCOMPL- (F3DESC + FMVN)

-DIlQFLf- (FMYDV + FPTL + FPFL) -S- FLDCOMPL- (F3DESC + FMVN) · DlEQFLP + FLDCOMPL- (F3DESC + FMVN) -DlEQFLP • (FMYDV Ψ FPTL + FPFL) + FLDCOMPL- (F3DESC

(2ZSFB * ■ FLDCOMPL- (F3DESC + FMVNJ-DIEQFLP

■ «· FMVN) -DTEQFLP • (FMYDV -5- FPTL -t · FPFL)

The sign = and decimal 3φ = signals RSIR 21 = 23 are stored in the register RTNS2 of the register bank 730 = 32 and transferred to the decoding logic 730 = 38 via the RTNS2 = switch position of the ZTNSA = switch 730-36, in which the correction factors with regard to the length If the operand 3 is a 9 = bit = floating point number, then two digits are subtracted from the length leads to the fact that three digits are subtracted from the length. »The Boolean

Expressions for the signals DBITX and D1EQFLP that correspond to the ALNDA adder 730-18 and the ALNDB adder 730-20 are supplied have been described above.

The output signal of the decoding logic 730-38 is fed to the other inputs of the ALNDA adder 730-18 and causes the subtraction from the signals ZLNDAO-5. The ALNDA 0-6 signals are output at the output of the ALNDA adder, which adjust the length in such a way that the number of decimal digits in operand 3 is displayed. The output signals ALNDA 0-6 are sent via the ZALND switch 730-22 to the input of the ALNS adder 730-24. The scale factor signals ASF 0-9 are added to the ALNDA length, and the output signals ALNS 0-9 represent the set length of operand 3. The output signal ALNS O-9 is via the zero position of the ZLNADJ switch 730-24 The adder ACPR subtracts the set length ZLNADJ 3-9 from 64 _S and its output signals ACPR 3-9 show the position of the digit highest significance to _s to be stored in the internal result field »The signals ACPR 7-9 indicate the position of the digit of the highest significance within the word of the operand that contains the decimal digit of the highest significance = the signals ACPR 7-9 are the input side of the ACPSC modifier 730-54.

The output signals of the ARWC- ^ ddierers 730-76 _f that are the signals ARWC 0-6, are fed to the RRWC register 730-88? do they indicate the position of the operand word containing the digit with the highest value _? which is to be transferred from the decimal unit 730 to the cache memory 750. A one% dLrd to the ARWC adder in the case of an operand with a leading sign

03U02S / Q8S1

300ÜÜ45

added, which would result in another word being transferred to the cache memory 750.

In the floating-point operation, during the first inspection to zero or overflow, d _e h ₀ upon the occurrence of the test zero-overflow command DUCMD 304, and at each subsequent review, at which the overflow flag FDOFL has not been set, the output signal of the ALNDA adder 730-18 is selected via the ZINADJ switch 730-26. If the decimal overflow flag FDOFL was set for a floating point = output result, then the output signal of the ALNS adder 730-24 is selected via the ZLNADJ switch 730-26. The ALJMS adder 731-24 forms the difference between the output signal of the ALNDA adder 730-18 indicating the set length and the effective digit count minus the set length from the output signal of the ASF adder 730-10.

The start character pointer signals ASFA 33-36 are stored in register RCP2 of register bank 730-42; she are selected in switch position RCP2 of the ZCPA switch 730-44. The signal ZCPA 0-3 becomes the input side of the ZCPNB switch 730-48. If operand 3 consists of 4-bit characters, then the Signals ZCPA 1-3 are selected, and if operand 3 consists of 9-bit characters, then signals ZCPA 0-2 selected as output signals ZCPNB 0-2, which are fed to the input side of the ACPNB adder 730-50. A one is added to the ACPNB adder if the operand has a leading sign «The output signals ACPNB 0-3 are inserted on the input side; see chap ACPSC adder 730-54. The switch 730-56 selects the Signals ACPSC 0-3 for storage in the RDSC = register 730-58. The ACPSC adder 730-54 subtracts

the digit with the highest value within the internal operand word, which is indicated by the signals ACPR 7-9 is designated by the digit position in the memory word of the highest significant digit as it is designated by the ACPNB signal to provide the value of the number of digits around that of the one to be stored Operand is or will be moved. This value is characterized by the signals ACPSC 0-3, stored in RDSC register 730-58; this value represents the shift counter for the ZDS shifting device 730-156.

The output signals ASWC O-6 of the ASWC adder 730-68 provide the input signals for the ZSWC switch 730-70, for the ZRLMP switch 730-112, for the ZSMP switch 730-116 and for the ZEMP switch 730-120. The output signals the switches are delivered to the sliders 730-114, 730-118 and 730-122. the Slider output signals are provided to controller 1ZSMR logic 730-142 and to controller 2ZSMR logic 730-146 to generate the 1ZSMR 0-7 and 2ZSMR 0-7 signals. These signals are sent to the ZSMR switch 730-180 issued to set the sign, the exponent and the rewrite characters in the 0perand-3 words to load. The start character pointer signals ZCPA 0-3 are fed to the input side of switch 730-46, its output signals, these are the signals ZCPWC 0-2, of the signals ZCPA 1-2 for an O-hit character operand while these are the signals ZCPA 1-3 for a 4-bit character operand acts. The signals ZCPWC 0-3 are fed to the input side of the adder ACPWC 730-66. The decimal digit is subtracted and the outputs ACPWC become 0-3 delivered to the input side of the ASWC adder 730-68. The length field of operand 3, the signals ZLNDA 0-5, is or become the start character pointer minus a one

83ÖÖ28 / 0S81

added to display the character pointer for the last decimal point in the operand »

The first word of operand 3 is indicated by the pointer · = called 720 via the signal lines HCHU 4-35 and the buffer 730-168, which receives the detection signals RCHU 4-35 and the negated signals or "J negation signals RCHU 4-35 generated.

The control signals 1ZPK and 2ZPK select the zero position of the ZPK switch 730-160, and the signals RCHU 4 = 35 occur at the output of the switch as signals ZPK 0 = 31 and ZPX 0-31

In the case of a long operand, doho for operands that are greater or longer than 15 decimal digits, the operand is transferred from the RCHU register 720 = 10, whereby one word is first transferred to the decimal unit 730 decimal digits most significant _o

If xcLrd requires a sign for the operand, the firmware sets the RSGN = register 720 = 134 via the signal lines. _{ZADSP 3 = 11 loaded 9} by the auxiliary computing and control unit 722 upon the occurrence of a command DUCMD Mn which affects the loading of the DU sign register. The output signal of the RSGN register 730 = 14 is sent to the selected position 1 of the ZSMR switch 730-180. The character position in the ZSMR switch position is selected as follows a subsequent or _o appended sign "the output of the ZCPA ~ switch 730 = 44 points to the leading sign = sign position _o a ZSMP = S © halter 730-116 itfählt a following or leading sign for 4-bit or 9-bit = operands from _o The shift = counter position ZSMP1-3 is transferred to a SIGNM shift device 730 = 118

submitted. The input logic signal O for the SIGNM shift device 730-118 leads to the selection of one of the output signals SIGNM 0-7 for 4-bit operands ,, The logic signal O and the ZTNSAO signals select two adjacent signals of the output signals SIGM 0-7 for 9-bit operands. The output signal SIGNM 0-7 of the shifting device selects the output signal 1ZSMR 0-7 of the control device 1ZSM 730-142 from _s one of eight switch 1 positions of the ZSMR switch 730-180 for the 4-bit decimal number operand = Selects sign or two adjacent positions for the 9 ~ bit sign operand sign®

The exponent is added to the operand on instruction DUCMD 308 , which concerns the loading of the DU exponent register. A REXP registers 730-138 is of the signal bus line ZADSP 3 = 11 ₀ loaded forth a ZEXP switch selects the exponent bit-730-140 Üonfiguration for an operand with a 4-bit decimal point, and stores the least significant 4-bit Characters in an even digit in the cache memory 750 via the 1 position of the ZEXP = Sehalters _o All other exponents are selected via the zero position of the switch "" The output signal ZEXP 0-8 is set to position 2 of the ZSMR switch ZSMR 730- 180 supplied «, The exponent character positions are selected by the output signals 2ZSMR 0-7 from the control logic 2 ZSMR 730-146 The signal is generated as follows _o The Boolean expressions for the control signals 1ZSMR 0-7 and 2ZSMR 0-7 are above has already been specified »

The output signals ASWC 5-6 of the ASWC adder 730-68 show the position of the low-order word of the operand of the low-order character for 9-bit characters. One Binary 1 is subtracted from this value in the ACPE adder 730-74 to place the digit with higher significance of the exponent for an operand that consists of

300GGA5

4-bit characters. A ZEMP switch 730-120 selects the character position and the output signals ZEMP1-3 are sent to an EXPM shifter 730-122 submitted. The output signals EXPM 0 = 7 are sent to the control logic 2ZSMR 730-146. The output signals 2ZSMR 0-7 select the two adjacent character positions in the ZSMR switch 730-180 to enable the writing of the To release exponents in the word lower degree.

For a 4-bit operand, it is for the digit position The highest possible value for the exponent sign is that it is in digit position 7, and the The lowest significant position can be in the digit position 0 of the next word. In this case the EXPM marker 730-122 generates a 1 output signal on signal line EXPM7 when the ZEMP switch 730-120 pointer is in the decimal position 7 while the penultimate word is recorded. When the last word is recorded, the ZEMP switch pointer remains at 7 and the DBITS input signal is output as a 1-signal, whereby a binary signal 1 is output on the EXPMO line. This will make the Zero character position of the word least significant activated. The Boolean expression for the DBITS signal reads:

DBITS - DFCO (DUCMD 30 3 + FOPSTR) (ACPEl * ACPE2 * ACPE3) DlEQFLP

The signals RDESCO and RDESC1 are applied to the write select inputs of the RLNDO-3 register 730-12, the RTNSO-3 register 730-32 and the RCPO-3 register 730-42. The signals RDESCO and RDESC1 are binary coded 00, 01 and 10 to identify operands 1, 2 and 3, respectively.

The control signals 1ZLNDA and 2ZLNDA are sent to the ZLNDA switch 730-16 and handed over to the ZTNSA counter 730-36.

03002 ^ / 0801

The status indicator FMVW is sent to the ZLNDß switch 730-20 and handed over to the ZTNSB counter 730-34.

The control signals 1ZCPA and 2ZCPA are sent to the ZCPA switch 730-44 delivered. The Boolean expressions describing the signals are as follows:

[IZLNDA = F3DESC * FLDCOMPL
[2ZLNDA - F3DESC · FLDCOMPL

[IZCPA «FRDPl · FLDCOMPL + F3DESC · FLDCOMPL [2ZCPA «F3DESC · FLDCOMPL

The output signal ZSMR 0-35 contains decimal digits, Exponents and signs; this signal is delivered to the ZDOD switch 730-152 and into the RDOD register 730-154 loaded for transfer to cache 750.

When storing short operands, the words from of execution unit 714, with the lowest significant word first and the highest word Significance to be added last. The command or command DUCMD 305 (data transfer from RCHO to RPKj is initiated by the firmware. The word least significant is expressed by the character unit 720 via the Signal bus line RCHU 4-35 received and in the RPK register 730-162 via a buffer 730-168 and the Position 0 of switch ZPK 730-160 saved. if the short operand is two words then the most significant word in the RCHU register will be in the same Cycle housed; it occurs on the signal bus line RCHU 4-35 on the following cycle, across the buffer 730-168 and the position 0 of the switch ZPK 730-160. The signals in question become the

030028/0801

ISS 300 ^π ; Η5

Input side of a ZP & R switch 730-164 and one ZPKL switch 730 = 166 supplied as ZPKO-31 signals » If the short operand was only one word long, then zeros are sent to the RCHU ^ bus line To serve word of highest value »

The negated output signals of the buffer 730-168, the signals RCHU 4 = 35 »are fed to the input side of an output zero · = and overflow detector logic 730-80 and the effective digit logic 730 = 81» during the cycle j during which the Command DUCMD 305 is present, the word with the lowest significance is checked for zero or overflow and the word with the highest significance is checked for zero or overflow in the following cycle, which is marked by the fact that the FCZO = indicator in the inoculation state is 1 ₀

An RSCUM register 730 = 78 stores the operand 3 length plus the scale factor output signal of the ZLNADJ = switch 730 ° 2β _ο An RSCLM register 730 = 144 stores the Qperand ~ 3 = scale factor = output signal from the ASF adder 730 IO = ₀ the output signals of the registers and RSCUM RSCLM be the input side of knüpfungseinheit Ver = ₀ or logic unit 730-80 supplied "

The zero = and overflow detector logic 730 = 80 masks the not "0peranden = 3 = field and shows the firmware, when the Qperand ~ 3 = field is zero, since the DZERO output signal of the detector logic 730 = 80 in this case a logic signal is 1 and likewise the 0 operands = 3 = field and masked the scale factor field and the firmware a Display in the event that a non-zero decimal digit in the character positions on the left The side of the most significant character of the operand 3 is present in the most significant word, which means that the DOFL = output signal of the detector logic 730-80 as

Link signal 1 occurs. The output signals of the registers RSCLM and RSCUM are used to mask the non-operand 3 character positions, and the RSCUM register output signal masks the operand 3 and scale factor characters »positions _9, which enables the overflow check .

The Boolean expression for loading the RSCUM register 730-78 and the RSCLM register 730-144 is;

LDRSCM = (FLDCOMPL (FCRD + DUCMD 314 + DUCMD 205) (DUCMD 305 + FCZO))

The Boolean expression for decrementing the bit position is RSCUM 0-6 and RSCLM 0-6 CNTDWNRSCM = (DUCMD 305 + FCZO)

A command DUCMD 303 (operand storage by the decimal unit) is initiated by the firmware. Since this is a short operand operation, two words are grounded from the execution unit 714 to the decimal unit 730 via the bus line RCHU 4-35 sent out. The least significant word remains stored in the RPK register 730-162, and the most significant word remains on the RCHU 4-35 bus line for processing the command.

The RRWC register 730 =? 88 stores the internal position of the Data word of the highest value ^! «From the decimal unit 730 to the cache memory unit 750 is. The content of the register is reduced if a word consisting of 4-bit characters is sent to the cache memory 750 «The content of the register is also reduced in each case Run a word of 9-bit characters to a memory location is sent out with an odd address in the cache memory 750 «, The Boolean expression for the decrement signal CNTDM-RRWC has already been described above.

/ 06 * 1

3000G / .5

The RDSC register 730-58 stores the shift counter position which is sent to the ZDS shifter 730-156 is issued via the ZDSC switch 730-72.

Assuming the shift count is positive which means that the RDSCO bit is a zero and that the RRWC register indicates a word count that; is bigger as üins, the zero output signals of the ZPKL switch 730-166 and the ZPKR switch 730-164 are transferred to the sliding device 730-156. The output signals ZDSO-31 are zero; they will be sent to the ZID counter 730-150 submitted. The output signals ZID 0-35 are sent to the ZSMR switch 730-180 issued, in which the rewriting characters and the leading sign can be added to the most significant word. That Output signal ZSMR 0-35 is sent to the ZDOD switch, in which 9-bit character words, iBCDIC or ASCH zone characters are added, with the output signals ZDOD 0-35 can be loaded into RDOD register 730-154 for simple transfer to cache memory 750. The control signal SRDODA loads as logic signal 1 the RDOD register 730-154. Dor Boolean expression is:

[5RDODA - ((FDATA-AV + DUCMD 203 + DUCMD 310 + DUCMD 309 + FRPK DUCMD 303 + FkPK FALT FSWRT) DUCMD 3ll)

When the count in the RRWC register 730-88 equals 1, then the most significant word stored in RCHO register 720-10 and which occurs on the signal bus line RCHU 4-35, via the buffer 730-168, the position 0 of the ZPK switch 730-160, position 0 of the ZPKR switch 730-164, the ZDS shifter 730-156, in which the relevant word is shifted to the right, released, with the number of digit positions equal to the binary

03002d / Qd81

ZDSC shift count is 1-3. Thereby zeros, which are equal to the number of slide counts on which inserted to the left of the digit position of the highest order. The output signals ZDS 0-31 are through the position 0 of the ZID switch 730-150 is switched through. The output signals ZID 4-35 are sent to the ZSMR switch for 4-bit characters, whereby the word is expanded from 32 bit positions to 36 bit positions. The output signals ZSMR 0-35 are switched to RDOD register 730-154 via position 3 of ZDOD switch 730-152 switched through, from which the word to the cache memory is transmitted.

If the word has 9-bit characters, then the Output signals ZID 0-35 to position 2 of the ZDOD switch 730-152, provided the word is in an even Address of the cache memory 750 is written, or the relevant output signals are sent to the position of the ZDOD switch 730-152 when the word is in an odd address of the cache memory 750 via the RDOD register 730-154 is written. Assume that there is a word for an even address in the Cache memory 750 is present. Then the signal ZID 4-35 is via position 2 of the ZDOD switch 730-152 switched through, whereby the four characters indicated by ZID 4-19 are expanded to 36 bits by adding the SBCDIC or ASCII zone characters can be added. On the next cycle, the signals ZID 4-25 are over position 1 of the ZDOD switch is switched through, whereby the signals ZID 20-35 are expanded to 36 bits, that the EBCDIC or ASCII zone characters are added.

The RRWC register 730-88 is reduced in terms of its content each time a 4-bit character word is added is transferred to the cache memory 750, or each

Ö3ÖU2Ö / 08S1

- 3OÜO ^; U5

when a 9 = bit = character word is transferred to an odd address in the cache memory 750 _o The counter position of the RRWC counter 730 = 88 is reduced to zero; the shift count signal ZDSC1 = 3 is a positive binary number _o In this case the output signals ZPK 4-31 are output via the ZPKL switch 730 = 166, and the output signals RPK 0-3 are output via the ZPKR switch 730-164

The RRWC register 730 = 88 is reduced in terms of its contents to the binary value = 1, wherein the Schiebezählsignal ZDSC 1 = 3 is a positive number _o 162p which stores the RPK register 730 = the least significant word; outputs its output signals RPK 0-31 via the ZPKL switch 730 = 166 to the ZDS = shifter 730-156 »This means that zeros are sent to the ZDS shifter 730-156 via the ZPICR = Sehalter the switches for loading the RDOD = register 730 = 134 sum for the purpose of transferring to the cache memory 750 =

Unless erfordernCh _9, the RRWC register 730 = 88 reduced in its value to the binary value = 2 In this case zeros are delivered to the inputs of the ZDS shifter 730 = 156 The duty cycle is the exponent of the following sign and also the replacement characters for storage in the RDOD register 730 = 154 free _p after the ZEWR = switch 730 = 180 and the ZDOD switch 730-152 have been switched through

Each of the above memory operations is enabled by a signal DUCMD 303, which by a firmware command set Xtfird, which puts the word in the RDOD register 730 = 154 loaded in the first firmware cycle and how

the word in cache 750 in the second firmware cycle is written. The first firmware cycle and the second firmware cycle are repeated as long as until all of the words containing the operand 3 information are transferred to the cache memory 750.

The sequence of steps to load cache memory 750 to achieve a negative shift count, which means that the output signal RDSCO is equal to 1 same as the sequence of steps for a positive shift count, with the exception that the binary value in the RRWC register 730-88 for the respective step is 1 higher than the corresponding value for the positive Shift counting.

As part of the long operand store operation, the firmware initiates a DUCMD-304 operation (check for Zero / overflow) c The operand 3 information is taken from the Execution unit 714 to decimal unit 730 under Firmv / areststeuerung sent out, each time one word is sent out with the word lowest Starting value. A command DUCMD.304 is issued for each meaningful word to be checked, with the relevant word Word into the RCHO register 720-10 of FIG. 2 is entered at the respective time = The last command DUCMD 304 is highest for the word by the firmware Significance of the long operand given. The decimal unit 730 samples each word included in the cycle which follows the command DUCMD 304, which is marked by the fact that the FCZO flag is set. The scanning takes place from the word with the lowest value to the word with the highest value, whereby the number of digits on the right-hand side including the most significant digit is counted. These Number is stored in RWPC register 730-84, RLZCI register 730-96 and RLZC2 register 730-98.

030028/0881

300UC-45

The output signal of this register stands for the firmware to issue the command DUCIO 311 (give operand word count in FlDOD).

The resulting operand word RCHU 4-35 is checked by the effective digit logic 730-81 according to FIG. which is accepted by the character unit 730 »The resulting operand word was in the execution unit 714 have been generated; it represents the result of the decimal-numeric operation on the operand and has been executed on operand 2.

The negated signals RCHU 4-35 are sent to the inputs given by NAND gates 81-2 to 81-16. The decimal digit zero signals RCHU 4-7 are fed to the input side of the NAND gate 81-2. The decimal digit 1 signals RCHU 8-11 are fed to the input side of the NAND gate 81-4. The Decimal digit 2-7 signals are applied to the inputs of NAND gates 81-6 to 81-16.

When the input signals to the NAND gate 81-2 indicate that the signals RCHU 4-7 in the digit position O is a Display digit that is not zero, then the output signal DGZ-O of the NAND element 81-2 is fed as a logic signal 1 to the input of a NAND element 81-42. The output signal EDC-O indicates as logic signal 1 that the word contains eight significant digits. That Output signal DGZO is sent as a logic signal O to the Inputs of the NAND gates 81-44, 81-46 and 81-48 emitted, whereby the output signals EDC1-3 as logic signals be delivered.

If the signal RCHU 4-7 in the digit O is a decimal 0 indicates, then the output of the NAND gate 81-42 blocked, and the output signal of the NAND

Links 81-44, 81-46 and 81-48 are released; this output signal shows the position of the highest digit Significance of the operand word. It is assumed that the digit with the highest value is in the 5 of the eight-digit operand word with the Places O to 7 are located. Therefore, the output signal DGZ5 of the NAND gate 81-12 occurs as a logic signal O, and the output signals DGZ 0-4 of the NAND gate 81-2, 81-4, 81-6, 81-8 and 81-10 are used as logic signals 1 submitted

The signal of the number 5 is used as a logic signal O. the input of the NAND gates 81-22 and 81-32 delivered. The output signals DZR56 and DZR5 / 7 are used as logic signals 1 to the inputs of the NAM) elements 81-28 or 81-40. The other input signals, viz the signals DZR34 and DGZ4 are sent as logic signals to the other inputs of the NAND gates 81-28 and 81-40 submitted. The output signal DZR3 / 6 is output as logic signal 1 to the input of a NAND element 81-36. The other input signal DZR12 leads as logic signal 1 to the fact that the output signal DZR1-4 of the NAND element 8-34 occurs as logic signal 0, whereby the output signal EDC-1 of the NAND gate 81-44 as logic signal 0 occurs. The output signal DZR1 / b des NAND gate 81-36 occurs as logic signal 0, since the input signal DZR34 of NAND gate 81-28 as a link signal 1 occurs. As a result, the output signal DZR1 / 6 is emitted as logic signal 1, whereby the output signal EDC-2 of the NAND gate 81-46 is output as logic signal 1.

The output signal DZR4 / 7 of the NAND element 81-40 is fed as logic signal 0 to the input of the NAND element 81-24. The output signal DZR3 / 7 is fed as logic signal 1 to the inputs of a NAND element 81-30.

Q3ÜQ2S / QGS1

3 ^ nnnq /, ς

* = ^ j U υ; .. '4 y

The other input signal DGZ-2 acts as a logic signal 1 the delivery of the output signal DZR2 / 7 as a logic signal O, whereby the output signal DZR1 / 7 of a NAND element 81-38 as logic signal 1 o This causes the output signal EDC-3 of the NAND gate 81-48 output as logic signal 1

The signal EDC-1 as logic signal 0 and the signals EDC-2 and BDC = 3 as logic signals 1 indicate that there are three significant digits in the operand word.

The word with the lowest significance is received by the decimal unit 730 via the signal bus line RCHU 4 = 35 in the buffer 730-168. The negated output signals RCHU 4-35 are given to the effective digit logic 730 = 81., The effective digit logic 730 = 81 transmits the output signals EDC 0-3 to the input of the ZEDC switch 730-82. The output signals ZEDC 1 = 3 identify a binary counter position or »number of significant digits in the word, starting with the digits of the highest significance and counting up to digit position 7 of the lowest significance _P which is included in the counting _o The output signal ZEDCO indicates as logic signal 1 that the highest significant digit of the word, that is the digit O ₅ , has a decimal digit other than 0 o This output signal is loaded into the AEDC adder 730-96 ^ after the first word has been recorded o The RWPC register 730 = 84 is in each case incremented by 1 when a subsequent word from the execution unit 714 is received forth _o This is done be issued by the control signals ENRWPCp CNTUP = RWPC and LDRWPC, the = to the input terminals of the register 730-84 RWPC "

The Boolean expressions for the control signals LDRWPC, which load the RWPC = register 730 = 84, and for the signals ENRWPCj which enable the output of the register following s

tENRWPC = ((DUCMD 305 + FCZO) + FCRD · DUCMD 314

• DUCMD 205)

[LDRWPC - ((DUCMD 305 + FCZO) (FCRD + DUCMD 314 + DUCMD 205))

The output signals RWPC 0-3 are one terminal of a AEDC adder 730-86. The ZEDCO signal will fed to a further connection of the AEDC adder 0-3, the output signal of which via the ZEDD switch 730-94 switched through and in positions 0-3 of the RLZC1 register 730-96 and the RLZC2 register 730-98 if the respectively recorded word has a stored decimal digit other than zero. the binary output signals ZEDC 1-3 of the ZEDC switch 730-82, which indicate the number of significant digits in the! ■■ 'place, are in positions 4-6 of the RLZCI register 730-96 and the RLZC2 register 730-98. »The register output signals RLZC1 0-6 and RLZC2 O-6 are fed to the ZLZC switch 730-76, its output signal for the firmware via position 3 of the ZID switch

will
ters 730-150 made available! The registers RLZC1 and RLZC2 both store the number of significant digits in the operand 3. If the first word is received by the execution unit 714 and, according to the assumption, the position 0 has a decimal digit other than 0, then the binary value 8 is in the registers RLZC1 and RLZC2 saved. The input signal ZEDCO for the ZEDC adder 730-84 is a Veikjaüpfungssignal 1 "If the second word is recorded and, as assumed, contains a decimal digit again in position 0, then the ZEDCO input signal for the ZEDC adder appears as a 1 signal, and the RWPC3 input signal is a binary signal 1. As a result, the output signal ZEDCO-3 is output as a binary 2, and the binary quantity 16 is stored in the registers RLZC1 and RLZC2. It is assumed that the third word contains only three decimal digits, with the digit of the highest order in position 5. In this case, the initial

030U28 / QSS1

300004§

signal ZSDCO-3 a binary value 011 in the RLZC1 or » RLZC2 registers 730-96 and 730-98, which are now in size 19 is saved in the registers "

The bits RLZC1-2 and RLZC2-2 (binary 16-bit) are set again because the output signal AEDC 0-3 is a binary 2 is. The RWPC register 730-84 has been incremented from binary 1 to binary 2. That RRWC register 730-88 stores the set length of the operand, which is derived from the length and the scale factor values has been calculated as indicated by the descriptor. The RWPC register 730-84 stores the Number of words checked by the firmware as a result of the DUCMD 304 command a long operand.

With the long operand memory operation it is necessary to the operand 3 - which is the result of the calculations concerning operand 1 and operand 2 and which exists internally in execution unit 714 to compare with operand 3 as it is in the cache 750 and use a simplified firmware procedure to do this.

First, the firmware issues the DUCMD 303 command, which concerns the storage of an operand by the DU unit. This command or this command triggers the actual storage sequence in the decimal unit 730. In contrast to the storage procedure for a short operand, the firmware does not prepare a write address and does not send a write command to cache memory 750 until decimal unit 730 allows it is. The decimal unit 730 makes this decision based on the information contained in the RRWC register 730-88, in the RWPC register 730-84 and in the position of the most significant digit within the word is stored if the operand is replaced by the

Decimal unit 730 is received by execution unit 714, as indicated by the output of the ACPNB adder 730-50. As in the case of the short operand becomes the output of the ACPR adder 730-62 is subtracted from the output of the ACPNB adder 730-50 in the ACPSC adder 730-54 to obtain the Generate shift number which is stored in RDSC register 730-58.

each

It should be noted that word stored in cache memory 750 requires a minimum of two firmware cycles for the store operation. The address in the cache memory 750 under which the operand word is written is sent out to the cache memory 750 in the first cycle, and the data for the cache memory 750 is sent out in the second cycle. The firmware is therefore organized in two step loops. In the first step, the address and the write command are generated, and in the next step the data is passed from the decimal unit 730 to the cache memory unit 750. The process begins in the cycle in which the firmware sends the command or command DUCMD 303 to the decimal unit 730. The firmware checks the start write signal RRLTRD for the execution addressing and branching circuits 701-1 according to FIG.

The FSWRT flag is set to the decimal unit 730 to indicate that the firmware is sending write commands to the cache memory 750. When the start write line RRLTRD carries a logic signal 0, then controls the Firmware loading the RCHO register 720-10 of the drawing unit 720 with words from the execution unit 714, until the word of the highest order is stored. This is

G3GÖ2Ö / Q881

the case when the counter position in the RWPC register 730-84 is greater than the counter position in the RRWC register 730-88. The content of the RWPC register 730 = 84 is reduced whenever a word is accommodated in the RCHO register 720-10, until the counter position in the RWPC register is equal to the counter position in the RRWC register ₉ if the RDSC Register 730-58 indicates a positive shift, or until the counter position in the RWPC register is less than the counter position in the RRWC register, provided the RDSC register shows a negative shift RCHO register 720 = 10. On a negative shift, the most significant word is stored in RPK register 730-162 and the second word is stored in RCHQ register 720-10

In the operation related to the positive displacement the start write line RRLTRD will lead a logic signal 1 ^ and the firmware triggers the writing into a loop of the cache memory 750 when the count of the RRWC register 730-88 equals the The counter setting of the RWPC register 730-86 is “As a result the FSND = iiennzeichen is set by which the previously word stored in the RCHO register 120 = 10 into the RPK register 730-162 is keyed in o In addition, the Firmware indicated to load the next word into RCHO register 720-10 from execution unit 714 is in that the transmit data signal RREQRD is output as logic signal 1 o

The Boolean expressions for the start write signal RRLTRD and for the transmit data signal RREQRD with regard to Storage operations on long operands are as follows

DSEND DATA

(FCPCO ■ • FSWRT

ZTNSAO

+ ZTNSAO) DMSEQ 3000045

DSTRTWRT RREQRD RRLTRD DMSDRGTE

DMSEQ

DMSDRGT

• FMSDRN

DMSDRGTE · RDSCO + DMSDRGTE • RDSCO + DUCMD 30 3 · RRWCO «FDUACT · DSEND DATA · DUCMD 202

• DÜCMD 204 · DUCMD 30b FDUACT · DSTRT-WRT · DUCMD 202

The Boolean RWPC registers

[CNTDWN-RQPC

• DUCMD 204

(RWPC 0-3 ° MINUS 1)> IRRWCO (RRWCl + RRWC2) RRWC3

• RRWC4 · RRWC5 · RRWC6 (RWPC 0-3 · MINUS · 1)

ÖRRWCÖ (RRWCl + RRWC2) - RRWC3 . RRWC4 · RRWC5 · RRWC6 (RWPC 0-3 · MINUS · 1)>

(KKWCU ". (RRWCl + RRWC2) * RRWC 3

• RRWC4 · RRWC5 · RRWC6)

Expressions for counting down in the 730-84 are?

frpk ducmd 303 (etnsao fcpco

+ ztnsjlo) + FrTk (fopstr +

ducmd 303 dmsdrgte) fält (fswrt

[$ RDOD

• DMSDHGT + (ZTNSÄO · FCPCO + ETNSAO) ' FSWRT · DMSDRGT))

=> FDÄTA-ÄV + DUCMD 203 + DUCMD 310 + DUCMD 311 + DUCMD 309-5- FRPK DUCMD 303 + F ¹ RPK FAL? · FSWRT

The decimal unit 730 compares the output signals RRWC 0-6 with the output signals RWPC 0-3 in a comparator 730-90. The comparator output signals DMSEQ, DMSDRGT and DMSDRGTE cause the register and the switch controller 730-91, and the signals RRLTRD RREQRD and the various signals to produce the ₉ ZPK the switch 730-160, the RPK register 730-162, the ZPKL Switch 730-166 and the ZPKR switch 730-164

Ö300H / OÖ81

steer. The signals also initiate the status flag control logic 730-202 to set the flags FSND, FSWRT, FMSDRGTE and FMSEQ as well as the content of the RRWC register 730-88 and the RWPC register 730-84. If the number of in the RRWC register 730-88 stored words is greater than the number of words stored in RWPC register 730-84, then the cache write flag FSVKT is set but the FSND flag is not. This leads to, that the RDOD register has 73-154 words containing all zeros, to the cache memory 750 and decrements the contents of the RRWC register 730. If the comparator 730-90 indicates an equality state, then the FSND flag is set, and under firmware control, the word of highest significance is used by the execution unit 714 is sent out to the decimal unit 730 via the signal bus line RCHU 4-35. This results in a Entry into buffer 730-168. The output signal of the Buffer 730-168 is transferred to position 0 of the ZPK switch 730-160. The word of highest value is used in the RPK register 730-162 from the ZPK switch 730-164 saved. A control logic (not shown) enables the ZPKR switch when a data word is put together and broadcast to cache memory 750. In this case the output signals ZPKR 0-31 are sent to the ZDS shifter 730-156 is released and the word is shifted through a number of digits, the is equal to the binary value of the signals ZDSC 1-3. In the process, zeros are sent to the signal bus line ZPKL 4-31. The output signal ZDS 0-31 becomes position 0 of the ZSMR switch via position 0 of the ZID switch 730-150 730-180 switched through if the operand comprises 4-bit characters. If the operand is 9-bit characters, then will the output signal ZDS 0-31 via position 0 of the ZID switch 730-150 switched through to position 1 of ZDOD switch 730-152, provided the word is in a

Ü 3 0 0 2 a / 0 Q

odd address is to be written in the cache memory 750, or to position 2 of the ZDOD switch, if the word is to be written into cache 750 at an even address.

The position 0 of the ZSMR switch leads to an expansion of the word containing 4-bit digits from 32 bits to 36 bits, whereupon the word has the position 3 of the ZDOD switch 730-152 is switched through to the RDOD register 730-154, in which the relevant word and sent out to cache memory 750 in the next cycle.

in position 2 of the ZDOD switch 730-152, words of operands are expanded to consist of 9-bit digits, by expanding the output signals ZID 4-19 in such a way that the 3b-bit word is generated. This is done by that the ACSII or EBCDIC zone characters are added. In position 1 of the ZDOD switch 730-152, the Output signals ZID 20-35 to 36 bits on the signal bus line ZDOD 0-35 extended. The output signals ZDOD 0-35 from position 2 of the ZDOD switch are in the RDOD register 730-154 and transferred to an even address of cache memory 750. The output signals in the position 1 of the ZDOD switch is transferred to odd addresses of the cache memory 750,

In the event that the output of the comparator 730-90 indicates that the binary number or counter position RRWC 0-6 of the RRWC register 730-88 is smaller than the binary counter position RWPC 0-3 of the RWPC register 730-84 the data words are neither received by the execution unit 714 still sent out by the decimal unit to the cache memory 750, and the counter position of the RWPC register 730-88 is counted down or decreased until the output of the comparator 730-90 indicates that the

030Q28 / OS81

4Ή 3 OO :) ϋ Α

binary counter position RWPC 0 = 3 is equal to the binary counter position RRWC 0 = 6 _o This sets the flags FMSEQ and FSWRT, and the data words are introduced into the RDOD register 730 = 154 by clock control and transferred to the cache memory 750,

Operand with 9 ~ bit characters effect the transfer of two words to the cache memory 750 to each of the power consumed by the execution unit 714 during the normal operation words out _o of the execution unit 714, recorded ^ ort has up to eight decimal digits, each having four bits to 5 it is expanded to two words, each of which has up to four decimal digits with nine bits each o The cyclic setting and removal of the FCPCO = identifier controls the transmission of words to odd addresses and even addresses in the cache memory 750 _o

Cycle delay

The rate of processing of short operand is increased thereby, that at the beginning of the processing of the command or ₀ of the instruction, the number of words is predetermined., The wirdp emitted from the decimal unit 730 to the execution unit 714 and that the number of cycles is predetermined between the time at which the first read command is sent to the cache storage unit 750, and the time at which the first data word is sent to the execution unit 714. The number of words and the number of delay cycles are calculated in the decimal unit 730 and determined by the firmware in the execution control unit 701. The output signals PK-VCTR 0 = 3 of the decimal unit 730 according to FIG submitted; they cause

30000 / i5

let the firmware branch to a specific address in execution control memory 701-4, which causes the firmware to execute a subroutine to process the operand. The particular selected Subroutine is designed to match the exact number of words in the operand with the exact number of delay cycles, whereby the operand is processed with the minimum number of microwords will.

The calculation of the number of delay cycles is a function of the data type, what does it mean? that the concerned Calculation depends on whether the incoming operand consists of 4-bit characters or 9-bit characters. In addition, the calculation in question depends on the position of the highest-order character in the operand, the comes from the cache memory 750, and also from the Position of the most significant digit in the operand that is transferred to the execution unit 714 *, as an example assume an 8-decimal digit = 0perand, which consists of 9-bit characters with a leading sign. It is also assumed that the sign is contained in the third character position of the first word of the operand is or was. The second word from cache 750 contains 4-decimal characters, and the third word from the Cache memory 750 contains 4-decimal characters «The decimal unit 730 would not include any decimal digits whatsoever of the first word, there is the first word contains only the sign. Four decimal digits are added from the second word, but this is still the case is not enough to fill RDOD register 730-154. Four decimal digits are or were from the third word recorded, and the RDOD register was or is loaded with 8 decimal digits «,

These load operations take three cycles to complete

030028/0081

300ÜÜ-15

assemble the word and transmit it to execution unit 714. The signal lines PK = VCTR 0-3 would show the firmware a word transfer with a 2 = cycle delay. The firmware performs using the information indicating the number of transmitted Words and the number of delay cycles indicates the control regarding the transfer of Words of data from one register to another register in a special cycle, rather than stopping or in to pass a waiting loop for a data word =

The delays are a function of the type of data being used 4-bit or 9-bit decimal characters, as indicated by the State of the output signal of the ZTNSA switch 730-36 and the ZTNSB switch 730-34 is displayed. These signals are the signals ZTNSAO and ZTNSBO. The ACPNB adder 730-50 gives as an output signal the digit of the highest significant digit of the Cached memory 750 from the word recorded from «The ACPDF adder 730-52 supplies the difference with regard to the Adjustment between the first character position for the high order digit in the first word from the cache 750 and the digit position of the digit with the highest value as sent to the execution unit 714 is transmitted. The output signal ZCPAO of the ZCPA switch 730-44 denotes the word from the cache memory 750 which is below an odd or below an even Word address occurs.

The Boolean equations for calculating the number of words and delay cycles can easily be implement in functional hardware; they are given by the following equations:

PK-VCTR 9 ^m 0 PK-VCTR 1 - TDBJZi PK-VCTR 2 - TDBl PK-VCTR 3 · » ARWC6

TDB0 »((ZTNSA) J · FDUACT · FlOPl + ZTNSBfT · FRDPl) (ACPDF0 · iÜPTff + ACPDF0 · ZCPAff · ACPDFl)]

TDBl »((ZTNSA0 · FDUACT · FRDPl + ZTNSB0 · FRDPl) (ACPDF0)

FDUACT FRDPl + ZTNSB0 FRDPl)

[(ACPDFZ · ECPTjJ) + (ACP.DF0 · ZCPA ^ (ACPN ^- B 0 · ACPNBl · ACPNB2 · ACPNB3 + AÜ? ÜfT · ACPNB0 * ACPNBl) + ACPDF0 · ZCPA0 · ACPDFl)]]

The PK-VCTR1 signal is output as a binary signal 1 and indicates a 2-cycle delay. That Signal PK-VCTR2 indicates a 1-cycle delay as binary signal 1. The signal PK-VCTR3 shows as a binary signal O indicates that a data word from the decimal unit is transferred to execution unit 714. The signal PK-VCTR3 indicates as a binary signal 1 that two Data words are transferred to the execution unit 714.

The Boolean shows the calculation of the PK-VCTR1 signal Expression ZTNSA0. FDUACT · FRDP1 indicates that a 9-bit 0perand-1 word from the cache memory 750 is present. The signal ZTNSB0.FRDP1 shows the presence of a 9-bit 0 operand 2 word from the cache memory 750. The expression ACPDF0 * ACPA0 indicates that by shifter 730-156 a left shift of the word is made from an even address of the cache memory 750. The expression ACPDF0 · ZCPA0 · ZCPDF1 shows a left shift 1-3 decimal digits of a word from an odd address of the cache memory 750.

For the calculation of the signal PK-VCTR2, the expression shows ZTNSAO ° FDUACT.FRDP1 «ACPDF0 the presence of a 4-bit 0-operand 1-word from the cache memory 750, which requires a left shift by the shifter 730-156. The expression ZTNSBO · FRDP1 «ACPDF0 indicates a 4-bit 0perand-2 word, which is a left

03ÖÖ20 / O881

30CC045

Shift required, the expression ZTNSA0 ° FDUACT ° FRDP1 + ZTNSB0.FRDP1 shows a 9 ~ bit 0 operand = 1 word and a 9 bit operand 2 word at ₀

The expression ACPDFZ ° ZÜPÄ0 + 2WDF0 ° ZCPA0 indicates either a zero shift / a right shift of the word from the even cache memory address -Bit character fortes or in position 0 of the 9-bit character word from an odd cache memory address. The expression ACPDF1 ο ÄCPNB0 ο ACPNB1 indicates that the high-order decimal digit taken from the cache memory 750 is contained in digits 1-3 and that the shift number is less than four digits, the expression ACPDF0 ° ZCPA0 ° ACPDF1 indicates a left shift ₉ which is greater than three digit positions from the odd cache memory = address word _o It should be noted ₉ that the signal ACPDFZ indicates as a binary signal 1 " that the adder 730 = 52 is set to a binary = value 0 ₀ To calculate the signal PK- VCTR3, the signal ARWC6 indicates a 1 = word transmission from the decimal unit 730 and the execution unit 714 if the signal in question occurs as a binary signal 0, while a 2 word transmission then indicates xv ± rd ₉ if the signal in question appears as a Binary signal 1 occurs = occurs.

Dezimaleinhei t 730 ° FIGS ₀ 3 - rewrite operation

Operand 3 can begin and end in character positions within the word of highest and lowest significance _o It may be necessary to record the information stored in the words of highest and lowest significance of operand 3 ^ which is not part of operand 3 ₀ In this Trap solves the

300004

Firmware issues a command DUCMD 306, which concerns the loading of rewrite data. This command is triggered in the decimal unit 730 in order to transfer the word of highest significance into the REWR2 register of the register bank 730-177 via the bus line ZDI 0-35 from the cache memory 750, the RDID register 730-158 and the RDID buffer 730- 176 to download. The firmware triggers a second DUCMD command to load the lowest significant word into the REWR3 register of the REWR O-3 register bank 730-177. If the firmware DUCMD a command outputs 303 (storing the operands on the decimal), the word occurs on most significant on the ^s ignalbusleitung ZID 0-35. Assume that there are 4-bit decimal points for the operand. In this case the RCP2 register of the register bank 730 = 42 stores the start character position of the operand 3 ° Since this is a descriptor 3 operation ₉ the position RCP2 of the switch 730-44 is selected ₉ and the output signal ZCPA 0 -3 is given to a ZRUMP holder 73O »148. The position 1 of the ZRUMP switch \ fird is activated, and the output signal ZRUMP 0-2 is sent to an RBWUM ° shifting device 730 149. The output signals REWUM 0-7 are sent to the control 1-ZSMR logic 730-142, and the Control-2-ZSFJR-0-7 output signals select the digit position of the ZSMR switch that is selected. For example, for processing the most significant word of the 4-bit digit operand, the digit positions in position 0 of the ZSMR switch 730-180 would be selected for the operand digit data. The sign position in position 1 of ZSMR switch 730-180 would be selected if the operand had a leading sign and the digit positions to the left of the operand would be selected in position 3 of the ZSMR switch for rewrite data v / earth. The output signal REWUM is 0-7 of the shifter 730-149

030028/0881

Iff 300UÜ45

request the write data for those digit positions O _9, the output bus line ZSmR O ~ 35 is switched to the RBOD register 730-154 via position 0 of the ZDOD switch 730-154.

If the operand contains 9-bit decimal digits, then the logic signals 1ZSMR O, 2 ₉ 4 and 6 and the connection signals 2ZSMR O ₉ 2, 4 and 6 are output to the unpacking or spreading ZDOD logic 730 = 184 The output signals 1ZD0D 0-3 and 2ZD0D 0-3 indicate the positions for rewriting or rewriting and for the leading sign digit of switch position 3 and the operand decimal digit positions of either position 1 or position 2 of the ZDOD switch 730 = 152 free.

During the load operation with respect to a 2-descriptor = operation, the most significant word of the operand 2 _S, which could contain rewrite information, is written into the REWRO register of the register bank 730 = 177, and all subsequent words are written into the REWR1 register , which replaces the previous word _c This results in the most significant word of operand 2 being stored in the REWRO register and the least significant word of operand 2 being stored in the REWR1 register »Loading these registers into the RDOD registers 730-154 are done in the manner described above.

The REWR register bank 730-177 is enabled by the control signal SREWR. The Boolean expression is SREWR = (FDID + FLDREWRH).

The control signal WRREWR1 is output to terminal 1, and the status flag FLDREWRH is applied to terminal 2 of the register selection "input terminals, for one

030028/0881

300 (1045

of the four registers RSWR 0-3. The Boolean expression for the control signal WRREWR1 is: WRREWR1 = FR0P2LD F0P2F + FLDREmH FREWR

The output signal of the register REWR 0-3 is transmitted via the ZEWR switch 730-178 selected. The signal 1ZEWR becomes to output selection terminal 1, and the status flag FREWR is applied to the output selection terminal 2 of the ZEWR switch 730-178. The Boolean expression for the control signal 1ZEWR is:

1ZEWR = (FREWR. FREWR2. FFOSD + F0P2S. FFOSD FREWRJ ο

Decimal unit 730 - Fig. 3 - rounding constant

Two commands or commands DUCMD 309, the introduction the rounding constant in the device RDOD are initiated by the firmware. For short operands the rounding constant is sent out to the execution unit in response to the first DUCMD instruction 309 if the relevant constant is to be inserted into the word lowest value. The rounding constant is sent to the execution unit on the occurrence of the second command or second command DUCMD 309 sent out in the case, that the constant in question is to be inserted in the word of highest value. In any case, will a word that contains a total of zeros to the execution unit in response to the further instruction DUCM) 309 sent out. The further or other rounding constant, a binary 5, is assigned to the digit to the right of the Scale factor pointer added (decimal point). The rounding constant is in bit positions 4-7 of the Switch position 3 of the ZPK switch 730-160 saved.

The ATMP adder 730-30 subtracts a 1 from the operand 3 scale factor stored in the RSF2 register of the

030028/0881

479 3Ü0 ^f ! 0 ' ₊ 5

Register bank 730 = 4 is stored, with a signal = output to the ATMP adder 730-20 via the ZASFB switch 730-28 takes place. If the output ATMP6 is a zero then the rounding constant is applied to the word lowest value issued on command DUCMD 309 »If the output signal ATMP6 is a 1, then the rounding constant is given to the word with the highest value in response to the second DUCMD 309 command

The output signals ATMP 7 = 9 are inverted by means of the inverter 730-147. The output signals ATMP 7-9 are selected by the ZDSC = switch 732; they represent the binary shift number for the shifter 730 = 156 ₀

The ZPKR switch 730 = 164 is released in response to the first DUCMD 309 command, provided the rounding character is added to the word with the lowest significance _o in each case is a binary output signal 5 from the position 3 of the ZPK switch 730-160 to the execution unit 714, information on the ZPKR switch 730 = 164, ZDS-shifting means 730 to 156, the position 0 of switch 730 ZID = 15O ₉ the position 0 of the ZDOD switch 730 = 152 and the RDOD = register 730-154 transferred

For the long operand store operation, the decimal unit 730 speaks to the first Command DUCMD 309 with a pointer that points to the word in the notepad memory to which the The rounding constant is added »Furthermore, the relevant decimal unit speaks to the second command DUCMD 309 with the rounding constant. The output signals ATMP 0 = 6, which indicate the word ^ to which the The rounding constant is added via the position

of the ZLZC switch 730-76, position 3 of the ZID switch 730-156, the position O of the ZDOD switch 730, the RDOD register 730-154 for the execution unit 714 is selected. The rounding constant, a binary 5, becomes to execution unit 714 during the second DUCMD-309 operation as explained above for the short operand.

Sign derivative

Since each operand is included by the decimal unit 730 during the load operation, the Yor character checked, provided it is not an overlaid sign. The decimal unit 730 checks whether the character in question is a valid algebraic sign.

An RCPS O-2 register 730-126 stores the memory location within the word of the sign. A ZCPS switch 730-124 selects the position of the sign the end. The ZCPS switch position O sets the leading sign position fixed for 9-bit character operands. Switch position 1 sets the leading sign position for 4-bit character operands. The switch position 2 denotes the final sign position for 9-blt-character overands. Switch position 3 designates the final sign position for 4-bit operands.

The output signals RCPS 0-1 select the position of a ZCH switch 730-170, which could contain the sign. No attempt is made »um select the terminating or leading word of the operand in the ZCH switch 730-170. One from the cache 750 operand word received via the signal bus line ZDI 0-35 is stored in RDID register 730-158 and applied to ZCH switch 730-170. The exitBeignal ZCH 2-8 is connected to a ZCHL switch 730-172 and to the

030026/0881

Xi

ήΐή 30000Λ5

Sign derivation logic 730 = 174 output The position 1 of the ZCHL switch is for 9 = bit = 0 operands and selected for 4-bit operands with an odd character = pointer

The sign derivation logic 730 = 174 selects either the sign from the final or ₀ after the following word or from the leading TKfort »If the sign is coded as an invalid character, a link signal (SET ILLEGAL) the output of an error display for the software »If the sign is coded as the correct sign, the logic signal (SET SIGN) sets a display for the software. The output signals ZCH 1 = 8 for the sign = sign derivation logic indicate 8 <= Bii. ° EBCDIC = sign = sign. The output signals ZCH 1 = 8 for the ZCHL switch indicate 4-bit signed characters in the lower half of the 9-bit character (bit position 4-8) with 9 = bit = character operands. In the case of 4-bit operand words, even pointers indicate the left four bits (bit positions 1 = 4), while odd pointers indicate the right four bits (bit positions 5-8).

The control signals 1ZCPS and 2ZCPS are connected to the selection = input connections 1 and 2 of the ZCPS switch 730 = 124 delivered. The Boolean expressions are?

[IZCPS - (ZTNSAO · FDUACT · FRDPl + ZTNSBO · FRDPl) [2ZCPS a fcTNSAl • ZTNSA2 • FDUACT • FRDPl + ZTNSBl. ZTNSB2 FRDPl)

The RCPS register is controlled by an SRCPS control signal

released whose Boolean expression is given by [$ RCPS - (FDUACT · FRDPl) + SFOP2LD)

Ö3ÖÖ28 / QS81

Over-hole dial correction - Fig. 3

Operands having words with 9-bit characters may have separate signs, either in a leading character position or in a subsequent character position, or the operand may have a sign contained in the decimal digit code in a single character position. This requires a correction to be made to the decimal digit to include the over-holed sign. It is assumed that operand 1 requires an over-holed sign correction. A link signal ROP1 is sent from the control store 704-2 to the decoding logic 730-38. If the output signal ZTNSA 0-2 from the RTNS2 register of the register bank 730-32 and the ZTNSA switch 730-36 is encoded so that it represents a binary signal 000 or 011, whereby 9-bit characters with leading sign or are denoted by the following sign, then a logic output signal D1EQOVP of the decoding logic 730-38 is output with a high level. The logic signal D1EQOVP selects position 1 of a ZSSC switch 730-108 for an operand with the following sign _o Position 0 of the ZSSC switch is selected for the leading sign. The RLMP 4-6 signals are coded to point to the character position of the leading sign, and the RTMP 4-6 signals are coded to point to the character position of the trailing or appended sign.

The shift count signals ZSSC 0-2 are output to a shift device 730-145 in order to generate a logic signal Shift DBITT, the number of bits being determined by the counting signal ZSSC 0-2. The link signal DBITT is used as a link signal 0 for the overlaid Sign operations issued during the cycle in which the most significant word or the

030028/0881

Word lowest value from the cache memory for a leading sign = correction or "for a subsequent sign correction read X '/ ith _o The output signals ZCRDGM 0 = 7 of the shifter 730 = 145 _s are delivered to the ZID switch control logic 730 = 188 to the Select position 2 of the ZXD switch for the character = position, which is indicated by one of the signals ZCRDGM. 0-9 is displayed ;, x ^ elches occurs as a zero signal and indicates the over-punched sign position.

The RSGN register 730 = 134 is loaded with the corrected overlaid sign for operand 1 under firmware control ₀ The REXP = register 730 = 138 is loaded with the corrected overlaid sign = character for operand 2 under firmware = control ₀ A ZCRDG switch 730-136 selects the output signals RSGN 5-8 for the overlaid sign correction sign of operand 1 «The signals ZCRDG 0 = 3 are inverted by means of an inverter 730 = 186 and transferred to the position of the ZID switch 730- 150 given \ Jenn the word to which the corrected over-holed sign is added, is picked up by the cache picker 750 and switched through by the decimal unit 730 ₉ it is stored in the RDOD register 730-154 Da® characters in the prefix = character position is by replaced the corrected over-punched sign ZCRDG 0-3

The Boolean expression for the signal DBITT is § DBITT »(FOPlLD · DlEQOVP - (ETNSAl · FFDO + ZTNSA (I) • DMPEQ) + F0P2LD · D2EQOVP · (ZTNSBl ·

■ ETdTT + ZTNSA (I) · dmpeq))

where DMPEQ is a link signal 1 in the case ISt ₀ that the content of the RLMP register 730 ° 102 is the same as the content of the RTMP register 730 = 100 _{or the like}

The above equation indicates that the signal DBITT is set as logic signal 0 in the case that operand 1 or operand 2 an over-punched sign correction required during the load operation. The expression ZTNSA1 · FFDO shows a leading overpunched s sign, and the expression ZTNSA 1 · DMPEQ indicates a subsequent over-punched sign.

DlEQOVP - (DlIfX ROPl ZTNSAÖ) D2EQOVP - (ΒΒΪΤΖ ROPl ZTNSBU)

During the store operation, the sign is inserted into RSGN register 730-134 and into the operand word inserted via position 1 of the ZSMR switch 730-180, as previously described.

Decimal Unit 730 - Figure 3 - Load the STC mask into the RDOD register

The firmware initiates a DUCMD-203 Load STC Mask command in the RDOD command during the occurrence of the commands (STCA and STCQJ, which the Storing a character in the accumulator and in the quotient register concern. The decimal unit 730 receives the output signals RCHU 30-35 from the drawing unit 720; these signals are sent to position 1 of the ZID switch 730-150 via the buffer 730-168. Each of the output signals RCHU 30-35 leads as Link signal 1 to the fact that the corresponding six bits of position 1 of the ZID switch 730-150 as 1-Signa-Ie appear. These groups of six bits are stored in RDOD register 730-154 via ZDOD switch 730-152.

030028/0881

30ÜÜ045

4 shows the relationship between the hardware of the decimal unit 730 and the firmware in the execution control memory 701 = 2 “The execution addressing and branching circuits 701 = 1 send the control memory ^ memory location addresses ZECSA 0 = 12 to the execution control memory 701 = 2 _o The microword at the relevant address memory location is read out, and the bit positions RSCR 88 _P 89, 94 = 97 are fed to the input side belonging to the decimal unit 730 = the decoding logic 730-204, which has a conventional decoding logic circuit »The table 1 94-97 showing the bit configurations RSCR 88, 89, for the appropriate commands or commands _o DUCMD 200-206, 300 = 315 "

With the commands or commands DUCMD 200 = 206, 300-315 a status indicator is entered in the control logic 730-202. This unit consists of conventional FlipflopS; which is set in a conventional manner or reset, =

The i-cycle control state circuits 704-102 that are at the above-mentioned elsewhere (see U.S. Patent Application Serial No. "853,944) the signals FPOA [POP HOLDN and HOLDE, in order to control the timing of the decimal unit 730 for so-called assembly line or Effect pipeline operations of control unit 704. These signals are also the input side of the Status indicator control logic 730-202 supplied, the output signals of which are the input side of a decimal unit control logic 730-200 as well as the input side of the status indicator control logic 130-202 and the decimal unit control logic 730-200 are also fed to the decimal unit control logic 730-200, the output signals DUCMD of the decimal unit decoding logic 730-204 and the descriptor information supplied by the

Control unit 704-1 via the signal lines RSIR 21-35 and ASFA 33-36 in the registers shown in FIG. 3 has been recorded.

The operands stored in cache 750 are transferred to the operand processing unit 730-206, one word at a time via the signal lines ZDI 0-35 is transmitted. The operand processing unit 730-206 is determined by the descriptor information, the status flag signals and the register and switch control signals cause the operand word off cache 750 to remove non-operand and non-decimal digit characters from the word and convert the relevant word into 4-bit decimal digits and the four 4-bit decimal digits into up to align eight words with 4-bit decimal digits and pass the full word to execution unit 714 to transmit the signal lines RDOD 0-35. The output signals from the combination or logic unit 730-200 the signals PK-VCTR 0-3 and the signals RRLTRD, RREQRD, ADSZ and condition branch signals ZAHO are the branch addresses in execution addressing and branching circuits 701-1.

A clock signal controls the time relationships between the logic units according to FIG. 4.

4 illustrates the logic flow in the system. Those parts of the logic blocks according to FIG. 4 that relate to relating to the invention are illustrated in more detail in FIG.

B'ig. Figure 5 shows two typical commands that processed by the decimal unit 730. The AD2D instruction - which concerns the addition using two decimal operands, results in the operand

Ö3002Ö / 0881

30 0 0 ΰ Λ

from the address location designated by the descriptor 1 and with the address location indicated by the relevant descriptor 1 the specified format is added to the operand from the address memory location that occurs with the format, as specified by descriptor 2, with the resulting operand in the format and in the address memory parts are brought, as specified by descriptor 2 "

The AD3D instructions - relating to an addition by reference to three decimal operands - beitfirken ₉ that the operand from the address space, and in the format, as specified by the descriptor 1 ₉ added to the operand from the address space, and in the format is, as is determined by the descriptor 2, and that the resulting operand is accommodated in the format and in the address memory locations, as is determined by the descriptor 3 »The instructions or command word consists of 36 bit positions 00-35.

The command format includes a P = BItwelches as zero-bit EBCDIC data and as 1-bit ASC11 data.

The fields MF1, MF2 and MF3 describe the address modifications that are to be carried out with regard to the descriptors 1 _P 2 or ₀ .

The T bit enables the termination error.

The RD bit indicates the rounding operation free The opcode specifies the operation to be performed "As shown in FIG. 5 indicates the operation code 202-1 AD2D the instruction, and operation code 222-1 denotes the instruction or the instruction with I _e AD3D the interrupt = interruption lock bit is designated «,

O3QO28 / Q081

Purely the descriptor formats are Y1, Y2 and Y3 Main memory word locations of the character with the highest significance of the operand, which is defined by the descriptors 1, 2 or 3 is designated.

The O / E bit denotes the main memory word address as odd address or as an even address.

CN1, CN2 and CN3 denote codes that indicate the position of the most significant character within the Define the memory word of the operand which is identified by descriptors 1, 2 and 3, respectively. The codes depend on the data type, as shown below.

Codes characters-numbers

O 1 2 3

0 1 2 3 4 5 6 7

TN1, TN2 and TN3 are codes that define the numeric data type for descriptors 1, 2 and 3, respectively. A zero specifies a 9-bit data signal and a 1 specifies a 4-bit data signal.

Fields S1, S2 and S3 identify the sign and decimal types of descriptors 1, 2 and 3, respectively.

030028/0881

9-bit characters 000 010 100 110 4-bit characters 000 001 010 011 100 101 110 111

Unpacked data Packed data TM = 1

TNsQ Q ¥ P allowed or OVP not allowed

β σ

ö O

00 LS ₉ OVPj true to scale 00 Floating point, LS

01 LS, to scale 01 LS to scale

10 TS, to scale 10 TS to scale

11 TS, OVPp to scale 11 no sign,

true to scale

LS = leading sign

TS = following sign

OVP = perforated sign

SF1, SF2 and SF3 denote the scale or "scale factors of descriptors 1, 2 or, 3 °. The decimal point is located behind the digit with the lowest value ₀ A positive scale or" scale factor shifts the decimal point by as many positions to the right "On negative scale or scale factor _e shifts the decimal = komnia to as many positions to the left.

N1, N2 and N3 are the number of characters in the operand, which number is determined by the descriptors 1, 2 and »3, respectively. N1, W2 and N3 can be 4-bit codes, the designate the registers that contain the length of the operand concerned. To describe the invention however, N1, N2 and N3 are the number of characters in that Operands.

Decimal Unit 730 - Figure 3 - Vector Branch Data

Referring to Figure 3, the decimal unit control logic generates 730-20 the control signals 1PKVCTR, 2PKVCTR and 4PKVCTR to the Occurrence of the DUCMD command signals of the decimal unit 730, as has been described above. The vector branching logic 730-15 signals have been supplied which are indicative of the properties of the operand. The outputs of decode logic 730-38 and

030028/0801

730-40, which will be described later, define the operand as a floating point or as an overlaid sign or as scaled operands, provided they consist of 4-bit or 9-bit decimal points. the Signals ZTNSA1 and ZTNSB1 indicate an operand with a subsequent sign if they are used as a logic signal 1 occur and they indicate an operand with a leading sign when used as a logic signal Zero occur. The signals ALNS 3-5 and the signals ALNDA 0-3 and ALNDB 0-3 designate the operand that has a set length of more than 63 decimal digits or a length of less than 63 decimal digits or has a length equal to 63 decimal digits. The detailed link arrangement is illustrated in fig.

The output signals PK-VCTR 0-3 of the vector branching logic 730-15 are sent to execution addressing and branching circuits 701-1 upon the occurrence of the control signals 1PKVCTR, 2PKVCTR and 4PKVCTR are output to the execution control memory 701-2 1 to display the next microword to be processed by the system.

Referring to Fig. 8, a PK-VCTR switch 15-72 generates a-d vector branch signals PK-VCTR 0-3 on microword signals which are given to the decimal unit 730. The microword signals generate DUCMD command signals or command signals that are linked to their linkage or Combination with the status identification signals generate control signals 1PKVCTR, 2PKVCTR and 4PKVCTR. These Control signals are applied to input selection terminals 1 and 4 of switch 15-72; they lead to selection one of eight inputs from each of the four areas of switch 15-72 a-d.

03ÖÖ28 / O881

While processing numeric commands that are not decimal — numeric commands, the Decimal unit 730 ineffective, whereby the input connection O of switch 15-72 a-d is activated.

The type-length-vector signals are fed to the input terminal 1 of the switch 15-72 ad. The DSHORT signal is applied to input terminal 1 of switch 15-72a. If the ALNS adder 730-24 indicates that the set length of the operand is greater than a binary 16 or equal to the binary 1b, then one or more of the input signals ALNS 3 = 5 for the AND / NAND gates 15-32, 15-34 or 15-36 issued as logic signals 1. One or more of the output signals are fed as logic signals O to the inputs of an AND / NAND element 15-38. The output signal ALNSGTE16 is fed to the input of an AND / NAND gate 15-50. If this is not a decimal = multiplication / division command, then the output signal DLNSCLDGTE 16 is output as logic signal 0. This signal, which is fed to the input of an AND / NAND element 15-74, causes the output signal DLüMg is emitted as a link signal 0 _e The signals ΑΧΗΠΚΤ, ALNDA2, ALNDB1 and ALNDB2 are the inputs of the AND / NAND gates 15-40, 15-42, 15-44 or; _o 15-46 fed. A logic signal 1 is fed to the other input terminals. The output signals of the AND / NAND gates 15-40 and 15-42 are fed to the inputs of an AND / NAND gate 15-52, and the output signals of the AND / NAND gates 15-44 and 15-46 are fed to the inputs • ines AND / NAND gate 15-54 supplied. The output signals ALNDAGTE 16 and ALNDBGTE 16 indicate, as logic signals 1, that the length of operands 1 and 2 is shorter than 16 decimal digits. If the operands are not floating point operands and if the set length

030028/0881

including the scale factor setting is less than 16 decimal digits, then the signal DLONG shows, the output signal of the AND / NAND gate 15-74, as a logic signal 1, that both operands as short Operands are or are being processed. The signal DLONG is the input of an AND / NAND gate 15-56 fed. The output signal DSHORT indicates, as logic signal 1, that the operand is long Operand is processed. The signal D12EQ0VP is the the other input of the AND / NAND gate 15-56 supplied; as logic signal 1 indicates the relevant signal, that neither operand 1 nor operand 2 has an interleaved sign, which is the requirement for is a short operand.

The DSHORT signal indicates, as logic signal 1, that a short operand is the input of an AND / NAND element 15-58 is fed. The signal 2W§IS shows as Logic signal 1 indicates that an operand with 9 bits per Character is delivered to the other input of the NAND gate 15-58. The output signal DHHORT 9 is used as a link ssignal O to an input of an AND / NAND gate 15-62 issued The output signal DLNGORST 9 is sent as a logic signal 1 to the input terminal 1 of the Switch 15-72b released »which is a short operand is displayed with nine-bit pr @ characters o The link signal 0 is fed to the input terminal of switches 15-72c and dο

The signals TDBO and TDB1 are applied to input terminals and 3 of switch 15 ~ 72b and switch 15-72c, respectively. The Boolean expressions have already been described above; they indicate the number of delay cycles between the cycle _s in which the read request is made with respect to the cache memory 750 _p usid the point in time aa ₉ at which a complete reading of the

030028/0881

Execution unit 714 received is ₀ The signal ARWC 6 of the ARWC adder 730-60 is fed to the input connections and 3 of the switch 15-72d5 it indicates a 1-word operand when it occurs as a logic signal O, and it shows a 2 · = Word operands on if it occurs as logic signal 1, _etc.

The input connections 4 and 6 of the switch 15-72 a ~ d are selected for the descriptor 1 vector or "for the memory = vector operations." The signal ROP = I from the control memory 704-2 indicates 1 as a logic signal, that a uberlochter sign operand one input of an AND / NAND gate is supplied 15-2 _o the signal ZTNSAO which indicates an operand with nine bits per character is referred to as link 1 signal to the other input of the AND / NAND-GIiedes 15 = 2 »Each input signal occurring as logic signal 0 causes the signal D1NEW 9, which is fed to an input of an AND / NAND element 15-14, to appear as logic signal 1. The signals ZTJMSA1 and ZTNSA2 are fed as logic signals 1 to the other inputs of the UJMD / NAND element 15-14 »The output signal D1EQFLP shows a floating point operand as logic signal 0; it is fed to the input of an AND / NAND gate 15-64. The output signal D1FLPORTSO, which occurs as logic signal 1, shows a floating point operand as such a logic signal _o

If the signals ROP-1 and ZTNSAO occur as logic signals 1, the output signal D1NEW9 of the AND / NAND element 15-2 occurs as logic signal 1. If the signal DBITX occurs as logic signal 1, then the output signal D1EQOVP of an AND / NAND element 15-22 will appear as logic _{signal 0 o} As a result, the output signal D12EQ0VP of an AND / NAND element 15-30 will appear as logic signal 1. When the signal ZTNSA1 as

030028/088 1

Link signal 1 occurs, whereby an attached or subsequent sign is displayed, the Output signal DIEQTSO of a NAND gate 15-26 as logic signal 0 lead to the output signal D1FLPORTSO of the AND / NAND gate 15-64 as a logic signal 1 occurs. The signal D1FLPORTSO is used as a logic signal 1 to the input connections 4 and of switch 15-72b, creating a floating point operand or an operand with a punched subsequent Sign is displayed.

The output signal D1EQ0VP of the AND / NAND gate 15-22 is applied to the input terminals 4 and 6 of the switch 15-72a which means that an operand with an overlaid sign is displayed.

The signal DBITX then occurs as logic signal 1, when the signals ZTNSA1 and ZTNSA2 are fed as logic signals to an AND / NAND gate 15-4, whereby a Unsigned operand or an interleaved subsequent sign are displayed, or signals ZTNSAO, ZTNSA1 and ZTNSA2 are supplied to an AND / NAND gate 15-6, which results in a floating point operand comprising 9 bits per character or an operand with an overlaid leading sign is displayed. The output signal D1EQFLP '9 of a AND / NAND element 15-6 introduces the output signal DBITX of AND / NAND element 15-16 as logic signal 0 Link signal 1 over.

The logic signals 0 are selected by the connections 4 and 6 of the switches 15-72 c and d. The firmware produces a zero result and an overflow check during the memory vector operation. The descriptor Z vector selects input terminal 5 of switch 15-72a-d. The signal D2EQ0VP is applied to terminal 5 of switch 15-72a. If this

030028/0881

30GCKHS

Signal occurs as logic signal 1, it indicates an operand with an overlaid sign _o The signal D2EQ0VP is generated in a corresponding manner as the signal D1EQOVP, which indicates an operand 1 with an overlaid sign.

The signal D2FLP0RTS0 is generated in the same way as the signal D1FLPORTSO ₅ , namely via the AND / NAMD gates 15-28 and 15 ~ 66 _O The relevant signal is fed to the connection 5 of the switch 17 = 72b in order to set a floating point To display operands or an operand with an overlaid subsequent sign

The input connections 5 of the switch 15 = 72 C ₉ d carry a logic signal O ₀

The long input vector selects the input connection 7 of the switch 15-72 a »d _e The signals D1EQFlP and D2EQFLP are fed to the inputs of an IMD / NAND element 15-48. The output signal D12EQFLP is fed to the inputs of the AND / NAND gates 15 = 60 and 15-70 D12FLP0R0VP in binary signals 1o The input connection 7 of switch 15-72 a and switch 15 = 72 b indicates with a link = signal 1 of the firmware ₉ that the descriptor = 1 = and descriptor = 2 "vectors are to be executed

l'Iemi the signal D12E13FLP occurs as link signal 1, XTO is shown by scaled or ₀ scaled operands _p the signal ALNSLTE63 as link signal 0 indicates a length that is shorter than or equal to 63 decimal digits _o This signal is the input of the AND / NAND gates 15-60 and 15-68 supplied "The output signals D12FLP0REL show as logic

signals 1 indicates that both operands have a length that is less than or equal to 63 decimal digits. That Signal D12EQ0VP becomes the other input of the AND / NAND gate 15-68 fed. The output signal D12OVPL63 is used as a logic signal O to the input of the AND / NAND gate 15-70 fed. The output signal D12FLP0R0VP indicates, as logic signal 1, that both operands with an overlaid sign and that the lengths are shorter than or equal to 63 decimal points.

The signal ALNSLTE63 is generated as logic signal 0 at the output of an AND / NAND element 15-8. The input signal ALNS3 shows, as logic signal 1, a length that is greater than 63 decimal digits. The FMYDV signal occurs as logic signal 1 on _P because it is not a multiplication / division operation. The signal D12EQFLP occurs as logic signal 1 ₉ since no operand is a floating point «operand»

The invention has thus created a microprogrammed data processing system, in which the system throughput is increased during the processing of decimal-numerical commands by an arrangement that is caused by command or instruction descriptors prior to the inclusion of operands, the decimal digits of the operand words such as align the words _s which aufnia the arrangement in question from the memory

The descriptor for each operand includes the scale or _a scale factor, the location of the sign, the position of the character most significant within the word, regardless of whether it is a floating point operand, or an operand with a scale factor, The information in question also includes the number of bits in the respective decimal symbol, either four or nine bits, and the length of the operand.

030028/0381

30000Α5

The arrangement is given by the descriptor = information causes the two operands to be aligned for processing,

The arrangement indicates to the microprogram the properties of the operand being processed, making the correct one Microprogram subroutine is enabled, that is, if the operand is a floating point operand or an operand with a scale number, 4 ~ bit ~ decimal ~ digits or 9 ~ bit »decimal digits, a perforated, has leading sign or trailing sign, has a set length that is shorter than or equal to 63 decimal digits, regardless of whether the operand is a long one Operand or a short operand, regardless of whether the resulting operand is zero or one Has overflow.

The arrangement describes the operands of zone bits, signs, exponents and characters that are not operand characters when the operand in question is stored in memory. The order in question adds add zone bits, signs, exponents and non-operand characters to the resulting operand if the relevant resulting operand is stored in the memory. The control signals for releasing and adding information is released by slider link elements

The arrangement in question takes up a long operand that is larger than a certain number of words, which is the result of the calculation, composes the resulting operand in accordance with an instruction descriptor and transmits the resulting operand Operands to the memory.

030028/0881

The arrangement takes a prediction and indication of the number of aligned words in the operand for the firmware during the processing of short operands, i.e. with 15 decimal digits or less Digits, the operand in question being taken by the execution unit that performed the decimal instruction executes. Furthermore, the number of delay cycles is determined by the arrangement in question is predetermined and indicated between the time a read request is made from the cache memory of the first word of the operand stored in the cache, and the time at which the first Word aligned in the order in question and ready for transmission to an execution unit is composed.

In response to the occurrence of a micro-word which indicates that the result of the decimal-numerical calculation is a short operand, which means that a certain Number of words or fewer words, and generated in accordance with an instruction descriptor the relevant arrangement a counter position with regard to the number of words of the resulting operand, and the decimal unit makes a transfer to memory.

030028/0881

Claims (1)

DIPL. ING. HEINZ BARDEHLE Munich, ^{l 2> Jan 138} ° PATENT ADVOCATE File number: My reference: P 2988 Claims Data processing system with a cache memory (scratch pad memory) for storing operands and instructions, each of which contains an operation code part and descriptor information which is used to describe properties of the operands, characterized in that an execution control unit (701) is provided which stores micro-words to which operations can be carried out which are determined by the operation code part of the relevant instructions, that a control unit (704) is connected to the cache memory (750) and to the execution control unit (701), that the cache memory (750) and the control unit (701) have Microwords transmit one of the instructions and the descriptor information indicating a decimal numeric operation to the control unit (704) from the cache memory (750) that the execution control unit (704) in response to the microwords the operation code part of one of the instructions to the execution control unit (701) practice r indicates that the execution control unit (701) selects a series of micro-words in response to the operation code part of the relevant instruction, that the decimal-numerical operation can be carried out in response to the relevant series of micro-words, that a decimal unit (730 ) is connected, which stores signals indicative of the descriptor information for the relevant row of micro-words, the descriptor information signals the decimal 030028/0881 Cause unit (730) to align the operands in the case before the operands are included that the relevant operands are transferred from the cache memory to the decimal unit, and that with the decimal unit (730) an execution unit (714) which the aligned operands from the relevant decimal unit to picks up the row of microwords in question and performs the decimal arithmetic operations. 2. System according to claim 1, characterized in that the decimal unit is a decimal unit control device which is connected to the control unit and which respond to control status signals the descriptor signals in the decimal unit that the decimal unit controller stores an adder means responsive to the descriptor signals for register and switch control signals generated, and that with the cache memory and the execution unit an operand processing device is connected, the operands on the occurrence of the relevant series of micro-words from the cache memory and the occurrence of the relevant register and switch and control signals to align the operands for transfer to the execution unit. 3. System according to claim 2, characterized in that the decimal unit control device is a decoder which is connected to the execution control unit and which is directed to the relevant A large number of selected signals from the micro-words generates a large number of command signals, that with the decoder a status device is connected to the relevant Responds to a large number of command signals and the G3DQ28 / Q3S1 ~ ⁵ ~ 300004. is connected to the control unit and in response to a plurality of control status signals a plurality of status identification signals generated, and that with the relevant = the control unit, with the status device and the decoding device is connected to a control device which is applied to the relevant plurality of control status signals, to the descriptor signals, the plurality of status indicator signals and the relevant plurality of command signals responds and which generates the register and switch = control signals, the relevant control device connected to the status device for generating the plurality of status indicator signals is. 4. System according to claim 3 _S, characterized in ₉ that the control device contains a memory device which is connected to the control unit and stores the descriptor signals in response to the relevant plurality of control state signals, which are indicative of the descriptor information, and that with the memory device one Adder device is connected _s which responds to the status identifier = signals and the descriptor signals and generates and stores the recording = counting signals which are indicative of the number of words in the operands? able wherein to generate the adder further memory Sehiebezählsignale in question to be included by the decimal unit of the cache memory., and the further transmission count signals generated _s which characteristic are to be transmitted by the decimal unit to the execution unit for the number of Wörterp ₉ “Which are characteristic of the number of decimal digits of the operands ^ which are to be shifted to the decimal unit ο 5. System according to claim 4, characterized in that the descriptor information is used to describe properties of the operands and comprises a first descriptor for describing the first operand and a second descriptor for describing a second operand that the first operand and the second operand by the Decimal unit are aligned in such a way that they can be transmitted to the execution unit, which allows the decimal-numerical operation to be carried out on the relevant row of micro-words using the first operand and the second operand, so that the descriptor information includes signals which are characteristic of a Scale factor by which the position of the decimal point of the relevant operand is displayed _? that the descriptor information further comprises signals which are indicative of a length of the operand ^ such that the number of decimal points is displayed in the operand concerned, that the descriptor information further includes signals that are indicative of a character pointer position, such that the position of the most significant character is the operand displayed within a word, and further comprising a display provided it v / ill if the word in question has an odd address or even address _p and that the descriptor in = includes formation signals lcennzeichnent for the decimal type the decimal point of the operands ^ in such a way that the number of bits contained in the decimal point ₉ which are received by the cache memory is displayed, as well as the position of a sign, an indication being provided about whether the operand concerned is a floating point -Operand or an operand with a number factor _e U30Q28 / O8S1 6. System according to claim 5 _S, characterized in that the storage device comprises a first scale factor storage device for storing signals which are indicative of the scale factor of the first operand, and a second scale factor storage device which stores di @ signals which are indicative of the scale factor of the second operand, and that signals indicative of the first or the second scale factor can be picked up by the control unit in response to the occurrence of the relevant plurality of control status signals, _o 7. System according to claim 6, characterized in that the adding device is a scale factor adder includes means associated with the first and second scale factor storage means for Calculation of a scale factor difference is connected. 8. System according to claim 5, characterized in that the memory device also has a first length = memory device for storing signals, which are indicative of the length of the first operand, and a second length storage device = contains device which is used to store signals which are indicative of the length of the second Operands that for the first length and the second length characterizing signals from the control unit can be recorded upon the occurrence of the plurality of control state signals in question, and that the storage means further comprises a first decimal-type storage means for storing signals that are characteristic of the decimal = type of first operands, and a second decimal-type memory device for storing v @ n signals C3Ü02S ' which are indicative of the decimal type of the second operand, where the signals which are characteristic of the first or second decimal type, from the control unit to the occurrence the relevant plurality of Steuerstatusssi signals can be picked up. 9. System according to claim 8, characterized in that the adding device comprises a first adding device for an operand of set length and a second adder device for an operand Has set length that the first adder means with the first length memory means and the first decimal type storage means for calculating a first set length operand is connected and that the second adder means with the second length memory means and with the second decimal-type memory means for calculation of a second operand of the set length, the set length of the first operand and second operand the number of decimal digits in the first operand or in the second operand. 10. System according to claim 9, characterized in that the adding device is a scale factor switch device which is connected to the scale factor adding means and which is based on a Signal from the scale factor adder means the operand with the larger scale factor indicated 11. System according to claim 10, characterized in that the adding device is a length-scale factor adding device contains that with the scale factor switch device and with the 030028/0831 Scale factor adding means is connected so that the calculation of the set length of the operand with the larger scale factor can be performed. 12. System according to claim 11, characterized in that the adder device contains a set length = switch device which is associated with the length-scale factor adder device , with the length set for the first operand Adder device and with the length set for the second operand = device for selecting the operand set Length is connected that the set length switching device set the first operand Length of the length scale factor = adder device and the set length second operand from the length set for the second operand provided adder device in the case select- = zuwähl-n allows the first operand to be the larger scale factor and that the set Length switch device the second Operands set length from the lengths = · scale factor adder and the first Operands set length from the length set for the first operand Allowed to select a oiler device in the event that that the second operand has the larger scale factor = o 13o system according to claim 12, characterized in that the adder device contains a transmission word counting adder = device which is associated with the set Length switch means for calculating the number of words of the operand connected by the Decimal unit to be sent to the execution unit, System according to Claim 13 _9, characterized in that the adder device contains a transmission word counting memory device which is connected to the transmission word counting adder device for storing signals which are indicative of the number of words in the operand is to be sent from the decimal unit to the execution unit c System according to Claim 14, characterized in that the memory device contains a first Xeiohenzsiger memory device for storing signals which are characteristic of the character pointer position of the first operand, and that. said memory means includes a second character pointer · = storage means for storage of signals that are indicative of the character = pointer location DES second Operaaden _P uobei signals that are indicative of the first and second character pointer position of the respective control = unit on the control state signals towards are acceptable. 1BO system according to claim 15, characterized ₉ that the Addierersinrichtung a Zeichenz @ igerwort ~ count = adder © nfcMlt associated with the srstsa Zeichenzsigez ^ Spsichereinriehtungp with the first long-Speiehe ^ eiariohtung and represents © rstsn deci "Max-type storage device For the calculation of the number of words of the first operand, which is taken from the Caehespsiola by the decimal unit, and that the relevant adding arsenal direction is the second character pointing device, with the maximum length memory device and with the second decimal ^ Type memory device for calculating the number of words of the second operand is connected, that is, the decimal unit is able to take up from the cache memory. ~ ⁹ ~ 3Ü0J0A5 17o system according to claim 16, characterized in that the adder device contains a recording word = counting memory device which is connected to the recording word count adder. direction is connected in such a way that the word counter position of the operand can be stored, which can be taken from the cache memory by means of the decimal unit ₀ 18o system according to claim 17 _9, characterized in that the adder device contains a character pointer adder device which is connected to the set length switch device, the first character pointer memory device and the first decimal-type memory device for calculating the number of decimal digits by which the first operand is shifted in the decimal unit, and that the respective adder device is connected to the respective set length switch device of the second character pointer memory device and the second decimal-type memory device for calculating the number of decimal digits by which the double operand is shifted in the decimal unit » System according to Claim 18, characterized in that the adder device contains a digit shift memory device which is used to store the number of decimal digits by which the operand is shifted in the decimal unit ₀ 2Oo system according to claim 19 _P, characterized in that the operand processing device contains a receiving device which is connected to the cache memory for storing words of the operands which are transferred from the cache memory to the relevant row of micro-words, that with the receiving device and the adder a Shifting device is connected, the words of the operands on the shift counting signals align ^ and that with the sliding device and the execution unit a transmitting device is connected, which the aligned words to the execution unit towards the relevant Series of micro-words ", 21. The system of claim 20, characterized ₉ that the receiving means includes an input Ragistereinrichtung ,, which is connected to the cache memory for storing the words of the operand _9, the _s were taken from the cache memory to the relevant number of the micro-words out with that the input register is connected to an input register switch device which, in response to the signals which are characteristic of the decimal type for receiving the words from the input register, derive zone bits from the relevant words, and that a word enable device is connected to the relevant input register device and the adder device which, in response to the record count signals and the send count signals, enables the words of the operands for alignment, the registers, and switch control signals including the record count signals and the send count signals. 22. System according to claim 21, characterized in that the transmitting device has a sign and Includes exponent separator which is connected to the displacement device and which on Responds to signals that are indicative of the position of the decimal digits and the least significant decimal digits within their corresponding words of the operand, such as that the sign and the exponent can be detached from the relevant operand, which is from the 030028/0881 relevant sliding device is included " 23c, data processing system, in particular according to one of claims 1 to 22, characterized in that a memory device is provided for storing operands and commands, each of which contains an operation code part and also descriptor information _P which is used to describe properties of the operands The instructions comprise an operation code part which designates a decimal = numerical operation to be carried out, so that a decimal unit is connected to the memory device in such a way that it is able to accept the operand words and signals which are characteristic of the descriptor information in question, where = in this recording in response to signals takes place, which are characteristic of the decimal-numeric command that the decimal unit contains a decimal unit control device and generates register = and switch control signals in response to the command signals and the descriptor signals, that the decimal unit also has an operand processing device contains direction which receives the operands from the memory device in response to the relevant command signals, and which aligns the operands to the register and switch control signals Mn ^ and that an execution device is provided which is connected to the decimal unit and which is used to receive the Aligned operands are used to carry out numerical operations that are specified by the relevant decimal arithmetic command 24ο System according to claim 25, characterized in that that the control device includes a storage device associated with the storage device connected and responding to the command signals the descriptor information stores that an adder device is connected to the storage device which, in response to the command signals and the descriptor signals, generates recording counting signals which are indicative of the number of words of the operands to be recorded by the decimal unit from the storage device that the concerned device also generates transmit count signals which are indicative of the number of words to be transmitted from the decimal unit to the execution unit, and that the device concerned generates shift count signals which are indicative of the number of decimal digits by which the relevant Operands in the decimal unit are to be shifted ₉ 25. System according to claim 24, characterized in that the adder device controllable by the descriptor device contains a scale factor adder device for calculating the scale factor of the relevant operands and for displaying an operand with a larger scale factor _o 26. System according to claim 25, characterized in that the scale-factor adder means connected and responsive to the Deskriptorsignale adder means includes means responsive to operand set length Äddierereinrichtung _s the operand in question is used to calculate the adjusted length ,, wherein the operand with the larger scale factor contains the relevant sac factor in the set length. 27. System according to claim 26, characterized in that that the adder means a transmission word count adder means contains that with the setting 030028/0881 length adder device for generating second word counting signals is connected, which are indicative of the number of words in the operands that go from the decimal unit to the Execution unit are delivered, 28. System according to claim 27, characterized in that the adder device which responds to the descriptor signals contains a received word counting adder _{device which allows the received word count signals to be generated which are indicative of the number of words of the operands 9} from the memory device to the decimal unit to be handed in. 29. System according to claim 28, characterized in that that the responsive to the descriptor signals Adder device contains a digit shift adder device for generating shift signals, which are indicative of the number of decimal digits by which the operands are sent be shifted in the decimal unit «, 30. System according to claim 29, characterized in that the operand processing means a with the storage device connected recording device, which in response to the command signals Storing the operands allows the recording device to also use the adder device is connected and the receive count signals and the send count signals out the operands for a Alignment releases, and that with the recording device and with the adding device a sliding device is connected, which aligns the relevant operands to the shift count signals, the send count signals, the receive count signals and the shift count signals in the register 030028/0831 and switch control signals are included. 31. Data processing system, in particular after a of claims 1 to 30, characterized in that a cache memory (notepad memory) for Storage of operands and instructions is provided, each of which has an opcode part and a descriptor information for describing Properties of the operands has that an execution control device for storing Microwords are provided in response to the operations carried out by the relevant Instructions are designated that a control unit with the cache memory and the Execution control unit is connected that the cache memory and the control unit to the relevant MicroWords indicate one of the commands and the descriptor information, which is a decimal-numeric Operation denotes transferred from the cache memory to the control unit that the control unit in response to the microwords, the opcode portion of one of the instructions to the execution control unit that the execution control unit transmits to the operation code part of the relevant Command selects a series of microwords, the decimal-numeric Operation is carried out that a decimal unit is connected to the control unit and the cache memory which stores the descriptor information in response to the occurrence of the relevant series of microwords, that the descriptor information causes the decimal unit to align the operands in the event that this to the decimal unit from the cache be transmitted that an execution unit is connected to the decimal unit, which on the relevant Series of microwords takes up the aligned operands from the decimal unit and Performs decimal arithmetic operations such that a 030028/0881 resulting short operand is generated for transfer to the decimal unit, and that the decimal unit takes the resulting short operand and the relevant microword towards accommodating the short operand in data words and towards the descriptor signals transfers to the cache memory » 32. System according to claim 31 »characterized in that the decimal unit contains a decimal unit control device which is connected to the execution control unit and to the control unit and which responds to a plurality of selected signals from the microwords from the execution control unit and to the Responds to descriptor signals and generates register = and switch _{control signals 9} and that an operand processing device is connected to the execution unit and the cache memory; Aligns control signals towards the short operand and shuffles it for transfer to the cache memory 33 »System according to claim 32 _P, characterized in that the decimal unit control _{device contains a decoding device 9} which is connected to the execution control unit and which generates a large number of command signals in response to the large number of selected signals from the micro-words ₉ that with the decoding device one Status device connected XSt ₉ which responds to the relevant plurality of command signals that the status device is connected to the control unit and generates a plurality of status indicator signals in response to a plurality of control status signals that a control = -16- 30QQQ45 device with the control unit, with the status device and the decoding device is connected and on the plurality of control status signals, on the plurality of status indicator signals, responds to the plurality of command signals and to the descriptor signals and generates the register and switch control signals, and that the control device concerned also is connected to the status device for generating the plurality of status identification signals. 34. System according to claim 33, characterized in that that the control device contains a storage device which is connected to the control unit and which is responsive to the plurality of control state signals for storing descriptor signals which are characteristic of the descriptor information, and that an adder device is connected to the storage device and to the status identification signals and generating the descriptor signals to send count signals and stores, which are indicative of the location of the word most significant of the short Operand to be transferred to the cache memory from the decimal unit, and that the relevant Adder device is also able to generate and store shift counting signals which characterize are for the number of decimal digits by which the short operand in the decimal unit is used for a transfer is moved to the cache » 35. System according to claim 34, characterized in that the adder means a scale factor means, an operand length adder means and a sign = and decimal type display device, which is connected to the storage device and which responds to the status identifier signals and the descriptor Q3ÖÖ. (P signals the transmit counting signals are generated and stored » System according to Claim 35 _»9 that the adder includes a character pointer adder, the scale factor means the operand length adder, the signal means and the decimal type display device, which is connected to the memory means and the status indicator signals and the Deskriptorsignale the shift count signals are generated and stored, and that the send count signals and the shift count signals are used to generate the register and switch control signals » 37. System according to claim 36, characterized in that the operand processing device is a receiving device which is connected to the execution unit for receiving signals which are characteristic of a first word and a second Word of the short operand, with the signal being picked up in response to the large number of command signals, that a selection device is connected to the register device, which is responsive to the register and switch control signals hin selects signals which are characteristic of the first word or the second word, or the Signals outx-counts which are characteristic of a Word, which contains numerical zero digits, that with the register device a shift device is connected, which shifts signals in response to the shift counting signals which are indicative of the first word or the second word or the word containing the numeric zero digits, i-robei a number of the digit positions is determined by the shift counting signals j, and that with the shifter a Mixing and transmitting device is connected, which respond to the register = and switch control signals the short Forms operand words for transfer to the cache memory. 38. System according to claim 37, characterized in that the adding device is a decrementing device contains which, in response to the command signals and the status indicators, the send counting signals in decreases (decrements) the case that the short operand word from the decimal unit to the cache memory is transmitted. 39. System according to claim 38, characterized in that the selection device is operated in response to selection signals which are indicative of the word containing numeric zero digits, operating on the Occurrence of the shift count signals and the send count signals occurs, which are coded such that a Number is designated, the value of which is greater than or equal to a first specific value, that the selection device is also used to select signals which are characteristic of the second word, is effective on the transmit count signals which are coded to designate a number whose Value is equal to a second specific number that the selection device also allows signals to be selected, which are indicative of the first and second words on the shift count signals and the transmission count signals encoded to designate a number whose value is equal to one third specific number is that the selection device is also effective for selecting signals that characterize are for the first word, the operation being based on the shift count signals and the send count signals takes place, which are coded in such a way that a number is designated whose value is equal to a fourth specific Number, and that the selection device is effective for the selection of signals which are characteristic of the 030028/0881 Word containing numeric zero digits, the operation being based on the shift count signals and the transmit count signals which are coded to designate a number whose value is less than that fourth specific number concerned. 40. System according to claim 39, characterized in that the consecutive particular numbers of the first specific number are generated based on the fact that the relevant successive specific Numbers are diminished. 41. Data processing system, in particular according to one of claims 1 to 40, characterized in that a memory device is provided for storing operands and commands, each of which has an operation code part and descriptor information for describing properties of the operands, that the commands have an operation code part, denotes a decimal numerical operation _s to be executed, that the memory means a decimal unit is connected, which serves to receive signals, which are indicative of the descriptor that the decimal further for transferring operands between said memory means and the decimal unit on signals used toward that are indicative of the decimal numeric order that an execution unit is connected to the decimal _9, the _S is for receiving a first operand and a second operand for performing an operation represented by the respective n decimal-numeric instruction is designated in such a way that short operand errors for the transmission to the decimal unit are generated in response to signals which are characteristic of the decimal-numeric instruction in question, and that the decimal unit the short operand in question for assembly in data words on the descriptor » signals for the transmission to the pe icher device · = direction picks up _β 42 _o The system of claim 41, characterized indicated that the Deziaaleinheit includes a controller _s connected to the memory means and to said command signals and the Deskript ©! ³ signals towards register and switch <= control signals generated, πκιά that an operand = processing device is connected to the execution device and to receive the short operand words from the execution unit in response to the command signals and to the register = and switch = Control signals to the short operands for the transmission to the storage device is able to generate. 43. System according to claim 42, characterized in that the control device is a storage device which is connected to the memory device and which, in response to the command signals, the Deskri torsigna-Ie stores that an adder device is connected to the storage device, which is based on the Command signals and the descriptor signals generated and stored in the form of send count signals, which characterize are for the position of the word with the highest significance of the short operand that points towards the storage device is to be transmitted by the decimal unit, and that the relevant adder means for generating and Storage of shift counting signals is used, which are indicative of the number of decimal digits to which the short operand in the decimal unit is shifted for transmission to the storage device, wherein the send count signals and the shift count signals can be used to generate the register and switch control signals » 44. System according to claim 43, characterized in that the operand processing device has a recording 030028/0881 device contains ₈ is ait said executing means for receiving signals associated, which are characteristic for a first word and a second word of the short operand "wherein the Signalaufnahoe to the command signals is carried out _p and that Oine" d © r register means selection means connected to the register · = and switch = control signals signals ₉ which are characteristic of the first "tfort or the second word, or signals from = s, which are indicative of a numeric JMull ~ word containing digits » 45o system according to claim 44 »characterized in that the adding device contains a decrementing device? which, in response to the command signals, allows the transmission counting signals to be reduced in the event that the short operand word is transmitted from the decimal unit to the memory device 46β System according to claim 45, characterized in that the selector allows to select signals which are indicative of the numerical zero = Word containing digits, xrobei the selection in question in response to the shift count signals and the send count signals, which are encoded in such a way that a number is established whose value is greater than a first specific value or which is equal to this value, that the selection device also allows to select signals which are characteristic of the second word, the selection takes place in response to the transmit count signals, which are coded so that a number is fixed, the value of which is the same a second specific number is that the selection means for the first word and the second word identifying signals to be selected in response to the shift count signals encoded so that a Number is set, the value of which is equal to a third specific number, -that the selection device also signals identifying the first word to the 030020/0 · '::, Occurrence of the shift counting signals and the sending counting signals Mn which are coded in such a way that a number is designated ISt ₉ whose value is equal to a fourth specific number ₉ and that the selection device is also operated in such a way that it selects signal © permitted ^ which are characteristic of the numerical zero ~ ZIfferm containing® Tfortp where the relevant selection is made on such coded shift counting signals and sending counting signals ₉ that a number is designated whose hoard is less than the fourth specific number _o 47ο Systeia n @ .ch _s to claim 46 characterized in that the successive _ΰ certain numbers from the first predetermined number will be generated based the fact that the consecutive numbers are given reduced. 48. Data processing system, in particular according to one of claims 1 to 47, characterized in that a Cache memory is provided for storing operands and instructions, each of which has an opcode part and furthermore has descriptor information for describing properties of the operands, that an execution control unit is provided for storing micro-words upon their occurrence the operations indicated by the instructions in question are performed with the cache memory and a control unit is connected to the execution control unit, the cache memory and the control unit in response to the microwords one of the commands and the descriptor information, which is a decimal-numeric Operation denotes transferred from the cache memory to the control unit that the control unit is on the relevant microwords to the operation code portion of the relevant one instruction to the execution control unit hin transmits that the execution control unit 030028/0881 ~ 23 = selects a series of micro-words in response to the operation code part of the relevant instruction, the occurrence of which results in the decimal-numerical operation from = · perceptible ¹ “ that a decimal unit is connected to the control unit and the cache _{memory 9} for storing the descriptor information and for receiving the Operands for the relevant row of microwords serves _ΰ that the decimal unit is caused by the Deskriptoriaformatioxi to determine whether the operands are to be processed as short operands or long Qperandea-, whereby the short and lay operands are aligned ₅ and that with the DQgimaleinheit an execution unit is connected, which was used to receive the Aaligned short and long operands to the relevant row of micro-errors and to carry out the Bezimal = arithmetic operations 49. The system of claim 48 _p characterized in that the decimal unit contains a decoding device which is connected to the ÄusführungsSteuereinheit and which generates a selected field of the respective series of micro words towards a plurality of command signals to indicate the operation that the Dezimalein = · that is, that a status device is connected to the decoding device which responds to the relevant plurality of command signals, that the status device is connected to the control unit and generates a plurality of status identification signals in response to a multiplicity of control status signals, that the status identification device responds to the relevant plurality of status identifier = - signals a sequence of status identifier signals for controlling the decimal unit operation is generated that a control device is connected to the control unit, which for receiving the descriptor information on the relevant plurality of control status signals are used and thereupon a large number of descriptors = Status signals generated, and that the control device is connected to the status device and to the relevant sequence of status identification signals and the plurality of descriptor status signals generated the plurality of vector branch signals. 50. System according to claim 49 »characterized in that the descriptor information for describing properties of the operands has a first descriptor for describing a first operand and a second descriptor for describing a second operand, that the first operand and the second operand by the decimal unit for a transfer to the execution unit are aligned so that the execution unit allows the decimal-numerical operation to be carried out on the relevant row of microwords using the first operand and the second operand, that the descriptor information includes signals that are indicative of a scale factor (scale factor ), which indicates the position of the decimal point of the operand in question, that the descriptor information also includes signals which are indicative of a length of the operand in question, such that the number of decimal points in the operand is indicated that the descriptors nformation further comprises signals which are indicative of a character pointer position, such that the position of the most significant character of the operand is displayed within a word and whether the word concerned has an odd address or an even address in the cache memory, and that the descriptor information also Has signals which are indicative of the decimal type of the decimal symbols of the operands, such that the number of bits is indicated which are in the 030028/0881 _ ₂₅ _ 3000QA5 Decimal characters are included, which are taken from the cache memory, and that the location of a Sign and whether the operand in question is a floating point or fixed value operand is. 51. System according to claim 50, characterized in that the control device is connected to the control unit Contains memory means that respond to the relevant plurality of control state signals Stores descriptor signals indicative of the descriptor information that is associated with the storage means an adder means is connected which is responsive to the status flag signals and the descriptor signals hin the plurality of descriptor status signals generated that the decimal unit by the descriptor information and by a plurality of status indicator signals that are applied to a selected field of the Microword of the relevant row of microwords are generated hin, are caused to generate a plurality of vector branch signals by the vor the taking of the short operands from the cache memory by the decimal unit the number of words of the respective short operands are predetermined, which the decimal unit sends to the execution unit, furthermore, that the number of cycles is predetermined which occur between the short operands which are followed by the cache memory are requested by the microwords, with a first word of the short operands is received by the execution unit, and that the execution control unit further communicates with the decimal unit is connected and a branch in response to the plurality of vector branch signals in question to a subroutine of the relevant row of microwords for the purpose of processing the short ones Executes operands. 52. System according to claim 51, characterized in that the storage device is a first scale factor storage device for storing signals which are characteristic of the scale factor of the first operand, that further a second scale factor storage means for the storage of Signals is provided which are indicative of the scale factor of the second operand that the Storage means further includes a first length storage means for storing signals which A characteristic of the length of the first operand is that the memory device also has a second Has length memory device for storing signals which are indicative of the Length of the second operand, and that the memory means further comprises a first decimal type memory means for storing signals that are characteristic of the decimal type of the first operand, and second decimal type memory means for storing signals indicative of the are for the decimal type of the second operand. 53. System according to claim 52, characterized in that the adder device contains a transmit word count adder device which is connected to the first scale factor storage device, to the first length storage device and to the first decimal-type storage device for receiving the signals which are indicative for the first operand scale factor, for the first length and for the first decimal type, in such a way that a first descriptor status signal can be generated from the plurality of descriptor status signals, which is indicative of the number of words which the decimal unit to the execution unit is sent out for the purpose of processing a first short operand, and that the word counting 030028 / Ö881 Adder means further comprising the second scale factor storage means, with the second length storage means and with the second decimal type storage means is connected to receive the signals which are characteristic of the second operand scale factor, for the second Length and for the second decimal type, such that the first in question generates a descriptor status signal from the plurality of descriptor status signals which is indicative of the number of words that the decimal unit sends to the execution unit is sent out for the purpose of processing a second short operand. 54. System according to claim 51, characterized in that the storage means further comprises a first receive character pointer storage means for storing signals that are indicative of the Character pointer position of the most significant character of the first operand, and that the storage device further includes a second character pointer storage means for storing signals indicative of the are for the character pointer position of the most significant character of the second operand. 55. System according to claim 54, characterized in that the adding device also has a receive character = pointer adder means associated with the first received character pointer storage means and connected to the first decimal type memory means and responsive to the signals which are characteristic of the character pointer position of the character with the highest significance of the first operand, and for signals indicative of the decimal type of the first operand, receive digit pointer signals generated, which are indicative of the position of the highest significant digit of the 030028/0881 00004 the first operand, and that the received symbol = · pointer adder means with the second received symbol pointer memory means and to the second decimal type storage means and responsive to the signals through _g indicative of the highest for the character pointer position of the character value of the second operand , and in response to the signals indicative of the decimal type of the second operand, generate receive digit pointer signals indicative of the position of the most significant digit of the second operand. 56. System according to claim 55, characterized in that the adder device further comprises a send character pointer adder device contains that with the first scale factor storage means with the first length storage means and connected to the first decimal type storage means is such that the device in question is able to pick up signals which are characteristic of the first scale factor, first length and first decimal type, taken from the institution concerned Send digit pointer signals can be generated, which are indicative of the position of the highest digit Significance within the first operand word which is transmitted from the decimal unit to the execution unit, and that the send character pointer adder device with the second scale factor storage means, with the first length storage means and with the second Decimal-type memory device for receiving the length and scale factor for the second operand of the decimal type characterizing signal and is connected to generate the send digit pointer signals, which are characteristic of the position of the digit with the highest value within the second operand word, which 030028/0881 transmitted from the decimal unit to the execution unit x- / ird _o 57o system according to claim 56 »characterized in that the adder device contains a first send = digit = pointer = adder device _p which is connected to the receive character pointer = adder device and to the send = character pointer = adder device and which is connected to the receive digit pointer signals towards and on the send digit pointer = signals generated first signals which are indicative of the difference in the digit position of the digit of the highest significance of the first operand recorded by the decimal unit and the digit position of the digit of the highest significance of the first one sent by the decimal unit to the execution unit Operands, and that the send digit pointer adder device generates shift signals in response to the received digit pointer signals and to the transmit digit pointer signals, which are indicative of the difference in the digit position of the digit of the highest order of the second operand received by the decimal unit and the number po Position of the highest significant digit of the second operand sent from the decimal unit to the execution unit. 58. System according to claim 57, characterized in that the control device responds to short operands and word count vector means responsive to the first status signal of the plurality of Descriptor status signals generated a word count vector branch signal which is indicative is for a word transfer from the decimal unit to the execution unit in the event that the Word count vector branch signal occurs as binary zero during a 2-word transfer from the decimal unit to the execution unit 030028/0881 - 3o - 3OQOOAi in which case p is indicated that the relevant word = Counting vector branching signal occurs as binary signal 1 ο 59 ° Systea according to claim 58, characterized in that _p that the means responsive to the short operand Steuerein = direction of a 2-Zgrklusverzögerungs ° vector facility enthältj which is connected to the state machine and the sprichtj to selected status indicator signals at = which the respective signals are indicative of the character pointer position, and that the control device in question is able to generate a 2-cycle delay vector branching signal for the first operand and for the second operand, respectively, in response to the shift signals. 60. The system of claim 59, characterized in that the short operand responsive control device includes a 1 cycle delay vector device connected to the status device and responsive to selected status flag signals, the signals in question being indicative of the decimal type, and that the control device in question is further responsive to the shift signals and to signals indicative of the character pointer position, a 1-cycle delay vector branch signal being able to be generated for the first operand and for the second operand, respectively. 61. System according to claim 60, characterized in that the execution control unit on the relevant 1 cycle delay vector branch signal, to the 2 cycle vector branch signal and to the Word count vector branch signal selected sequences of microwords for processing the short operands generated. 030028/0881 - ³¹ - 3ÖÖÜIK5 Datenverarbeitungssystemj particular according to one of claims 1 Ms 61, characterized in that a memory means is provided for storing operands and instructions, each having a one decimal ^ numerical instruction defining operation code portion and a descriptor for describing properties of the respective operand having ₇ that the A decimal unit is connected to the storage device, which is used to store signals ₉ which are characteristic of the descriptor information and the operands, the relevant storage being carried out in response to the decimal-numeric commands that an execution device is connected to the decimal unit, which is used to receive the aligned Operands are used for the purpose of performing numerical operations which are determined by the decimal search command that the decimal unit is caused by the descriptor information to generate a plurality of vector branch signals n, by which the number of words in each of the short operands which the decimal unit will receive from the memory device is predetermined by the storage device prior to the inclusion of short operands in the decimal unit, that furthermore the number of words of the short operands is predetermined, which the decimal unit will send to the execution unit, that the number of cycles between the short operands in question is also predetermined, which are required by the memory device, that a first word of the short operands is received by the execution unit, and that an execution control unit with the decimal unit and generates a series of signals in response to the plurality of vector branch signals in question, the execution device in question further being connected to the execution control device and in response to the series in question 03002870881 Signals to perform an operation indicated by the decimal-numeric command. 63. System according to claim 62, characterized in that the decimal unit is a transmit word count adder device which generates pre-counting signals for the short operands in response to the descriptor signals, which are indicative of a first signal of the plurality of vector branch signals. 64. System according to claim 63, characterized in that the decimal unit is a 2-cycle delay vector device contains, which respond to the signals indicative of the command in question and in response to the descriptor signals, 2 cycle delay vector branch signals generated for the short operands in question. 65. The system of claim 64, characterized in that the decimal unit is a 1 cycle delay vector device containing a 1 cycle vector branch signal in response to the instruction signals and the descriptor signals generated for the short operands. 66. System according to claim 65, characterized in that the execution controller to the 1 cycle delay, in response to the 2 cycle delay and word count vector branch signals Series of signals for processing the short operands are generated. 67. Data processing system, in particular according to one of claims 1 to 66, characterized in that a Cache memory is provided which stores operands and instructions, each of which has a portion of opcode and furthermore has descriptor information for describing properties of the relevant operands, 030028/0881 -33- 300OU 4 that an execution control unit is provided for storing micro-words upon their occurrence operations indicated by the instructions are executable that with the cache memory and the execution control unit a control unit is connected that the cache memory and the control unit in response to the relevant micro-words one of the commands and the descriptor information indicating a decimal-numeric operation from the cache memory to the Control unit transmit that the control unit on the micro-words in question out the operation code part of the transmits an instruction to the execution control unit that the execution control unit selects a series of microwords on their occurrence in response to the relevant operation code part of the instruction towards the relevant decimal-numerical operation can be carried out that with the control unit and the Cache memory is connected to a decimal unit, which is used to store the descriptor information on the relevant row of microwords serves that the descriptor information cause the decimal unit, align the operands in the event that these operands are from the cache to the decimal unit be transmitted to the fact that an execution unit is connected to the decimal unit, which on the occurrence towards the series of microwords concerned receives the aligned operands from the decimal unit and perform the respective decimal arithmetic operations such that a resulting long operand is produced is used for the transfer to the decimal unit that the decimal unit on the relevant row of Micro words towards start = write signals and send data signals generated and that the execution control unit on the start · = write signals and the send data signals hin the relevant series of micro-words for the storage of the long operand in the cache memory generated. 68. System according to claim '67, characterized in that the decimal unit is a decimal unit control device which is connected to the execution control unit and to the control unit and which on a plurality of selected signals from the micro-words from and on the execution control unit the descriptor signals to the start write signals, the transmit data signals and register and switch control signals generated, and that an operand processing means is connected to the execution unit and the cache memory and on the occurrence of the relevant row of microwords receives the long operand from the execution unit and the long operand for the transfer upon occurrence of the register and switch control signals aligns to the cache and subjects it to a merge operation. 69. System according to claim 68, characterized in that the decimal unit control means a decoder means, a status means and a control means which is connected to the control unit, to the status device and to the decoder device and which is based on the plurality of control status signals, on the plurality of status indicator signals, on the Variety of command signals and descriptor signals generates the start write signals, the send data signals and the switch and register control signals, wherein the relevant control device further comprises the status device for generating the relevant plurality connected by status indicator signals. 70. System according to claim 69, characterized _s that said control means includes a memory device which is connected to the control unit and which allows to store the plurality of control signals, the state Deskriptorsignale, and that with the Speichereinrich- 030028/0881 an adder device is connected which on the descriptor signals, the shift signals and the status flag signals to the start write signals, the transmit data signals and the switches and Register control signals generated, 71. System according to claim 70, characterized in that the adder means a shift counter which is connected to the memory device and which respond to the relevant descriptor signals the shift signals generated which are indicative of the number of decimal digits by which the Operand is moved in the operand processor. 72. System according to claim 71, characterized in that the adder device is a receive word count register device which is connected to the decoder and the status device and which on the command signals and the status indicator signals generate and store signals which are indicative of the number of significant Words that the decimal unit will accept from the execution unit. 73. The system of claim 72, characterized ₉ is that the adder further comprises a transmit word count = adder contains "associated with the memory device and generates the Deskriptorsignale out signals, and stores that characterize = drawing are for the number of words, which will send the relevant decimal unit to the cache memory. 74. System according to claim 73 »characterized in that the adder also has a comparator input direction, which is connected to the receiving - = - word counting register means and to the sending word counting register means and which respond to a first plurality of signals which are indicative of the number of significant words, which the decimal unit from the execution unit will record here? and a second plurality of signals towards _s which are characteristic of di © number of words, the decimal is transmitted to the cache memory, and generates the shift signals out register and switch control signals, and in that the comparison means also connected to the state machine and in response to the relevant status signals, to the shift signals and to the first and second signals, the start write signals and the transmit data signal are generated in the event that the first signal and the second signal are in a specific relationship to one another. 75. System according to claim 74, characterized in that the operand processing device includes a receiving device which communicates with the execution unit is connected and which is used to receive signals which are characteristic of the long operand words, the relevant recording being made in response to a first series of micro-words, the execution control unit responding to the relevant transmit data signals generates the first series of micro-words that a mixing device is connected to the receiving device the long operand words concerned in response to the register and switch control signals aligns for transfer to the cache on a second series of microwords and mixes, and that the execution control unit on the start write signal hirj the relevant second row generated by microwords. 030028/0881 -37- 3QÜÜUA5 76o system according to claim 75, characterized in that the comparator means to the first and second A large number of signals are generated for comparison signals which are characteristic of the relationship between the Binary numbers represented by the first and second plurality the signals are marked o 77o Systea na © h claim 7ö _s characterized in that oils lEapfangs ^ Uortzihl ^ Eoglstepeiiiirichtung © nthältp the on the status = measure the is the receive word count = gssij © lßhepi © 2i Signal® each in value ~ x-7®m & öqs relevant Opsrandenwort taken from the Desimalsinlieit is ₀ That the transmit word count register means includes: 78 _O system according to claim 77, characterized in that a discounting arrangement, which then reduces the Deskriptorsignale, the status indicator signals and the comparator signals towards the transmission · = Wortzählregistereinrichtung respectively in value, v / hen the operand word in question to transferred to the cache memory is ₀ 79. Data processing system, in particular according to one of claims 1 to 78, characterized in that a Storage device for storing operands and instructions is provided, each of which has an operation code part and further contains descriptor information which is used to describe properties of the operands serves that the commands contain an operation code part, which is a decimal = · numeric to be executed Operation denotes that a decimal unit with the storage means for receiving the signals is connected, which are indicative of the descriptor information, and which are also used for the transmission of operands between the memory device and the decimal unit in response to signals which are indicative of 300004 the relevant decimal-numeric commands with the decimal unit is connected to an execution device ₉ which is used to receive siaes first operands and a second operand of the operands di @ at _p which are used to execute sinsj? Operation äiem®n ₉ wele & e dureis, the betFoffQsidoB fi'sziESl ^ MSEiQjrlseteB Sefoftl is established _Ώ and äi © long Qpo ^ aMoauiPtoi 'fife äio to öor Boglmloinfeeit s ωϊ Sigssal © Ma θσ ³ x = ll1 ©! AEO IxorniSQieMead siM fis ³ άοη hQtrQ £ S @ nuGn Bynorlsahsis Bsfohlj, öaß öio Boslmaloiafeelt to doa botPQffosidloa Bofsfel Ma 3tar ^{j <fe} "=" Seli3? eibsigaale mid igssale generates _s that © SIq ü-usfülwimgesia = the side data signal © means that the long operand words are sent out to the decimal unit and that the memory device receives the long operand words from the decimal unit in response to the start write signals. 80. System according to claim 79, characterized in that the decimal unit is a decimal unit control device which is connected to the memory device and which responds to the command signals and descriptor signals the start write signals, the send data signals, generates the status signals and the register and switch control signals, and that an operand processing device is provided, which is connected to the execution device and the storage device and which receives the long operand from the execution unit in response to the instruction signals and on the register and switch control signals the long operand for di? Transfer to the storage device aligns and subjects it to a mixed operation. 81. System according to claim 80, characterized in that the control device is a storage device which is connected to the storage device 030028/08 * 1 = 39- un <S, the signals on the command towards abspeichertρ the Deskriptorsignale and in that adder means connected to said storage means for generating the Deskriptorsignale down shift signals _s wherein the Deskriptorsignale xirerdenj further used depending on the status signals and the shift · DC signals to the Generate start write signals, the send data signals and the switch = and register control signals, 82ο System according to Claim 81 , characterized in that the operand processing device contains a recording device which is connected to the execution device for recording the long operand words in response to the transmitted data signals, that a mixing device is connected to the recording device, which aligns and mixes the long operand words in response to the register and switch = control signals ₉ and that a transmission device is connected to the memory device and transmits the mixed long operand words to the memory device in response to the start write signals. 83 »Data processing system according to one of claims 1 to 82, characterized in that the decimal unit with the memory location ^ control device and the Cache memory for storing the descriptor information and for receiving the operands on the relevant Series of microwords is connected that the The decimal unit also aligns the operands to the descriptor information signals that the execution unit uses the decimal unit to receive the aligned Operands is connected, this recording being made in response to the row of micro words in question and decimal arithmetic operations are performed that the decimal unit further by the descriptor information »40-30Ü0Ü45 and through a variety of status indicator signals, those on a selected field of the microword of the relevant Series of microwords generated towards ^ is caused to have a multitude of vector branching = Generate signals that indicate the execution control unit and the properties of the operands, and that the execution control unit is dependent on the relevant plurality of vector dispersion signals a branch to a subroutine of the relevant series of microwords for processing the Executes operands. 84. System according to claim 83, characterized in that the decimal unit contains a decoder, those for receiving selected microword signals and for generating decimal unit command signals serves that a memory device for storing the descriptor information and for generating descriptor signals is provided, which are characteristic of the properties of the operands that are used with the decoder and the descriptor information storage means a status flag storage means is connected, the status identifier signals in response to the command signals and the descriptor signals generates that with the decoder and the status label storage means a vector branch control means connected to the relevant command signals and the status indicator signals generated hin vector branch control signals, and that with the descriptor means and the status identifier storage device is connected to a switch device for receiving the Descriptor signals and the status flag signals serves, with the vector branch control signals on the switch device for selecting certain descriptor signals and the status identifier signals are used in such a way that the vector branching 030028/0881 30Ü0Ü45 signals for delivery to the execution control unit are generated _o 85ο Syotoo aaoh claim 84 _p thereby goksraiseicbBetp that saforEiatioas storage facility sin® usd decimal t ^^ Speiefaereiarlehtung contains j, di © is able to generate signals _p which are characteristic for the preceding sign, the number of bits in the respective decimal place and the operand type _o 8βο System according to claim 85p characterized ₉ that the switch device contains a first position switch device for generating the vector branch signals ρ which are characteristic of a type length = vectorj that a second position switch device is provided for generating the vector branch signals ₉ which are characteristic for a descriptor 1 vector j that a third position switch device is provided for generating the vector branch signals j which are characteristic of a descriptor 2 = vector _s that a fourth position switch device is provided for generating the vector branch signals which are characteristic of a storage vector, and that a fifth position switch device is provided, which is used to generate the vector branch signals5 which are characteristic of a long input vector " System according to Claim 86j, characterized in that the first position switch device generates a first series of the vector _{branching signals of a short operand p} which is a first specific one, depending on the vector branching control signalsj which are characteristic of the type-length vector operation ₉ Number of bits in a character of the operand concerned, that a second series of the vector branch signals concerned is generated _s characterizing -42 = 30Ü0Ü45 are for the short operand having a second predetermined Änsahl of bits in the character of the relevant operand ^ that a dri tt © series of Vektorverzueigungsslgnale Uird generates the _D Isenssoiad SW? (Soja Imwzon QpopG & clOK oit oiaoa ! © tPS-QiehQ ^ w & u that ei & o viejfUe ÜQlho the yector branching signals generate virö, which are indicative of a long operand. 88. System according to claim 87, characterized in that the second position switch device as a function of the vector control signals which are characteristic of the descriptor 1 vector operations, the first Series of vector branch signals generated characterizing the are for an execution descriptor 2 operation that also includes the second series of vector branch signals which are indicative of a descriptor 1 floating point operation, that further the third row of vector branch signals is generated which are indicative of a descriptor 1 over-hole operation with leading sign, and that generates the fourth row of vector branch signals which are indicative of a descriptor 1 operation with a punched subsequent prefix. 89. System according to claim 88, characterized in that the third position switch device as a function the vector branch control signals indicative of the descriptor bit vector operation, generates the first series of vector branch signals indicative of the descriptor 2 operand, which is processed neither as a floating point operation nor as an operation with an overlaid sign is that the second series of vector branch signals is also generated indicative of the are in favor of the descriptor 2 operand being a floating 43-3GÜQ045 aaoperatioB is processed; that the relevant third row of vector branch signals generated will j. which are indicative of the fact that the descript = tor-2-Qperand as fixed-value operand with one over = punched leading sign is processed, and that the fourth row of vector branch signals generates tfirdp which are characteristic of the descriptor = 2-Qperandj, the fixed-value operand with an overlaid x-jirdo processes the following sign 90. System according to claim 89? characterized in that the fourth position switch device as a function of = the vector branch control signals characteristic of the memory vector operation, generates the first series of vector skew signals, which are characteristic for a check for zero or for an overflow operation that the second row the branch signals are generated which are indicative of the checking of the floating point operand Zero or an overflow "that the third row of the Vector branch signals are generated, which are indicative of the fact that the operand with over-holed leading sign is checked for zero or overflow, and that the fourth row of vector branch signals which are indicative that the operand has a perforated subsequent sign is checked for zero or an overflow « 91. System according to claim 90 _p, characterized in that the fifth position switch device in dependence = speed on the vector branching control signals which are characteristic of a long input vector operation, the first row of vector branching signals generated which is characteristic of operands that are specified with a set length that is less than or equal to a third specific number, 30Ü0Ü45 There is no over-holed sign that the second row of vector branch signals which are characteristic of operands that are defined with the set length, which is shorter than or equal to the relevant third specific number, where there is no over-holed sign is that the third row of vector branch signals is also generated which are indicative of Operands ^ which are fixed with the set length of descriptor or descriptor 2, where the length is greater than the relevant third specific number, and that also the fourth row of vector branch signals which are indicative of an execution descriptor 1 and a descriptor 2 vector operation. 92. Data processing system, in particular according to one of claims 1 to 91, characterized in that a Storage device is provided for storing commands which include descriptor information, that an execution control device for storing micro-words is provided that with the memory device and the execution control device is connected to a decimal unit which is used to receive the Descriptor information and a first series of micro words and the relevant descriptor information and selected micro-words of the relevant Series of microwords generated vector branch signals, and that the execution control means with connected to the decimal unit and dependent branches from the vector branch signals to a second series of microwords. 93. Data processing system, in particular according to one of claims 1 to 92, characterized in that the Cache memory is used to store operand words and instructions so that each operand word is encoded in such a way that that it denotes a number of types of information that 030028 / QS81 -45- 3O0Q0A5 Decimal digits, sign characters, exponents = characters and JUicht operand information, each instruction containing an operation code part which designates a decimal-numerical operation to be carried out, and also descriptor information for describing the properties of the operand words concerned, that an execution control unit for storing microxi words is provided, upon the occurrence of which Mn the operations designated by the operation code part of the instructions in question are carried out, that a control unit is connected to the cache memory and the execution control unit, that a decimal unit is connected to the control unit and the cache memory, and descriptor information from the control unit and is able to store the operands = words from the cache memory that the descriptor information causes the decimal unit to select the decimal digits of the operand canceler in the event that the relevant operander / ö rter from the cache memory to the decimal unit to = carry v; ground _p that the execution unit connected to the decimal unit serves to receive the decimal digits depending on the relevant series of microwords and executes decimal-numeric commands in such a way that a calculation result descriptive decimal digits are generated and transferred to the decimal unit in such a way that resultant operand words are formed for transfer to the cache memory, and that the decimal unit includes shifting means for generating the register and switch control signals by means of which the decimal digits of the operand words received from the cache memory selectable and the resulting operand words can be generated, which are accepted by the execution unit in one cycle of the operand words in question and which are processed by the decimal unit » 94. System according to. Claim 93, characterized in that the decimal unit contains a decimal unit control device which is connected to the control unit and allows the signals indicative of the control status signals for the descriptor information to be stored in the decimal unit Execution unit is connected and which generates the register and switch control signals in response to a plurality of the selected signals from the microwords and on the descriptor information signals, that the operand processing device is connected to the cache memory and the execution unit and in response to the relevant row of microwords Receives operand words from the cache memory and, depending on the register and switch control signals, decimal digits from the operand words for the purpose of transferring the decimal digits of the operand words to the execution unit for the purpose of verifying processing freed, and that the operand processing device is also able to receive the decimal digits indicating a computation result from the execution unit in response to the relevant row of microwords and, depending on the register and switch control signals, the decimal digits designating a computation result, the number of information types allowed to append such that the resulting operand words are formed for transfer to the cache memory. 95. System according to claim 94, characterized in that with the control unit, the status device and control device connected to the decoding device to the plurality of control state signals, to the plurality the status identifier signals, the plurality of command signals and the descriptor information signals responds and the register and switch -47- 30000Λ5 Generates control signals, and that the control device is further connected to the status device for generating the Large number of status indicator signals is connected " 96, system according to claim 95 »■ characterized in that the control device has a storage device connected to the control unit and an adder device which is connected to the storage device and which respond to the status indicator signals and the descriptor information signals generate pointer signals, and that the shifting means with the adding means is connected and in dependence on the pointer signals, the descriptor information signals and allows the status flag signals to generate the register and switch control signals. 97. System according to claim 96, characterized in that the operand processing means one with the Cache memory associated loader contains which depending on the series of microwords concerned Receiving the operand words from the cache memory allows a first switch device is connected to the charging device and in dependence on the register and switch control signals the decimal digits of those picked up from the cache Operand words for transmission to the execution unit for the purpose of processing replaces that the loading device is also connected to the execution unit and to the relevant Row of microwords to the decimal digits indicating a calculation result from the execution unit to include, and that a double switch = device is connected to the charging device and the register and switch ~ control signals relevant number of information types the decimal digits received by the execution unit appends in such a way that the resulting operand words are generated 98. System according to claim 96 or 97 »characterized that the adder means a left pointer load adder means which is connected to the memory device and which responds to the status flag signals and the first descriptor information signals towards left pointer load adder signals are generated which are indicative of the number of zeros on the left side of the digit highest value of the one recorded from the cache memory Operand word, and that the adder device also has a right-pointer load adder device which is connected to the memory device and which respond to the status flag signals and the second descriptor information signals Right-hand pointer load signals are generated which are indicative of the number of zeros on the right-hand side the least significant digit of the word picked up from the cache memory. 99. System according to claim 98, characterized in that the sliding device is a left-sliding loading device contains that with the left pointer load adder means is connected and the signals to the left pointer load out first register and switch control signals generated, and that the shifter further includes a right shift loader, which is connected to the right-hand pointer load adder and which is connected to the right-hand pointer load signals generated second register and switch control signals. 100. System according to claim 99 »characterized in that the first switching device connected to the charging device for receiving a first operand word from the Cache memory is connected, a first shedding device which, in response to the first register and switch control signals, · the character positions on the left-hand side 03UQ2B / Q881 sets the highest value digit of the first operand word to the decimal value zero in such a way that the sign and the non-opderand information is detached from the first operand word, and in that the first switch means further includes a second release means associated with the loading means for receiving a second operand word with the decimal number having the lowest value from the cache memory and which, in response to the second register and switch control signals, the Characters on the right side of the lowest significant digit of the second operand word to the decimal value 0 allows such that the sign and exponent signs and the Non-operand information is detached from the second operand word. 101. The system of claim 96 _Ρ characterized ₉ that the adder a sign memory pointer adder contains, which is connected to the memory means and generates the status indicator signals and the third descriptor information signals towards sign Speicherzeigorsignale which are indicative of the location of the sign characters in the resulting operand words, and that the adder means further includes an exponent = memory pointer adder device which is connected to the memory device and which, in response to the status flag signals and the fourth descriptor information signals, generates exponent memory pointer signals which are indicative of the position the exponent sign in the resulting words » 102. System according to Claim 101, characterized in that the shifter, a sign memory shifter and an exponent memory shifter contains that the relevant sliding 030028/0 ^ 1 -50- 306 0045 devices with the sign memory pointer adder device or the exponent memory adder device are connected and that the shifters concerned are based on the sign memory pointer signals and generate third and fourth register and switch control signals, respectively, in response to the exponent memory pointer signals. 103. System according to claim 102, characterized in that that the adder means further includes rewrite memory adder means which is connected to the storage device and which is available on the Status flag signals and the fourth descriptor information signals to rewrite memory pointer signals generated, which are indicative of the location of the non-operand information in the resulting Operand words. 104. The system of claim 103, characterized in that the shifter further comprises a rewrite memory shifter which is connected to the rewrite memory adder means and which is responsive to the rewrite memory pointer signals generated fourth register and switch control signals. 105. System according to claim 104, characterized in that the second switch device with the loading device for receiving the resulting operand words is connected by the execution unit and contains a trailer device that accesses the fourth register and switch control signals to the non-operand information to the resulting words allowed to attach. 106. System according to claim 105, characterized in that the shifting device is one with the adding device Ü30028 / 0881 - 51 - 30QO (KS contains connected input device, which is used to receive a plurality of input signals, which binary signals .1 ₈ binary signals O, the descriptor information and the status identifier signals include that the shifting device connected to the adder device and the input direction on the descriptor information signals and the status identifier signals selects a specific number of adjacent signals of the plurality of input signals in question, and that an output device is provided which is connected to the shifting device and the input device and which generates the register and switch control signals in response to the specific number of adjacent signals in question. 107. Data processing system, in particular according to one of claims 1 to 106, characterized in that the Storage device for storing operand words which are encoded so that they are a Identify a number of types of information, including decimal digits, plus and minus signs and exponents Non-operand information, as well as instructions, including descriptor information, with the relevant Instructions contain a part of an operation code which designates a decimal-numeric operation to be carried out, that the decimal unit is connected to the memory device and operand words as well as the Descriptor information on the decimal-numeric Instruction accepts that the decimal unit is a load shifter contains the load register · = and switch control signals for selecting the decimal digits of the operand words generates that the decimal unit is connected to an execution device which serves to accommodate the decimal digits of the operand words and which executes the decimal = numeric command, in such a way that a calculation result indicative of decimal Q3ÖÖ2B / QSS1 - 3000G45 digits generated and transferred to the decimal unit and that the decimal unit contains a memory shift device which is used to generate of storage register and switch control signals * which are used to form operand words which include the decimal digits that designate the calculation result. 108. System according to claim 107, characterized in that the decimal unit one with the memory device associated decimal unit control means, which are indicative of the opcode portion of the instructions Signals to the signals characterizing the descriptor information in the decimal unit allows the control device to store a load shift device for generating the load register and switch control signals that have a Operand processing device is connected, which in response to the operation code signals, the operand words receiving from the memory means allows the operand processing means to send a first Includes switch means that respond to the first register and switch control signals to select the Address decimal digits from the operand words in such a way that these digits go to the executing facility for the purpose of processing that the control device is a memory shift device for generating the memory register and control signals contains that the operand processing means in response to the operation code signals Decimal opcode signals to accommodate the decimal digits which designate the calculation result and that the operand processing means second switch means responsive to the memory register and control signals the decimal digits that indicate the calculation result Ü30Q28 / QS31 - 53 - 3000 01-- Append number of information types so that the resulting operand words are generated. 109. System according to claim 108, characterized in that the loading slide device is a loading input device with a plurality of adjacent binary load input signals 1 and a plurality of binary Load input in O contains that the load shifter is connected to the load input device and to the descriptor information signals and the status indicator signals towards a certain number of the neighboring signals from the plurality of Charging input signals are allowed to select, and that a loader output device is connected to the loader slide device and on the relevant a certain number of neighboring signals that generated load register and switch = control signals 110. System _s characterized according to claim 109, that the shift storage device _s includes a memory ~ input device having a plurality of adjacent memory input signals 1 having a plurality of adjacent binary memory input signals 0 and with signals which a plurality of descriptor information signals and Status identification signals have that the memory shift device is connected to the memory input device and, in response to the descriptor information signals and the status identification signals, allows a certain number of the adjacent signals to be selected from the plurality of memory input signals, and that a memory output device is connected to the memory shift device which is responsive to the concerning a certain number of neighboring signals to generate the memory, register and switch = control signals. 030028 / OeOil