GB2114785A

GB2114785A - A decimal operand processing unit

Info

Publication number: GB2114785A
Application number: GB08232426A
Authority: GB
Inventors: Jerry L Kindell; Richard T Flynn
Original assignee: Honeywell Information Systems Italia SpA; Honeywell Information Systems Inc
Current assignee: Bull HN Information Systems Italia SpA; Bull HN Information Systems Inc
Priority date: 1979-01-02
Filing date: 1982-11-12
Publication date: 1983-08-24
Also published as: FR2445985A1; DE3000006A1; DE3000006C2; GB2039104B; GB2114785B; FR2445985B1; GB2039104A

Abstract

In a microprogrammed data section processing system, the throughput of the system is increased by decimal operand processing apparatus which counts the number of effective digits in an operand which is the result of a decimal numeric instruction being processed by the system. The apparatus receives operand words the operand's least significant word first, in response to a predetermined microword. The decimal operand processing apparatus includes a first register which stores a count of one less than the number of words received; an adder which increments the output of the first register if the word received has a decimal zero in the high horder position of the word; and a second register which stores the output of the adder in a word count portion and the number of leading zeros in a digit count portion of the second register. The second register is loaded on the same cycle the word is processed providing the word does not contain all decimal zeros. <IMAGE>

Description

1 GB 2 114 785 A 1

SPECIFICATION A decimal operand processing unit

The invention generally relates to a microprogrammed data processing systems and in particular to decimal operand processing apparatus which generates and stores an effective digit count of a resultant operand during the processing of a decimal numeric instruction.

Data processing systems process data stored in memory in the form of an operand consisting of decimal digits. The length of the field in memory assigned to storing a particular operand contains as many memory locations as is required to store the largest possible number of decimal digits for that operand.

In many cases the operand stored in that field would require fewer decimal digits than does the 10 maximum sized operand. When the operand is the result of the system processing a decimal numeric instruction it is necessary to determine the number of effective digits in the resultant operand.

The Honeywell 6000 uses leading zero count logic at all times and when the effective digit count is needed for storing the resulting operand, the leading zero count is subtracted from 64 decimal digits which is the maximum operand size.

The approach takes a number of machine cycles and requires a relatively large amount of hardware. This reduces the throughput of the system at an increased cost.

It is a primary object of the present invention to provide means for achieving a lower cost microprogrammed data processing system by counting the number of effective digits as the words of the resultant operand are received thereby improving the throughput of the system.

Accordingly the invention provides a decimal unit for modifying multipleworded decimal numeric resultant operands that were processed by a data processor execution unit for storage in a memory, comprising:

means for receiving signals indicative of each word of said resultant operands least significant word first, each word being received in response to a microword; detecting means coupled to said receiving means and responsive to said word signals for generating signals indicative of decimal digit positions of said least significant word and subsequent words of said resultant operand; decoding means coupled to said detecting means, and responsive to said decimal digit signals for generating a first signal in a first state indicative of a decimal digit in a first position of said word having 30 a value greater than decimal zero, and generating binary signals indicative of the position of the most significant decimal digit of said word if said decimal digit in said first position has a value of decimal zero indicated by said first signal being in a second state; word counter means responsive to a control signal for generating signals indicative of a count of one less than the number of words of said resultant operand received by said receiving means; adder means coupled to said word counter means and to said decoding means and responsive to said count signals and to said first signal for generating signals indicative of the number of effective words received by said receiving means; an effective digit count register having at least a first and a second portion, said first portion being operatively coupled to said adder means for storing signals indicative of the number of effective word ' S, 40 and said second portion being operatively coupled to said decoding means for storing said binary signals, said register storing the number of effective digits received by said unit on a cycle said word was transferred to said receiving means.

A microprogrammed data processing system including an embodiment of the invention to be described in detail later comprises a cache memory for storing operands and instructions including 45 descriptors which define the characteristics of the operand. The operands are transferred to the decimal unit when the system performs decimal numeric instructions.

The decimal unit strips away nondecimal digit information and transfers the operands to an execution unit for arithmetic processing. The resultant operand is transferred to the decimal unit where the required sign, exponent, rewrite characters and zone bits are appended and the operand stored 50 back into cache.

In worst cases the number of significant decimal characters in the operand is less than the length of the field in the cache address location into which the resultant operand is written. Since the operand is stored in a cache a word at a time, the throughput of the system is improved if the number of significant decimal characters in the resultant operand is known. This will permit the system to use 55 only as many firmware cycles as are required to transfer the resultant operand to cache.

The resultant operand is received by the decimal unit from the execution unit, low order word first. An RWPC register 730-84 is incremented for each word received after the first word. The RWPC register stores one less than the number of words received by the decimal unit from the execution unit.

An AEDC adder 730-86 adds the output of the RWPC register to a signal which is at logical 60 ONE when the word received by the decimal unit contains a decimal zero in the high order digit position of the word. The AEDC adder output is stored in a word count portion of an RM register 730-96. However the RUC1 register is not loaded on a decimal unit cycle in which the word processed contains all decimal zeros. If the word contains a number of decimal zeros in the higher 2 GB 2 114 785 A 2 order positions of the word followed by a digit which is not a decimal zero, then the binary count of the number of high order digits is stored in a word count portion of the IRLZC l register. When the entire resultant operand is processed by the decimal unit, the RUC l register contains the count of the number of effective decimal digits in the resultant operand. Note that the RUC l register was loaded in the same cycle as a word containing a digit not decimal zero is processed ' by the decimal unit.

Other features of the apparatus described above form the subject matter of application 7943411 from which this application has been divided.

The above described system is now described in further detail with reference to the accompanying drawings, wherein:

Figure 1 is an overall block diagram of the host processor. The cache unit and system integration 10 unit are shown connected to the host processor.

Figure 2 is a block diagram of the execution unit and a portion of the character unit of the host processor.

Figure 3 is a detailed block diagram of the decimal unit.

Figure 4 is an overall block diagram of the decimal unit.

Figure 5 shows the instruction and descriptor formats for two decimal numeric instructions.

Figure 6 is a logic diagram of the leading zero count circuits.

Figure 7 is a logic diagram of the effective digit circuits.

Figure 8 is a diagram of the vector branch logic.

General description of processor 700-Figure 1

Referring to Figure 1, it is seen that a host processor 700 includes an execution control unit 701, a control unit 704, an execution unit 714, a character unit 720, an auxiliary arithmetic and control unit (AACU) 722, a multiply-divide unit 728, and a decimal unit 730 which are interconnected as shown.

Additionally, the control unit 704 has a number of interconnections to the cache 750 as shown.

The execution control unit 701 includes an execution control store address preparation and branch unit 701 -1, and an execution control store 701-2. The store 701-2 and unit 701 -1 are interconnected via buses 701-3 and 701-6 as shown.

The control unit 704 includes a control logic unit 704-1, a control store 704-2, an address preparation unit 704-3, data and address output circuit 704-4, and XAQ register section 704-5 which interconnect as shown.

The control unit 704 provides the necessary control for performing address preparation operations, instruction fetch l ng/executi on operations and the sequential control for various cycles of operation and/or machine states. The control is generated by logic circuits of block 704-1 and by the execution control unit 701 for the various portions of the control unit 704.

The XAG register section 704-5 includes a number of program visible registers such as index 35 registers, an accumulator register, and quotient register. Other program visible registers such as the instruction counter and address registers are included within the address preparation unit 704-3.

As seen from Figure 1, the section 704-5 receives signals from unit 704-3 representative of the contents of the instruction counter via lines RIC 00-17. Also, lines Z1RESA 00-35 apply output signals from the execution unit 714 corresponding to the results of operations performed upon various 40 operands. The section 704-5 also receives an output signal from the auxiliary arithmetic and control unit via lines MAU0-8 The section 704-5 provides signals prep rese ntaitive of the contents of one of the registers included within the section as an input to the address preparation unit 704-3 via the lines ZXO-20 and ZM 24-35. The address preparation unit 704-3 forwards the information through a switch to 45 the execution unit 714 via the lines ZDO 0-35. Similarly, the contents of certain ones of the registers contained within section 704-5 can be transferred to the execution unit 714 via the lines ZEB 00 35. Lastly, the contents of selected ones of these registers can be transferred from section 704-5 to the multiply/divide unit 728 via the lines ZAQ 00-35.

The address preparation unit 704-3 generates addresses from the contents of various registers 50 contained therein and applies the resultant logical, effective and/or absolute addresses for distribution to other units along the lines ASFA 00-35. The address preparation unit 704-3 receives the results of operations performed on a pair of operands by the execution unit 714 via the lines Z1RESB 00-35.

The unit 704-3 receives signals representative of the contents of a pair of base pointer registers from the control logic unit 701 via the lines RBASA and RBASA0-11. Outputs from the multiply/divide unit 55 728 are applied to the address preparation unit 704-3. Lastly, the contents of a secondary instruction register (RSIR) are applied as input to the unit 704-3 via the lines RSIR 00-35.

The data and address output circuits 704-4 generate the cache memory address signals which it applies to the cache unit 750 via the lines RADO/ZADO 00-35. These address signals correspond to the signals applied to one of the sets of input lines M1 00-35, ASFA 00- 35 and Z1RESB 00-35 60 selected by switches included within the circuits of block 704-4. Also, a word address signals are applied via the lines ASFA 32-33.

The control logic unit 704-1 provides data paths which have an interface with various units included within the cache unit 705. The lines ZIB 00-35 provide an interface with an instruction 3 GB 2 114 785 A 3 buffer included within the cache 750. The lines W1 00-35 are used to transfer data signals from the cache 750 to the control logic unit 704-1.

As seen from Figure 1, the control logic unit 704-1 provides a number of groups of output signals. These output signals include the contents of certain registers, as, for example, a basic instruction register (RBIR) whose contents are applied as an input to control store 704-2 via the lines 5 RBIR 18-27. The control logic unit 704-1 receives certain control signals read out from control store 704-2 via the lines CCSIDO 13-3 1.

The control logic unit 704-1 also includes a secondary instruction register (RSIR) which is loaded in parallel with the basic instruction register at the start of processing an instruction. The contents of the secondary instruction register RSIR 00-35, as previously mentioned, are applied as 10 inputs to the address preparation unit 704-3. Additionally, a portion of the contents of the secondary instruction register are applied as inputs to the auxiliary arithmetic control unit 722 via the lines RSIR 1-9 and 24-35, and to the decimal unit 730 via the lines RSIR 21-35.

The control store 704-2 as explained herein provides for an initial decoding of program instruction op-codes and therefore is arranged to include a number of storage locations (1024), one for 15 each possible instruction op-code.

As mentioned, signals applied to lines RBIR 18-27 are applied as inputs to control store 704 2. These signals select one of the possible 1024 storage locations. The contents of the selected storage location are applied to the lines CCSIDO 13-31 and to CCSIDO 00- 12 as shown in Figure 1.

The signals supplied to lines CCSDO 00-12 correspond to address signals which are used to address 20 the execution control unit 701 as explained herein.

The execution unit 714 provides for instruction execution wherein unit 714 performs arithmetic and/or shift operations upon operands selected from the various inputs. The results of such operations are applied to selected outputs. The execution unit 714 receives data from a data input bus which corresponds to lines RDI 00-35 which have as their source the control logic unit 704-1. The contents of the accumulator and quotient registers included within the section 704-5 are applied to the execution unit 714 via the lines ZEB 00-35 as mentioned previously. The signals applied to the input bus lines WO 00-35 from the address preparation unit 704-3 are applied via switches included within the execution unit 714 as output signals to the lines ZRESA 00-35 and ZRESB 00 35, as shown in Figure 1. Additionally, execution unit 714 receives a set of scratch pad address signals 30 from the auxiliary arithmetic and control unit 722 applied via the lines ZRESPA 00-06. Additionally, the unit 722 also provides shift information to the unit 714 via the lines ZIRSC 00-35.

The character unit 720 is used to execute character type instructions which require such operations as translation and editing of data fields. As explained herein, these types of instructions are referred to as extended instruction set (EIS) instructions. Such instructions which the character unit 35 720 executes include the move, scan, compare type instructions. Signals representative of operands are applied via lines ZRESA 00-35. Information as to the type of character position within a word and the number of bits is applied to the character unit 720 via the input lines ZOB 00-07.

Information representative of the results of certain data operations is applied to the unit 722 via the lines ZOC 00-08. Such information includes exponent data and data in hexadecimal form. The 40 character unit 720 applies output operand data and control information to the unit 722, the unit 730 and the unit 728 via the lines RCHU 00-35.

The auxiliary arithmetic and control unit 722 performs arithmetic operations upon control information such as exponents used in floating point operations, calculates operand lengths and pointers and generates count information. The results of these operations are applied to execution unit 45 714 via the lines ZRSPA 00-06 and lines ZRSC 00-05 as mentioned previously. Information signals corresponding to characters such as 9-bit characters, 4-bit characters, decimal data converted from input hexadecimal data, quotient information and sign information are applied to section 704-5 via the lines RAAU 00-08.

As seen from Figure 1, the unit 722 receives a number of inputs. Character pointer information is 50 applied via the lines ASFA 33-36. EIS numeric scale factor information are applied to the unit 722 via the lines RSIR 24-35. Other signals relating to fetching of specific instructions are applied via the lines RSIR 0 1 -09. Exponent signals for floating point data are applied to the unit 722 via the lines ZOC 00-08 while floating point exponent data signals from unit 704-1 are applied via the lines RDI 00-08. Shift count information signals for certain instructions (e.g. binary shift instructions) are 55 applied to the unit via the lines RDI 11-17. As concerns the input signals applied to the lines RCHU 00-35, lines 24-35 apply signals corresponding to the length of EIS instruction fields while 18-23 apply address modification signals to the unit 722.

The multiply/divide unit 728 provides for high-speed execution of multiply and divide instructions. This unit may be considered conventional in design and may take the form of the multiply 60 unit described in U.S. Patent 4,041,292 which is assigned to the same assignee as named herein. The unit 728 as seen from Figure 1 receives multiplier dividend and divisor input signals via the lines RCHU 00-35. The multiplicand input signal from register section 704-5 are applied via the lines ZAQ 0035. The results of the calculations performed by the unit 728 are applied as output signals to the lines MID 00-35.

00 -1 4 GB 2 114 785 A 4 The decimal unit 730 is operative under firmware control during the processing of decimal numeric instructions. The instruction format and its related descriptor words are described in greater detail with reference to Figure 5. The instruction word and the descriptor word information received by the decimal unit 730 via lines RSIR 21-35 and ASFA 33-36. They condition the decimal unit 730 to receive the operand described by the descriptor word from cache 750 via line 2-DI 0-35. The decimal unit 730 strips the sign character and exponent characters from the operand word, packs the data into up to eight 4-bit characters per word, stores the data into 32-bit words, aligns and transfers the data words to the execution unit 714 via lines RDOD 00-35, ZMD 00-35 and WO 00-35. Data words stored in cache include up to four 9-bit characters of eight 4-bit characters in a 36 bit word. The 9-bit character includes five zone bits and four data bits. The zone bits are stripped from the 9-bit character 10 and the remaining data bits are packed into a 32-bit register which may contain up to two cache data words made up of 9-bit characters or one cache data word made up of 4-bit characters. The packed data words of the operands are assembled in the execution unit 714 and processed in accordance with the decimal numeric instruction. The operand representing the desired result of the numeric instruction is transferred to the decimal unit 730 via lines Z1RESA 00-35 to the character unit 720 and then to the 15 decimal unit 730 via lines RCHU 4-35. There, the operand is processed in accordance with the coded information in a descriptor word. The operand is unpacked, required signs and exponents added, via lines ZADSP 3-11, E13CIDIC or ASC l 1 zone characters are added if 9-bit decimal characters are indicated by the descriptor word coded information, and stored back in cache 750 at an address specified by an address field in the descriptor word. The data is stored in cache 750 via lines RDOD 20

00-35, ZMD 00-35, ASFA 00-35 and RADO/ZADO 00-35. The decimal unit 730 is under firmware control via lines MEM-DO 88, 89, 94-97. PK-WT1R 0-3 signals from the decimal unit 730 indicate to the execution address and branch circuit 701-1 status information in response to firmware commands received by the decimal unit 730 via the lines MEM-DO 88, 89, 94-97. The PK VCTR 0-3 signals received by the execution address and branch 701 -1 results in the execution 25 control store 701-2 branching to a particular microprogram subroutine. British Patent 2,009,470 described the branching logic associated with the execution control store 701-2.

Data and control signals are transferred between cache 750 and an SIU 100 via the data interface line 600 and between cache 750 and the processor 700 via the lines of interface 604. Lastly, the cache unit 750 receives address and data signals from the data and address output circuits 7044 via the lines RADO/ZADO 00-35 and the lines ASFA 32-33.

Execution unit 714-Figure 2 The unit 714 includes as major units, addressable temporary register banks 714-10 and 714 12, an arithmetic logic unit (ALU) 714-20, a shifter 714-24 and a scratchpad memory 714-30.

Additionally, the unit 714 includes a number of multiposition data selected switches 714-15, 714- 35 17, 714-22, 714-26, 714-28, 714-34, 714-36 and 714-38 to provide flexibility in selecting operands and output results.

In operation, the operands are selected via the ZOPA switch 714-15 and ZOPB switch 714 17 from one of the registers of the banks 714-12 and 714-10 or from other input lines such as ZEBO-35 or RDIO-35 as shown. The ALU 714--20 and shifter 714-24 performs operations upon 40 the selected operands and the results are selected via the switches 714- 24, 714-36 and 714-38 to be applied to the output bus lines ZRESA 0-35 and ZRESB 0-35. Similarly, the contents of a scratchpad location selected via signals applied to the ZRSPA 0-6 lines by the AAW unit 722 can be read out via the switches 714-34, 714-36 and 714-38.

The selected output results or other data are thereafter loaded into other registers within 45 processor 700 including the temporary register banks 714-12 and 714-10 orthe scratchpad memory 714-30 of execution unit 714.

In greater detail, the sources of operands are identical for both the ZOPA and ZOPB switches 714-15 and 714-17. The selection of switch position for the ZOPA switch and ZOPB switch is under the control of the microinstruction word. The ALU 714-20 performs logical, decimal and binary 50 operations upon the selected operand data under the control of the microinstruction word.

The shifter 714-24 is a combinational logic network used to align, shift or rotate binary data under micro-program control. The input data signals from the ZSHFOP and ZEIS switches 714-28 and 714-22 can be viewed as being concatenated to form a single double word input. The shifter 7 14-24 provides a 36-bit output shifted in accordance with the shift count. The ZSHFOP switch 714-28 is controlled by the microinstruction word while the shift count is established by the sequence control constant field of the microinstruction word which is appropriately selected via the auxiliary arithmetic control unit 722. For the purposes of the present invention, the ALU 714-20 and the shifter 714-24 may be considered conventional in design. The microinstruction fields controlling the operation of the execution unit 714 are described in related Application Serial No. 853,944 60 described supra.

The scratchpad memory 714-30 provides a working space for storing various data required for the execution of certain instructions as well as various constants and descriptor values. For example, octal locations 10-15 are used to store an edit instruction table value required for carrying out edit GB 2 114 785 A 5 operations. Writing into the scratchpad memory 714-30 involves first loading the RSPB buffer register 714-32 with input data applied via the ZRES13 switch 714-38. During a next cycle, the contents of the register 714-32 are written into the location specified by the signals applied to the ZRSPA 0-6 lines by the AACL1 unit 722. Writing takes place when bit 22 of the microinstruction word (RSP field) is forced to a binary ONE.

As concerns the other switches, as mentioned, the results produced by the unit 714 are provided via the ZALU switch 714-26, the ZSM switch 714-34, the ZRESA switch 714-36 and the MES13 switch under microprograrn control. The ZALU and ZSP131 switches provide a first level of selection to the ZRESA and ZRES13 switches which provide a last level of selection. Since both the 10 ZRESA and ZRESB switches have identical input sources, they can provide the same output data.

Operands from the decimal unit 730 are received via the Z130 00-35 lines and stored in selected RTRL 0-3 registers 714-12 and RTRH registers 71410 as are described supra. Long operands are stored in scratchpad memory 714-30. The resultant operand is read through the ZRESA switch 714-36 into the RCHO register 720-10 of character unit 720 and to the decimal unit 730 via the RCHU 0-35 line.

Decimal unit 730-general description-system

Referring to Figure 3, the decimal unit 730 is operative under firmware control processing of decimal numeric instructions and receives data words from cache 750 made up of 4-bit characters or 9-bit EBCDIC or ASCII characters. The data word may contain a trailing sign or a leading sign which maybe part of an overpunched character and will also contain an exponent if the data word is apart of 20 a floating point operand.

The decimal unit 730 strips the sign and/or exponent from the data word, compresses the data words from 36-bit words to 32-bit words, packs both the 4-bit and 9-bit decimal digits into data words made up of 4-bit decimal digits, and transfers the resulting 32-bit data words to the execution unit 714 for processing as defined by the instruction.

The most significant and least significant words of the operand received from cache 750 may contain information which is not a part of the operand. This rewrite information is stored in registers and added to the most significant and least significant words of the operand if required during the store operation.

The decimal unit 730 processes operands made up of decimal digits either as short operands or 30 long operands. Short operands are 15 decimal digits long or less. Long operands are from 16 to 64 decimal digits long. Operands having more than 64 decimal digits are not processed in the decimal unit 730 but are nrocessed by the firmware.

Short operands comprising 1 or 2 data words are transferred to temporary registers RTRIL 0-3 714-12 and RTRH 4-7 714-10 in the execution unit 714. Long operands comprising from 3 to 8 35 words are transferred to the scratchpad memory 714-30 in the execution unit 714.

Decimal numeric instructions include an instruction word defining the arithmetic operation to be performed, a descriptor 1 word defining the characteristics of an operand 1, a descriptor 2 word defining the characteristics of an operand 2 and a descriptor 3 word defining the characteristics of a resultant operand 3. Some instructions use descriptor 2 to define the characteristics of both operand 2 40 and operand 3. The instruction and descriptor formats are shown in Figure 5.

The decimal unit 730 under firmware control receives operands 1 and 2 from cache 750, aligns them and transfers them to the execution unit 714. Both operands are checked for an illegal sign or illegal digits. The resultant operand 3 is transferred from the execution unit 714 to the decimal unit 730 where it is unpacked to 36-bit data words from 32-bit data words, ASCII or EBCDIC zone 45 characters are added for 9-bit words. Exponent characters and signs are added if required. Operand 2 or operand 3 rewrite information previously stored may be added. The operand is checked for zero/overflow conditions, is rounded or truncated if required and stored back in cache 7 50.

Descriptors defining the operands are stored in the RSIR register (not shown in the drawings) of the control logic unit 704-1. The RSIR bit positions 21 through 35 corresponding to the bit positions 50 of the descr!ptors of Figure 5, are transferred to and stored in registers in the decimal unit 730. The RSIR bit positions 17-20 are transferred to the decimal unit as signals ASFA 33-36 which are also stored in a register in the decimal unit 730.

As shown in Figure 5, the descriptor fields are defined as follows:

ASFA 33 is the least significant bit of the address of the most significant word of the operand 55 indicating an odd or even word address.

ASFA 34-36 points to the digit position within the most significant word of the high order character of the operand.

indicates an operand of 4-bit characters if a ONE or 9-bit characters if a ZERO.

defines the operand type and sign position.

00 Leading sign floating point or overpunched sign leading.

01 Leading sign scaled.

Trailing sign scaled.

11 No sign scaled or overpunched sign trailing.

RSIR 21 RSIR 22-23 6 GB 2 114 785 A 6 RSIR 24-29 indicates the scale factor, i.e. the position of the decimal point. A negative number movesthe decimal point to left of the least significant digit. A positive number moves the decimal point to the right of the least significant digit. RSiR 30-35 indicates the number of characters in the operand. Characters include decimal digits, sign characters and exponents.

The firmware controls the decimal unit with the signals RCSR 88-89, 94-97. The signals are outputs from the execution control store 701-4. Except for the CLK, ZAM, MPYREG and DUCMD fields, the firmware word is described in detail in the specification of British Patent 2,008,817.

Table 1

Logic name of 10 firmware RCSR Signals controlled 88, 89, 94, 95 96, 97 Description signals

TYPE F CLK, ZAM, MPYREG 1 0 0 0 0 0 Set FMYDV if FPOP 1 D, otherwise NULL DUCMD-200 15 1 0 0 0 0 1 Select RESULT=ZERO indicator 1 DUCMD-201 1 0 0 0 1 0 Select OP 1 =ZERO, OP2=ZERO DUCMD-202 indicators 1 0 0 0 1 1 Load STC MASK into RDOD DUCMD-203 1 0 0 1 0 0 Select DU OVERFLOW and DUCMD-204 20 TRUNCATION indicators 1 0 0 1 0 1 Reset ZERO/OVERFLOW CHECK logic DUCMD-205 1 0 0 1 1 0 Set FCMPN if FPOP 1 D DUCMD-206 1 0 0 1 1 1 Unused TYPE F DUCMD 25 1 1 0 0 0 0 Set F if FPOP 1 D, otherwise NULL DUCMD-300 1 1 0 0 0 1 Read OPERAND through DU DUCMD-301 1 1 0 0 1 0 Force Load Complete Status DUCMD-302 1 1 0 0 1 1 Store Operand Through DU DUCMD-303 1 1 0 1 0 0 Check ZERO/OVERFLOW DUCMD-304 30 1 1 0 1 0 1 Transfer Data from RCHO to RPK DUCMD-305 1 1 0 1 1 0 Load Rewrite Data DUCMD-306 1 1 0 1 1 1 Load the DU Sign Register (RSGN) DUCMD-307 1 1 1 0 0 0 Load the DU Exponent Register (REXP) DUCMD-308 1 1 1 0 0 1 Put the Rounding Constant int o RDOD DUCMD-309 35 1 1 1 0 1 0 Put Operand Leading Zero Count DUCMD-31 0 into RDOD 1 1 1 0 1 1 Put Operand Word Count into RDOD DUCMD311 1 1 1 1 0 0 Unused 1 1 1 1 0 1 Select Descriptor Vector Indicators DUCMD-313 40 1 1 1 1 1 0 Select Store Op Vector Indicators DUCMD-314 1 1 1 1 1 1 Select Long Op Vector Indicators DUCMD-315 Note that the RSCR bit positions 88 and 89, the TYPE F field, define the fields identified by RSCR bit positions 94-97. If the TYPE F field contains a---1 W then microword fields CLK, ZAM, and

MPYREG are selected. If the TYPE F field contains a---11- then microword field DUCMD is selected 45

DUCMD 200 sets the FMYDV flag during a multiply or divide decimal instruction.

DUCMD 201 selects the ADSZ conditional branch.

DUCMD 202 selects the RRLTRD conditional branch indicator if operand 1 equals zero and selects the RREQRD conditional branch indicator if operand 2 equals zero.

DUCMD 203 transfers the RCHU 30-35 output signals storing the STC mask into the RDOD 50 register 730-154.

DUCMD 204 selects the RRI-TRD conditional branch indicator for an overflow and the RREQRD conditional branch indicator for a truncation operation.

DUCMD 205 resets the FCRD and FDIFK flags.

DUCMD 206 sets the FCMPN flag if the FPOP 1 D flag is at logical ONE. 55 DUCMD 300 sets the FMV flag if the FPOP 1 D flag is at logical ONE.

DUCMD 301 starts the operand load operation in the decimal unit 730.

DUCMD 302 forces completion of the load operation by setting the FLDCOMPIand the FRDP 1 flags.

DUCMD 303 starts the store result through the decimal unit 730 by setting the FOPSTR and 60 FMSDRN flags.

7 GB 2 114 785 A 7 DUCMD 304 DUCMD 305 DUCMD 306 DUCMD 307 DUCMD 308 DUCMD309 DUCMD 310 DUCMD 311 DUCMD 312 DUCMD 313 DUCMD 314 20 DUCMD 315 The Decimal indicated below.

sets the FCZO flag for a check zero/overflow of the word stored in the RCHO register 720-10. sets the FM and FRPK flags. sets the FLDREWR flag and selects the RREQRD condition branch indicator for a truncation operation. conditions the loading of the sign register RSGN 730-134. conditions the loading of the exponent register REXP 730-138. Also conditions the loading of the RSF3 scale factor register of register bank 730-4 during a floating point FPOP3 cycle.

controls the loading of the rounding constant stored in the ZM switch 730150 10 into the proper character position of the RDOD register 730-154 and sets the FRCMD flag. controls the loading of the operand leading zero count into the RDOD register 730-154.

controls the loading of the operand word count into the RDOD register 730154.15 unused. selects the descriptor 1 vector and descriptor 2 vector indicators and sets the MM flag. resets the FCRD flag and selects the store vector indicators. selects the long input vector indicators.

Unit 730 responds to the firmware requests with the PK VCTR 0-3 signals Table 2 Vector branch data PK-VCTR 25 0 1 2 3 Type-length 0 0 0 0 Short Operand and 4-bit data 0 1 0 0 Short Operand and 9-bit data 1 0 0 0 Short Operand and (4 or 9 bit data) and overpunched sign 1 1 0 0 Long Operand 30 Descriptor 1 vector 0 0 0 0 Execute Descriptor 2 vector 0 1 0 0 Descriptor 1 =floating point 1 0 0 0 Descriptor 1 =overpunched leading sign, scaled 1 1 0 0 Descriptor 1 =overpunched trailing sign, scaled 35 Descriptor 2 vector 0 0 0 0 Descriptor 2floating point or overpunched sign 0 1 0 0 Descriptor 2=floating point 1 0 0 0 Descriptor 2=overpunched leading sign, scaled 1 1 0 0 Descriptor 2=overpunched trailing sign, scaled 40 Store vector 0 0 0 0 Check for RESULT=ZERO, OVERFLOW 0 1 0 0 Floating point result-Check for RESULT=121, Overflow 1 0 0 0 Overpunched leading sign output-check for FIESULT=Q Overflow 1 1 0 0 Overpunched trailing sign output-Check for FIESULT=O, Overflow 45 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 0 Long-input Both operands scaled and adjusted length descriptor 1:563 and adjusted length descriptor 2:563 and overpunched sign Both operands scaled and adjusted length descriptor 1 <63 and adjusted length descriptor 2563 and overpunched sign Both operands scaled and adjusted length descriptor 1 >63 or adjusted length descriptor 2 < 63 Execute descriptor 1 and descriptor 2 vectors 8 GB 2 114 785 A 8 Table 2-continued Vector branch data Predicted number of cycles of delay for processing descriptor 1 or descriprtor 2 operands PK- VC TR 0 1 2 3 Words of data Cycles of delay 0 0 0 0 1 0 0 0 0 1 2 0 0 0 1 0 1 1 0 0 1 1 2 1 0 1 0 0 1 2 0 1 0 1 2 2 The following Boolean expressions show the firmware selection of the vector branch data:

[1 MVCTR=FDUACT (DUCMD 315+DUCMD 313. MCV1 +FRDP 1 -Dt CMD 313. DUCMD 314. DUCMD 314) 15[2PKVCTR=FDUACT(DUCMD314+DUCMD315+DUCMD301+DUCMD315.FRDPl) [4 MCTR=FDUACT (DUCMD 313+DUCMD 314+DUCMD 315) [PI(VCTR=1 selects the type length vector which indicates to the firmware whether the operand is a short or long operand, 4 bit characters or 9 bit characters and if a short operand whether there is an overpunched sign in the descriptor 1 or descriptor 2 operands.

[PKVCTR=2 or 3 selects for short operands the number of cycles of delay needed after the first read 20 command is sent to cache 750 to the first data word being sent to the execution unit 714. This prediction simplifies the firmware processing of short operands.

[MVCTfl=4 selects the descriptor 1 vector which defines descriptor 1 as a floating point operand, an overpunched leading or trailing sign scaled operand or indicates to the firmware to execute the descriptor 2 vector. 25 [MVCTfl=5 selects the descriptor 2 vector which defines descriptor 2 as a floating point or scaled operand with overpunched leading or trailing sign.

[MVCTR=6 selects the store vector which indicates to the firmware to specific check for resulting operand equal to zero.

[MVCTR=7 selects the long-input vector and indicates to the firmware the comparison 30 between the operand lengths and 63 for scaled operands. The vector also indicates to the firmware to execute the descriptor 1 and descriptor 2 vectors.

The decimal unit 730 supplies a number of conditional branch indicators to the execute address and branch circuits logic 701-1.

Conditional branch indicators 35 Name Source START-WRT RRLTRD SEND-DATA RREQRD OP1=ZERO MLTRD OP2=ZERO RREQRD 40 OVERFLOW MLTRD TRUNCATION RREQRD RESULT=ZERO ADSZ DATA-AVA ADSZ CK-STR-VECT ZAMO 45 The RRTRD signal is generated:

1. during a DUCMD 202 command when the FOP 1 Z flag is set indicating that operand 1 is zero.

2. during a DUCMD 204 command when the FDOFL flag is set indicating that there was an operand overflow.

3. during a start write operation to indicate to the firmware to send write commands to cache 50 750.

The RREQRD signal is generated:

1. during a DUCMD 204 or DUCMD 306 command with the truncation signal at logical 1 indicating that least significant digits of an operand will be lost.

2. during a DUCMD 202 command when the F0P2Z flag is set indicating operand 2 is zero. 55 9 GB 2 114 785 A 9 3. during a send data operation to indicate to the firmware to transfer data to the decimal unit 730 from the execution unit 714.

The ADSZ signal is generated:

1. during a DUCMD 201 command when the operand is equal to zero.

2. when data is not available except during a DUCMD 201 command.

The ZAMO signal is generated to indicate a check store vector function such as floating point, overpunched character, overflow, result=0 operand.

The conditional branch indicators are called for by the firmware and results in an execution control store 701-2 branch.

Description of decimal unit status flags including the boolean expressions for setting and 10 resetting the flags are:

F3DESC FALT FMPN FCPCO FCRP1 FWD FM FDADIS Set for the processing of operand 3 which is defined by either descriptor 2 or descriptor 3. The boolean expression is: F3DESC SET: (FPOP. RDESCO. RDESC1) F3DESC RESET: (FPOA) Set during the store operation on alternate cycles. The decimal unit prepares a word for the RDOD register 730-154 on one cycle and transfers the word to the Execution Unit 714 on the next cycle. FALT set enables the storing of a word in the RDOD register. The boolean expression is: FALT SET: ((DUCMD 303+FOPSTR). 'A-LT. FPOA) FALT RESET: (FOPSTR. FALT+FPOA) Set for a DUCMD 206 firmware command for a compare numeric instruction. The boolean expression is: FCMPN SET: (FPOP 1 D. DUCMD 206) FCMPN RESET: (FPOA) Set when loading or storing 9-bit data words from odd addresses in Cache 750. The boolean expression is: FWC0 SET:j((WPA0. WDUACT. FRDP 1 +SFOP21-D +FLDCOMPL. (DUCMD 303+FOPSTM) + FCPCO. (FOP 1 LD. SFOP2LD +FOP2LD). WDID+FWD)+17CPC0 (DUCMD 303+FOPSTR). [$SRDOD) FPOA) FCPO RESET: (Z"-CPAO. (FDUACT. FRDP 'I +SFOP2LD+FLDCOMPL DUCMD 303+FOPSTR)+FWC0 (F0P1LD.SFOP21-D+FOP2LD) (FDID+FDFP)+FCPCO (DUCMD303+17OPSTR).[$RDOD +FPOA) Set during an operand load operation when one of the operands is long. This flag 40 lets the second load DU operand command (DUCMD 301) start a load process. A long operand causes the decimal unit.to cancel the first load DU operand command (DUCMD 301) to enable the firmware to get set up to process a long operand. The firmware always assumes a short operand operation. The boolean expression is:

FCRP1 SET: (MUCMD 301. FRDPI. (D1 E0OW +D2E0OW +LONG)). FPOA) MRP1 RESET: (FPOA) Set by a DUCMD 305 firmware command or an FM flag on for a check zero/overflow operation and reset by a DUCMD 205 or 314 command. Remains set for the entire operation processing. The boolean expression is:

FCRD SET: (MUCMD 305+FCZO). FPOA) FWD RESET: (DUCMD 314+DUCMD 205+FPOA) Set by a DUCMD 304 or 305 firmware command for a check zero/overflow of the word stored in the RCHO register 720-10. The boolean expression is:

FM SET ((DUCMD 305+DUCMD 304)). F-P-OA) FCZO RESET: (-S-F=+FPOA) Set for 9-bit decimal digit operand loads on alternate cycles to allow two 4 digit words to be received from cache 750 and stored in the RDOD register 730154 as one 8 digit word. The boolean expression is:

FDADIS SET (ZTNSAO. FFIDP2+MSBO FR13P2). DATA-AV. PPOA. SFOP2LD) FDADIS RESET: (SFDADI d$RDI-PC+SFWD +FDFD.RFDFD+SFOP2LD) GB 2 114 785 A 10 FDATA-AV FM FM FDID FDOFL FDTED FDUACT FDVIC1 F13ZER0 FFDO FFOSD FILLDIG Is set to load the RDOD register 730-154 by controlling the strobe signal [$RDODA. The boolean expression is: FDATA-AV SET: (DATA-AV. FPOA) FDATAAV RESET: (SFDATA-AV+FPOA) Is set during a load operation to indicate that the complete operand has been received from cache 750 by the decimal unit 730. The boolean expression is: FDFDSET:(DFCO.FDID.(RFDF).fP-OA. (FOP1LD.SFOP21-D+FOP2LD)) FDFD RESET: WPOA+WiCO. MID. DTECO.[$RDODA+NCO. FDID. FDTED +DTECO. [$RDODA. FDFD) Set when operand data is loaded into the ADID registers 730-158. The boolean expression is: WIDSET:([$11DI-PC. FLDREWR.F-RDPl) MID RESET: (SFDID) Set when an operand overflow is detected during a check zero/overflow operation and reset by a DUCMD 205. The boolean expression is: FDOFL SET ((DUCMD 305+FCZO). DOFL. F-PCA) FDOFL RESET: (DUCMD 205+FPOA) Set when all of the decimal digits of the operand were sent to the execution unit 714 but not all of the operand information has been received by the decimal unit; exponent or sign information for example. The boolean expression is:

FDTED SET: (DTECO. [$RDODA. (RFDFD. FPOA (FOP 1 LD. SFOP21-1)+FOP21 D)) FDTED RESET: (MFM Set during an FPOP control logic unit 704-1 cycle to indicate a decimal unit 730 operation. The boolean expression is:

FDUACT SET: (FPOP) FDUACT RESET: (FPOA) Is set when the firmware sends a DUCMD 313 for descriptor 1 information so that descriptor 2 information is sent on the next DUCMD 313. The boolean expression is:

FDVC 1 SET: (DUCMD 313. FPOA) MM RESET: (FPOA) Is set if the operand check with the check zero/overflow commands DUCMD 304 or 305 equal to zero. The boolean expression is:

FDZERO SET: ((DUCMD 305+FU0). DZERO. FPOA) FDZERO RESET: WPOA+(DUCMD 305+FICZ0). DZERO. FCRD) Is set when the first word of tne operand from cache 750 is loaded into the decimal 40 unit. The boolean expression is:

FFDI SET: ((FDID. 5-FCO. (FOP 1 Ll)+FOP2LD)) FPOA) FFDI RESET: (S170P21-D+FPOA) Is set when the first word of the operand is stored in the RDOD register 730-154 prior to being transferred to the execution unit 714. The boolean expression is: 45 FFDO SET: W$RDODA & (FOP 1 LD+FOP2LD). 115-T-E-CO).'P-O-A) FFDO RESET (SFOP21-D+FPOA) Is set when the first data word to be stored in cache 750 is loaded into the RDOD register 730-154. The boolean expression is:

FFOSD SET: ((FOPSTR+DUCMD 303). [$RDODA. FPOA) FFOSD RESET: (FPOA) Is set when an illegal digit or illegal length is received by the decimal unit 730. It signals a fault to the system and is reset one cycle later by the FLDGR flag. The boolean expression is:

FILLDIG SET: Q[$RDODA. (FPOP 1 LD+FOP21-M 55 DZIDEQID+ILLEGALLENGTH. (SFOP 1 Ll)+FiCZ0)). FLDGR +FPOM FILLDIG REST: (FLDGR+FPOA) FLDCOMPI- Is set when Uoth operands have been transferred to the execution unit 714. The boolean expression is:

FLDCOMPL SET: (((FOP 1 LD. FMVN+FOP2LD FM-VN). (DFCO. FDID. DTECO. [$RDODA+WiCO. MID FDTED +DTECO. [$RDODA. FND) +DUCMD 302). FPOA) FLDCOMPL RESET: (FPOA) 1 11 GB 2 114 785 A FLDGR FLIDREWFI FMSDRN FMSEQ FMVN WYDV FOP 1 LID FOP 1 Z FOPSTR Is set at the same time as the FILLDIG flag, i.e., when an illegal digit or illegal length is received in the decimal unit 730. It resets the FILLDIG after one cycle. The boolean expression is: FLDGR SET: Q[$RDODA. (FOP 1 LD+FOP2LD) DZIDEQID+ILLEGALLENGTH (SFOP 1 LD+FCZO)). FPOA) FLDGR RESET: (FPOA) Is set from the firmware by a DUCIVID 306 load rewrite data signal to start the sequence for storing the first or last words defined by descriptor 3 in the REWR 0 3 register bank 730-177. The boolean expression is:

FLIDREWR SET: (DUCIVID 306) FLDREWR RESET: (DUCIVID 309) FLIDREWRI-1 Is set one cycle after the FLDREWR flag is set to strobe the first or last word into the REWR2 or REWR3 register respectively of the REWR 0-3 register 730-177 during a descriptor 2 store operation. The boolean expression is:

FLDREWRH SET: (FLDREWR) FLIDREWRI-1 RESET: (FI-DREWR) FMSDRGTE Is set during a store operation on a DUCMD 303 firmware command if word count in the FIRM register is greater than or equal to the word count in the RWPC register at the time the DUCIVID 303 is used. The boolean expression is:

FMSDRGTE SET: (DMSDRGTE DUCIVID 303) _. FAWT. (DUCIVID 303. RRWCO+FMSDRN). FPOA) F0P2F FMSDRGTE RESET: (FPOA) Sets on the DUCIVID 303 firmware command for a long operand store if the word count in the RRWC register is negative in. The boolean expression is: 25 FIVISIDRN SET: (DUCMD 303. RRWCO. FPOA) FIVISIDRN RESET (FPOA) Sets during a long operand store sequence when the word count in the RRWC register equals the word count in the F1WPC register. The boolean expression is:

FMSEQ SET: (DMSEQ. (FSWRT. DIVISIDRGTE+13T (ZTNSAO+ZTNSAO. FCPCO)) (DUCIVID 303+FOPSTR). FALT (MUCIVID 303. RRWCO+FMSDRN). FPOA FMSEQ RESET: (FPOA) Is set for a move numeric instruction. The boolean expression is:

FWN SET: (DUCIVID 300. FPOP 1 D) FMVN RESET: (FPOA) Is set for multiply and divide instructions. This flag suppresses the scale factor alignment and right justifies the operands on a load operation. The booiean expression is: WYDV SET: (DUCIVID 200. FPOP 1 D) WYDV RESET: (FPOA) Is set for the operand one load operation. The boolean expression is:

FOP 1 LID SET: (DUCMD 301. R--DP 1. PP'OA. (D 1 EQOVP. DIEGOW. LONG+FWP 1)) FOP 1 LD RESET: WPOA+FOP 1 LD. DFCO. DTECO. FIDID. [$RDOIDA+FOP1 LID. DFCO.FIDID. FIDTED+FOP 1 LID. DTECO.[$RDODA. FWD) Is set if operand 1 equals zero. The boolean expression is:

F0P1 Z SET: ([$RDODA. FOP 1 LID. WIDEW. FPOA) FOP 1 Z RESET: (FPOA) Is set by the DUCIVID 303 store operand through decimal unit 7jO firmware command. The boolean expression is: FOPSTR SET: (DUCMD 303. FPOA) FOPSTR RESET: (FPOA) Is set for an operand 2 load and the first data word is received in the RDID register 730-155. The boolean expression is: F0P2F SET: (FIDID. F0P2LD. FPOA. 5-F-CO) F0P2F RESET: WPOA+MO. FIDID) 12 GB 2 114 785 A 12 F0P2LD F0P2S F0P2Z FM FRCIVID FRDIDH Is set for the operand 2 load operation. The boolean expression is: F0P2LD SET: ((FOP 1 LD. FIVIM (DUCIVID 301 +FRDP2). (DFCO. FDID. DTECO.[$RDODA+13FCO. MID. FDTED +DTECO. SRDODA. FDFD)+FOP 1 LD FMVN. DUCMD 301. FRDP 1). F-PO-A) F0P2LD RESET: (FPOA+FOP2LD. (DFCO. MID DTECO. [$RDODA+DFCO. MID MED+DTECO. [$RDODA. FDFD)) Is set on an operand 2 load operation when the second word is stored in the RDID 10 register 730-158. The boolean xpression is:

F0P2S SET: (F0P2F. MID. FPOA) F0P2S RESET: (FPOA) Is set if operand 2 is equal to zero. The boolean expression is:

F0P2Z SET: ([$RDODA. F0P2LD. DMIDEQZ. FPOA) F0P2Z RESET (FPOA) Is set if operand 1 or operand 2 are specified as floating point. The boolean expression is:

FPFL SET: ((DIEQFLT+D2EQFLP) FOP 1 LD. FPOA)) FPFL RESET: (FPOA) Is set by a DUCMD 309 firmware command to read the rounding constant into the RDOD register 730-154. The boolean expression is:

FRCIVID SET: (DUCIVID 309. -P-OA) FRCIVID RESET: (FPOA) Is set to indicate that the requested information is not stored in cache 750 and 25 cache must request if of backing store. When the data is received in cache and sent to the decimal unit 730, the FRDIDH flag gates the recovery signal to strobe the data into the RDID register 730-158. The boolean expression is:

FRIDIDH SET: ([$RDI-PC) FRDIDH RESET: (FRDIDH) Is set by DUCIVID 301 or DUCMD 302 firmware commands to indicate that the command for reading the first operand has been issued to the decimal unit 730.

The boolean expression is:

FRDP 1 FRDP1SET:((DUCMD301.( EQ0VP.1312EQ0VP LONG +FiCRP 1) +DUCIVID302) FFOUR 35 FRDP 1 RESET: (FPOA) FRDP2 Set by a DUCMD 301 firmware command when the FRDP 1 flag is set to indicate that the command for reading the second operand has been issued to the decimal unit 730. The boolean expression is.

FFIDP2 SET: (DUCIVID 301. FRDP 1. FPOA) 40 FRIDP2 RESET: (FPOA) FREWR Is set by the FI-DREWRI-1 flag in the cycle following the setting of the FI-DREWRI-1 flag. The flag is used to force the rewrite data to be read from REWR2 and REWR3 during the operand store process. The boolean expression is:

FREWR SET: (FLDREWRH. FPOA) 45 FREWR RESET: (FPOA) FREWR2 Is set by the FREWR and FI-DREWRI-1 flags both on. It causes the REWR3 register to be used to provide rewrite data for the last word of operand 3. The boolean expression is:

FREWR2 SET: (FLDREWRH. FREWR. FPOA) 50 FREWR2 RESET: (FPOA) F3DESC Is set for the descriptor 3 operation. The boolean expression is:

F3DESC SET: (FPOP. RDESC6. TD-ESC1) F3DESC RESET: (FPOA) FPOP3D Is set for the cycle following FPOP3 cycle of the control logic unit 704-1. The 55 boolean expression is:

FPOP3D SET: (FPOP. RDESCO. RDESC1) FPOP3D RESET: WPOA+FPOP3D. (DUCMD 305+FCM) FPTL Is set for the condition that the adjusted length, length plus scale factor difference is greater than 63 characters. The boolean expression is: 60 FPTL SET: (ALNSUE63. FOP 1 LD. FPOA) FPTL RESET: (FPOA) 13 GB 2 114 785 A 13 FRPK Is set on a DUCMD 305 transfer data from RCHO to RK firmware command and is used for the short operation store. The. boolean expression is:

FRPK SET: (DUCMD 305. DIEWILP. FPOA) FRPK RESET: WPOA+DUCIVID 205) FSND Is set when the SEND DATA bit is forced to a ONE. SEND DATA indicates to the 5 firmware to load a new word into the RCHO register 720-10 during a long operand store. The FSND flag strobes the previous word stored in the RCHO register into the RPK register 730-162. The boolean expression is:

FSND SET: (FALT. SEND-DATA. FPOA) FSND RESET: (FALT. SEND-DATA+FPOA) 10 FSSFD Is set when the scale factor difference is negative. The boolean expression is:

FSSFD SET: (ASF2. FDUACT. FR13P1) FSSFD RESET: (AM. FDUACT. FRDP 1 +FPOA) I'SWFIT Is set when the STRT-WFIT signal to the firmware is forced to ONE. STRT-WRT enables the firmware to start issuing write commands to the cache 750 during the 15 long operand store procedure. FSWU informs the DU hardware control that the firmware is issuinwrite commands. The boolean expression is:

FSW11T SET: (FALT. STRT-WRT. (DUCMD 303 +FOPSTR). FPOA) FSWFIT RESET: (FPOA) 20 FPOP 1 D Is set for the cycle following FPOP 1 cycle of the control logic unit 704-1. The boolean expression is: -R FPOP1D SET: (FPOP. RDESCO. DESC1) FPOP 1 D RESET: (SFPOP 1 D) FT13130 Are set as a 2-bit counter to countdown the number of cycles of delay for strobing 25 FTDB 1 the operand word into the RDOD register 730-154 for transfer to the execution unit 714. The boolean expression is:

FTD130 SET: (TDBO. DUCMD 301. FPO7k) FZCF FT1)130 RESET: (TDBO. DUCMD 301 +WOP 1 LD +FOP2LD). DUCMD 301.[$RDI-PC + FPOA) FT1)1311 SET: QTD131. DUCMD 301 +FTDBO (FOP 1 LD+FOP2LD). DUCMD 35-1. [$RDI-PC). FPOA) FT131 RESET: (TDBI. DUCMD 301 +FTDBl. (FOP 1 ILD+FOP2LM. DUCMD 301.[$RDI- PC+FPOA) Is set during the load operand procedure when the first non zero character is detected in the input data. It indicates the end of the number of leading zeros in the operand. FZW SET: ([$RDODA. (FOP 1 LD+ FOP2LD). EZ-CO. FPWOA)) FZW RESET: (SFOP2LD+FPOA)) The following are the boolean expressions for functions not previously described: SFU0=MUCIVID 305+DUCIVID 304). FPOA SMADIS=(ZTNSA0. FR13P2+MSBO. FRDP2). DATA-AV. FPOA SFOP2LD- 45 SFDFD=DFCO. MID. (RFDFD). FPOA SMATA-AV=DATA-AV. FPOA [$RDI-PC=ENABIZ+FTRF+FMT. (SRAD01. (RDIN. EQ. 0-1 M +TYPE. (MISREG. EQ. 4)+TYPD. (IBILIF. EQ. 3))+FIVIT ((IBPIPE. EQ. 1). FE112+TYPI31) (2). (MSKI). NEQ. 0) 50 +TYPBD (3). STO+FREWA. (RMEM. EQ. (8-110)) +FREQDI+FDIDBL SMID=[$RDI-PC. FI-DREWR. FRDP l DOFL indicates an overflow condition DZIDEQID=(Z]D4. (ZID5+ZID6))+(ZID8. (ZID9+ZID10)) 55 +(ZID12. (M1 3+Z11314))+ (M1 6. (M1 7 +ZID1 8))+WD20. (M21 +Z[D22))+(ZID24 (ZID25+ZID26))+(ZID28. (ZID29+ZID30)) +0D32. (ZID33+ZID34)) ILLEGALLENGTH=ALNDAO+ALNDBO+ALNDAZ+ALNDBZ 60 DZERO indicates that the operand word contains all zeros.

14 GB 2 114 785 A 14 Decimal unit-logic The scale factors for operands 1, 2 and 3 are received in the decimal unit 730 through a 4position switch ZSM 730-2 over signal lines RSIR 24- 29 from the control logic unit 704-1 and are stored in registers RSFO, RSF1, RSF2 respectively of register bank 730-4. ZADSP 3-11 signal lines apply the scale factor to position 0 of the switch when the scale factor is calculated by the firmware. Al-NDA signal lines apply the adjusted length of operands to position 2 of the switch during a floating point operation. The AEDC and ZEDC signals are applied to position 3 of the switch to store the number of effective digits during a floating point operation. This is described in greater detail as part of the store operation description.

Control signals [1 ZSFN and [2ZSFN select the switch 730-2 positions. The boolean expressions10 are:

[1 WM=((F3DESC+FIVIVN). FLDCOMPL. T-PO-P. D1 EQ171-P +DUCIVID 305+FCZO)) [2ZSFN=((F3DESC+FMVN). FLDCOMPL. FPOP. D1 EMP) For a non floating point operands the operand 2 scale factor is selected by the RSF1 position of a 15 ZSF13 switch 730-8 and is applied to an input of an ASF adder 730-10 where the operand 2 scale factor is subtracted from the operand 1 scale factor selected by the RS170 position of a ZSFA switch 730-6. If the operand 1 scale factor is larger than the operand 2 scale factor then the signals AS170-9 represent a positive number and bit position ASF2 is a logical ZERO. If the operand 2 scale factor is larger, then the signals ASFO-9 represent a negative number and bit position ASF2 is a logical ONE. 20 The length or number of numeric characters for operands 1, 2 and 3 is received over signal lines RSIR 30-35 from the control logic unit 704-1 and are stored in registers RI-NDO, RI-ND1 and RI-ND2 respectively of a register bank 730-12. An ALNDA adder 730-18 and an Al-NDB adder 730-20 calculate the number of decimal digits in operands 1 and 2 respectively. This is accomplished by subtracting the number of non digit characters in the operand such as sign and exponent from the 25 length. The output of a decode logic 730-38 and a decode logic 730-40 is applied to adders AI-NDA 730-18 and ALNDB 730-20 respectively to adjust the operand 1 and operand 2 lengths.

The sign and decimal type for operands 1, 2 and 3 are received over signal lines RSIR 21-23 from the control logic unit 704-1 and are loaded into registers RTNSO, RTNS1 and RTNS2 respectively of register bank 730-32. A ZTNSA switch 730-36 selects the operand 1 sign and decimal type stored in register RTNSO and applies it to the decode logic 730-38. A scaled unsigned operand results in a ZERO output, a scaled signed operand results in a ONE output, a floating point operand having 9-bit decimal digits results in a TWO output and a floating point operand having 4-bit decimal digits results in a THREE output from decode logic 730-38 respectively. The output valuels subtracted from the operand 1 length in the Al-NDA adder 730-18 to give as an output, signals ALNDA 0-6 which indicate the number of decimal digits in operand 1. The number of decimal digits in operand 2 indicated by signals Al-NDB 0-6 are calculated in a similar manner.

Signals DBITX and DBITZ are logical ONE indicates that a binary ONE is subtracted from the Al-NDA adder 730-18 and the Al-NDB adder 730-20 respectively. The boolean expressions are:

13131TX=QZTNSA1. ZTNSA2)+(ZTNSAO. iT-NSA1 - MSA2)) 40 DBITZ=UTNS131 ZTNS132WZTNS130.ZTNS131 ZTNSB2)) Signals D1 EWLP and D2EQ171-P at logical ONE indicates that a binary TWO is subtracted from the ALNIDA adder 730-18 and the Al-NDB adder 730-20 respectively. The boolean expressions are:

D1 EWLP=(iTN-SA1 ZTNSA2. (ZTNSA0+ROPM D2EQFLP=(ZTNSB 1 ZMS132. (ZTN5130+ ROP M ROP 1 indicates an overpunched sign instruction.

A ZAI-ND switch 730-22 selects the adjusted length of the operand with the larger scale factor and applies the output to an ALNS adder 730-24 which adds to it the absolute value of the scale factor ASF 0-9 output of the ASF 730-10 adder. Bit position ASF2 selects the operand with the larger scale factor. Bit position AM at a logical ONE indicates that the operand 2 scale factor is larger. 50 The output of a ZI-NAW switch 730-26 applies the adjusted length to an ARWC counter 73060 and an ACPR counter 730-62. The inputs to the ZI-NAW switch 730-26 are described below.

If the operand 1 scale factor is larger, then the switch selects the ALNS 0-9 input signals for operand 1 and the ALNDB input signals for operand 2.If the operand 2 scale factor is larger, then the switch selects the Al-NDA 0-6 input signals for operand 1 and the ALNS input signals for operand 2. A floating point operand or a multiply or divide instruction does not require a scale factor alignment, therefore, the ALNDA 0-6 and Al-NDB 0-6 input signals are selected for operand 1 and operand 2 respectively. The RI-M input signals are selected during a floating point store operand and provide the number of leading zeros in the operand.

Control signals 41 ZI-NAW and 42ZLNADJ select one of four positions of ZINAW switch 730- 60 26. The boolean expressions are:

1 GB 2 114 785 A 15 [1 ZI-NADJ=(FI-DCOMPIL. FRDP 1. F-SSFD+FMYDV+D 1 EQFLP +D2EQ1=CP+ALNS2)+ FI-DCOMPL (F3DESC +FIVIVN). D 1 EQFLP. FDOFL) [2ZI-NADJ=(FDOACT. FRDP 1. AS172 +FRDP 1. FSSFID). FMYDV. D1 EQFLP. D2EM -ALNS2. FI-DCOMPI+FI-DCOMPL. (F3DESC+FIVIVN). D1 EMP +D 1 EQFLP. FDOFL) If the outputs of the ALNDA adder 730-18, the ALNDB adder 730-20 and the ALNS adder 730-24 are all 15 decimal digits or less, this indicates that the non floating point decimal instructions are executed in the short operand mode. This mode provides for increased system throughput in 10 processing decimal instructions over the prior art, since much of the operand manipulation is done using logic performing many of the operand setup functions in parallel. The prior art performed many of the functions serially. The boolean expression for the short operand is as follows:

Short=(AMA1. Al-NDA2) (ALNDBl.;"L-NDB2) (L-NS3. ALNS4 ALNS5+FIV1YDV) (U1 -EQFLP+D2EQFLP) Note that the scale factor adjustment is not implemented for the multiply or divide instructions.

The ARM adder 730-60 calculates the number of words to be transferred to the execution unit 714 for both short and long operands. The signal [ONE/ARMB is applied to the minus input to adder ARWC 730-60 and, when at logical ONE, is subtracted from the adjusted length ZI-NADJ1 0-9 for a load operation. This assures that if the adjusted length as indicated by the ZI-NAW 0-9 signals 20 was 8-decimal digits, i.e. the ZI- NADJ6 signal was a ONE, then subtracting ONE would make bit position ARWC6 a ZERO and 8 decimal digits will be loaded into the first word. Discarding bit positions ARM 7-9 leaves bit position ARWC6 as indicating the number of words for the short operand. A ONE in bit position ARWC6 indicates a short operand of 2 words and a ZERO indicates a short operand of one word. The boolean expression for control signal [ONE/ARWCB is:

[ONE/ARWCB=FLDCOMPL+ZTNSA1 (ROP1+MSA0 +ZTNSA2))+(FRPK. ZI-NADJ7. ZI-NADJ8 ZI-NADJ19. FLDCOMPQ) The ARWC 0-6 output signals indicating the number of words in the operand is available to the firmware when the execution control store 701-4 sends a firmware word which is decoded in the 30 decimal unit 730 as a DUCMD 311---PutOperand Word Count into RDOD- signal and makes the word count available through a Z= switch 730-76, position 3 of a ZID switch 730-150, position 0 of a MOD switch 730-152 to a RDOD register 730-154 from which it is transferred to the execution unit 714.

The ACM adder 730-62 subtracts the adjusted length in decimal digits decoded by the 35 ZI-NAW 0-9 signals from decimal 64. The quantity 64 is the maximum number of digits in an operand that is processed by the decimal unit 730. The resulting output signals ACPR 3-9 indicate the number of zero digits to the left of the high order digit position for a 64 decimal digit operand. This value is stored in an RLIVIP register 730-102. Bit positions RLIVIP 4-6 store a binary code indicating the number of high order positions in the first word of the operand received by the decimal unit 730 to 40 be forced to ZERO. The RLMP 4-6 signals are applied to a Z113MU shifter 730-130. The number of high order digits to the left of the most significant digit position to be forced to ZERO is indicated by the number of successive signals starting with the ZIDMU 0 signal which are forced to ZERO. The ZIDMU 0-7 signals are applied to a [WID logic control 730-132. The output signals [EZID 0-7 output signals suppress the ZID switch 730-150 in zero to the left positions and enables the digit positions 45 of a ZI D switch 730-150 starting with the most significant digit position. The portion of the RLMP register 730-102 storing the RI-MP 0-3 bit positions has the capability of being incremented for every operand word received by the decimal unit 730 by the [CNTUP-RLIVIP1. 1 signal. The boolean equation is:

[CNTUPRLMPU=((FOP 1 LD+FOP2LD). [$RDODA. SFOP2LD) The boolean expression for the signal [ONE/ACPNBB is:

[ONE/ACPNBB=(ZTNSA1. R-O-P1 +MSA0+ZTNSA2) (WDUACT. FRDP l)+FL13COMPI- FRIPK ZI-NADJ7. ZLNADJ8. ZI-AND0) +(ZTNS131 (ROP 1 +ZTNSBO+ZTNSB2)). (FRDP 1 55 FLDCOMPQ) An ATIVIP adder 730-30 calculates the number of zeros to the right of the least significant digit of the operand with the larger scale factor. The ZASM switch 730-28 selects the adjusted scale factor binary signals ASF 0-9 which are added to the quantity 63 if the operand 2 scale factor is larger or subtracted from the quantity 63 if the operand 1 scale factor is larger. The output signals ATIVIP 3-9 are loaded into an RTMP register 730-100. Bit positions RTIVIP 0-3 store a binary 16 GB 2 114 785 A 16 count of the number of words of the operand to the left of the word containing the least significant digit position. B -6 store a binary number indicating the least significant bit position.

1Laositions RTIVIP 4 Signals RTIVIP 4-6 indicate the number of zeros to the right of the. least significant digit.

A comparator 730-104 compares signals RTMP 0-3 and RLMP 0-3. The difference equals the number of words of the operand to be received by the decimal unit 730 from cache 750. The binary 5 word count RLIVIP 0-3 is incremented each time a word of the operand is loaded into the RDOD register 730-154. The difference between binary signals RTMP 0-3 and RLW 0-3 is zero when the last word of the operand is received in the decimal unit 730 thereby enabling the A=B output signal of the comparator 730-104. This enables the TMSC 0-3 output of TMSC logic control 730 106 which is a binary count of the number of zeros to the ight of the least significant digit. This count 10 is applied to the TMSC logic control 730-106 by signals RTMI 4-6. The TMSC 0-3 count is applied to a Z1DIVIL shifter 730-120. The number of low order digit positions to the right of the least significant digit to be forced to ZERO is indicated by the number of successive signals starting with the ZIDML 7 signal which are forced to ZERO. The Z1DIVIL 0-7 signals are applied to the [EZID 0-7 logic control 730-132. The output signals [EZID 0-7 reflect the ZMIDL 0-7 signal states and enable the high order positions of the Z11) switch 730-150, forcing the low order positions to the right of the least significant digit to ZERO.

The ASFA 33-36 signals are received from the address preparation unit 7043 for operands 1, 2 and 3 and are stored in registers RCPO, RCP 1 and RCP2 respectively of a register bank 730-42.

The ASFA 33 signal indicates the least significant bit of the cache 750 address of the high order -20 word of the operand indicating whether this word is from an odd or even memory address location.

This is used in the compacting of operands having 9-bit characters which are received in the decimal unit 730 as 4 decimal characters per word to 8-decimal digits per word, which is sent to the execution unit 714.

For 9-bit character operands, signals ASFA 34 and 35 indicate the position of the leading 25 character in the high order word of the operand. For 4-bit character operand words, signals ASFA 34 36 indicate the position of the leading character in the high order word of the operand.

The operand pointer stored in register RCPO is selected through the RCPO position of a WPA switch 730-44 and applied to a ZWNB switch 730-48. The MPA 0-2 position of the MPNB switch 730-48 is selected if operand 1 comprises 9-bit characters and the WPA 1-3 position is 30 seiected if operand 1 comprises 4-bit characters. Signa! [ONE/ACMBB is applied to an input of the AWNB adder 730-50 and is added to the ZWNB 0-2 withals if operand 1 has a leading sign. This is indicated by the 1 -bit of the RTNSO register being a ZERO. The AWNB 1- 3 output of the adder points to the most significant decimal digit position of the high order word of operand 1 as it is received in the decimal unit 730 from cache 750.

An ACMF adder 730-52 subtracts the high order digit position from the ACPR 7-9 signal output of the ACPR adder 730-62. The ACPR 7-9 binary signal indicates the number of ZER0s to the left of the most significant digit in the operand high order word to be transferred to the execution unit 714. Subtracting binary signals AWNB 1-3 from ACPR 7-9 in the AMF adder 730-52 gives an output binary value signal AMF 0-3 which is the amount the operand being received from 40 cache 750 is shifted to be properly aligned for transfer to the execution unit 714. This shift value is stored in an RDSC register 730-58 through a switch 730-56. The output of the RDSC register 730-58 is applied to a shifter 730-156 through a MSC switch 730-72. The AMF adder 73052 calculation is made separately for operand 1 and operand 2 and aligns the operands relative to each other for numeric processing in the execution unit 714.

A WPM switch 730---46selects the operand character pointer for 4-bit and 9-bit character operands and applies it to an ACPWC adder 730-66 where a quantity ONE is subtracted to give an output signal ACPWC 0-3. A ZI-NT switch 730-64 selects the operand 1 length for the operand 1 load and the operand 2 length for the operand 2 load for input to an ASWC adder 730-68 where it is added to the ACPWC 0-3 binary signal. A ZSM switch 730-70 selects an ASWC 0-4 switch 50 position for a 9-bit character operand and an ASWC 0-3 switch position for a 4-bit character operand and applies the ZSM 0-4 binary output tor storage in an RSWC register 730-110.

The RSWC register 730-110 stores a binary count of the number of words in the operand to be transferred from cache 750 to the decimal unit 730. The count in the RSWC register 730-110 is decremented by a [CNTDWN-RSWC signal each time a word is received in the RDID register 730- 55 158. The boolean expression for the signal is:

[CNTDWN-RSWC=((LDRRWC(FDID. (FOP 1 LID+FOP2LD) DLFCO+[$RDODA. (DUCMD 303+FOPSTRM [LIDRRM--WDUACT - FRIDP 1 +SFOP21-D +FLIDCOMPL. (FOPSTR+DUCIVID 303)) DFCO=RSM0. RSMT. R-S-WC2. RSWC3. RSWET4 [$RDODA=(FDATA-AV+DUCIVID 203+DUCIVID 310 +DUCIVID 309+FRK. DUCMD 303+F-RP-K. -A-LT FSWRT). DUCIVID 311 17 GB 2 114 785 A 17 The RSWC register 730-110 at zero indicates that all the words of the operand have been received by the decimal unit and the DFCO signal output sets the FWD flag in status flag control logic 730-202.

The ARWC adder 730-60 output signals ARWC 0-6 are stored in an RRWC register 730-88 when the [LDRRWC signal is at logical ONE. The RRWC register 730-110 stores the number of words 5 in the operand to be transferred to the execution unit 714 during the load operation. Each time a word of an operand is loaded into the RDOD register 730-154, the RRWC register 730-110 is decremented by one when the [CUTDWN-RRWC signal is at logical ONE. The boolean expression is:

[CNTDWNRRWC=(DTECO. (FOP 1 Ll)+FOP21-13). [$RDODA +00PSTR+DUCIVID 303. (DMSDRGTE +(DIVISEQ. RDSCOffi. FALT. (FSWRT DIVISI3RGTE+(MSA0. FWCO+MSA0) FSMT)). FR-M+FRK. DUCMD 303 (TT-NSAO. FWCO+MSA0)) DTECO=RR-WCO'. RRWC1. RRM2. RRM3. RRWC4. RRWC5. RRM6 The RRWC register 730-110 at ZERO indicates that all the decimal digits of the operand have been sent to the execution unit 714 by the DTECO output signal setting the FDTED flag in status flag control logic 730-202.

The FOP 1 LD flag is set by the firmware initiating a DUCMD 301 signal indicating a "READ Operand through Decimal UniV operation. The FOP 1 LD flag is reset when the DFCO and DTECO Output 20 signals indicate that both the RSWC register 730-110 and the RRWC register 730-88 respectively have decremented to ZERO during the operand 1 load operation. The FRDP 1 flag set indicates that the DUCMD 301 has been issued to read operand 1 through the decimal unit 730.

The F0P2LD flag is set by the firmware to read operand 2 when the DUCMD 301 has been issued with the FRDP 1 flag set. The F0P2LD flag is reset and the RLDCOMP flag is set indicating that the load 25 operation is complete when both the RRWC and RSWC registers have decremented to ZERO during the operand 2 operation, i.e., both operands 1 and 2 have been processed in the decimal unit 730 and transferred to the execution unit 714.

An RI-M register 730-96 and an RLZC2 register 730-98 are used to indicate to the firmware the number of zeros to the left of the most significant non-zero digit in operand 1 and operand 2 respectively. e ister positions RLW l 1-3 and RLZC2 1-3 are loaded with the ARWC 4-6 output signals of the ARWC counter 730-60. This essentially prebiases the word count portion of the RLZC 'I and RLX2 registers, bit positions RI-M and RLZC2 0-3 with the value of 7 words minus the number of words to be sent to the execution unit (binary value of the ARWC counter 730-60 bit positions ARWC 4-6) and equals the number of words not being sent to the execution unit 714. The 35 number of leading zeros to the left of each operand is sensed at the output of the Z11) 730-150. The fl-D 04-35 signals are applied to the load zero count logic 730-182 and the output LZC 0-3 indicates the number of leading zeros in the word. Signal LWO being a ONE indicates that all the decimal digits of the word are zero, a ONE is added to the RLW 'I or RIM2 registers at the bit 3 position and the next word is received from cache 750. Again, if the word contains all zeros then signal 40 LWO is a ONE, a ONE is again added to the bit 3 position and the next word is received from cache 750. Assume that the next word received from cache 750 does not contain all zeros, then the signals LZC 1-3 indicate the number of zeros to the left of the first non-zero decimal digit. This sets an FWI flag indicating to the logic that the ZERO to the left count is completed for this operand. This count is transferred through a ZEDC switch 730-82 to the RLZC1 and RI 7C2 registers and stored in bit 45 positions RLW 1 4-6 and RI-M2 4-6 for their respective operands.

The binary values stored in the RI-M register 730-96 and RLX2 register 730-98 are the count of the number of digit positions to the left of operands 1 and 2 respectively to fill the 64 decimal digit positions set aside in the execution unit 714 for each operand.

The output of the RLZC 1 and RLX2 registers are transferred under firmware control through a 50 MC switch 730-76 position 3 of the ZI D switch 730-150, through the MOD switch 730-152 to the RDOD register 730-154. The ARWC signal input to the ZI-M switch 730- 76 provides the number of words transferred for a long operand. The ATIVIP signal input provides the word location to which the rounding constant is added. The boolean expressions controlling the R= 'I register 730 96 and the RWC2 register 730-98 for loading the low order positions of the registers are:

[$RLZCIL=([$RDODA. FOP 1 LD. FZW+(DUC[VID 305 +FCZO). DEDC2) [$RLZC2L=([$RDODA. F0P2LD. FZC+(DUCMD 305 +FCZO). DEDC2) The boolean expressions for loading the high order positions of the registers are:

[LDRLZC1 U=SFOP 1 LD+(DUCIVID 305+FCZ0). DEDW [LDRLZC2U=SFOP2LD+(DUCMD 305+FCZO). DEDW DEDW=EDCO.EDC1.EDC2.EDC3 18 GB 2 114 785 A 18 The registers are incremented by:

[CNTUP111-Z1C1 U=[$RDODA. FOP 1 LD. FZCF. LWO [CNTUPRI-MU=[$RDODA. F0P2LD. FZCF. LWO SFOP 1 W=(DUCIVID 301. RR-W 1. FP-OA. (51 -EQOVP. D2EQ0VIP LONG+17CRP SFOP21-D=WOP 1 LD. FIVIM (DUCIVID 301 +FR13P2) (DFCO MID. DETECO. [$RDODA+WCO. MID. FDTED +DTECQ. [$RDODA. MFM+FOP1 LD. FMVN DUCMD 301. FRDP 1) FPOA) D 1 EGOW=(D131TX. ROP 1 ZTNSAO) D2EQ0VP=(DI3ITZ. ROP 1 ZTNSBO) LONG=Al-NDAGTE1 6+Al-NDI3GTE1 6+ALNSGTE1 6. FMYDV+Dl EMP+D2EMP ALN DAGTE 1 16=ALN DA 1 +ALN DA2 Al-ND13GTE16=Al- ND131+Al-ND132 ALNSGTE 'I 6=ALNS3+ALNS4+ALNS5 Decimal unit-load operation Operands are transferred from cache 750 to the decimal unit 730 over signal bus W1 0-35 and are loaded into an RDID register 730-158 under firmware control. The firmware initiates a DUCMD 301 "Read Operand Through Decimal UniV command. This sets the FRDP 1 and the FOP 1 LD flags to 20 condition the decimal unit 730 logic to receive operand 1 from cache 750.

The RSM register 730-110 is loaded with the number of words to be received from cache 750. The RRWC register 730-88 is loaded with the number of words to be sent to the execution unit 714. The RSM register 730-110 is decremented by ONE for each word received from cache 750.

The RRWC register 730-88 is decremented by ONE for each word sent to the execution unit 714. The 25 boolean expressions for the loading and decrementing the RSM and RRWC registers 730-110 and 730-88 respectively are:

[LDRSWC=((FDUACT. FRDP l)+Wi-DCOMPL. DUCMD 303. FOPSTR)+SI7OP21-M [CNTDWNRSWC=((CD-RRWC WDID (FOP 1 LD+FOP21-13) WCO+[$11DODA. (DUCIVID 303+FOPSTU) [LDRRWC=(FDUACT. FRDP 1 +S17OP21-D+FI-DCOMPI(FOPSTR+DUCMD 303D [CNTDWN-RRWC=(DTECO. (FOP 1 Ll)+FOP2LM. [$RDODA +((FOPSTR+(DUCMD 303 (DMSDRGTE +(DMSEQ. RDSCOM). WNT. (FSWRT DIVISDRGTE+(MSA0. FCPCO+MSA0) FSWRT)). FRPK+FRPK. DUCMD 303 (TT-NSA0. FCPCO+ ZNTSAO)) The FOP 1 LD flag is reset on the cycle following the RSWC and RRWC registers counting down 40 to zero by the DFCO and DTECO outputs at logical ONE. The boolean equations are listed supra. This indicates that all of the operand 1 words have been received by the decimal unit 730 and sent to the execution unit 714. The firmware initiates another DUCMD 301 command which sets the F0P2LD flag since the FRDP 1 flag is still set conditioning the decimal unit 730 to receive operand 2 words. Again the RSM register 730-110 and the RRWC register 730-88 are loaded with number of words received from cache 750 and sent to the execution unit 714 respectively and counted down to zero indicating to the decimal unit 730 that operand 2 was received, processed, and transferred to the execution unit 714. The F0P2LD flop is then reset.

The operand may contain 4-bit or 9-bit decimal digits. Operands containing 4-bit decimal digits are processed through the decimal unit 730 differently from operands containing 9-bit decimal digits. 50 ssuming that the operands contain words with 4-bit decimal digits and the first word is stored in the RDID register 730-158. Control signal [1 ZM is forced to a ONE selecting the 1 position of a ZPK switch 730-160. The RDID 0-35 output signal is compacted from a 36 bit word to a 32 bit word in the selected position 1 of the ZM 730-160 switch and outputs as signal bus ZM 0-31 which may indicate up to eight 4-bit decimal digits. The negated output signal bus ZM 0-31 is stored in an RPK 55 register 730-162. The decimal digits of this data word are the high order digits of the operand. If the decimal digits of the first word of the operand outputting the ZM switch 730-160 have a sufficient number of decimal digits to be sent to the execution unit 714 as specified by the decimal unit 730 logic then the necessary switches are conditioned by their respective control signals to load the RDOD register 730-154. In this case the ZM 0-31 output signals are selected through a ZKR switch 60 730-164. The output signals ZMR 0-31 are applied to the shifter 730-156 where they are 19 GB 2 114 785 A 19 shifted to the right an amount specified by the MSC 1-3 binary shift count output of the RDSC register 730-58. The MS 0-31 output signals are applied to a ZID switch 730-150 where non decimal digit characters such as signs and exponents and also non-operand replacement characters are replaced by zero under control of the [WID 0-3 Z11) switch enable signal output of the [WID control logic 730-132. The output signals Z11) 4-35 are selected by position 0 of the MOD switch 730-152. MOD 4-35 output signals are stored in the RDOD register 730-154.

If the data word made up of 4-bit digits will not fill a sufficient portion of the RDOD register 730-154 fortransfer to the execution unit 714, then the first word remains stored in the RM register 730-162 and the next data word of 4-bit digits is transferred from cache 750 to the RDID register 730-158 under firmware control. The second data word is applied to the shifter 730-156 through 10 the ZM switch 730-160 and the ZMR switch 7301 64. The first data word stored in the RK register 730-162 is applied to the shifter 730-156 through a ZPKL switch 730-166. The shift count signal MSC 1-3 selects 32 of the 60 inputs to the shifter 730-156. The MS 0-31 output signals are stored in the RDOD register 730-154 through the ZID switch 730-150 and the MOD switch 730-152. Necessary zeros to the left and right are added to the MS 0-31 shifter output under control of the [EZID 0-7 enable signals while the operand word is switched through the Z11) switch 730-150.

If the operand from cache 750 to the decimal unit 730 consists of a 9-bit decimal digit the first data word containing a maximum of 4 decimal digits is stored in the RDID register 730-158. The 9- bit decimal digits are stripped of the 5 high order bits of each decimal digit and compacted as the word 20 is switched through the selected 2 position of the ZM switch 730-160 and are stored in either the left 16-bits of the RM 0-15 register 730-162 if from an even address in cache 750 or are stored in the right 16-bits of the RM 16-31 register 730-162 if from an odd address in cache 750.

If a data word may be made up to send to the execution unit 714 then it inputs the shifter 730 156 through the ZM switch 730-160 and the ZPKR switch 730-164. Note that the decimal digits 25 are repeated in ZM 0-15 and ZM 16-31 switch position 2 as the digits pass through the SM 0 31 switch. The extraneous digits, the sign, exponent and rewrite digits are stripped from the data word in the Z11) 730-150 switch. The MS 0-31 output of the shifter 730-156 is stored in the RDOD register 730-154 through positions 0 of the Z11) switch 730-150 and the MOD switch 730-150 and the MOD switch 730-152. 30 Assuming that the first data word comprising 9-bit characters was received from an even cache 750 address and stored in RM 0-15 register 730-162, the second data word would be received from an odd cache 750 address and would be stored in the RM 16-31 register 730-162.

The second data word is applied to the shifter 730-156 through the ZM switch 730-160 and the ZPKR switch 730-164 after being stripped of the high order 5-bits of each 9-bit decimal digit and 35 packed into both halves of the ZM 0-31 data word. The first data word stored in either the odd address or even address half of the RP K register 730-162 is applied to the shifter 730-156 through the ZPKIL switch 730-166.

Control signals [1 ZM and [2ZM select one of four positions of the ZM switch 730-160.

Position 0 is selected for the store operation, position 1 for the 4-bit digit operand, position 2 for the g- 40 bit digit operand and position 3 for the rounding operations. The boolean expressions are:

[1 ZPK=ZTNSAO. FOP 1 LD+ZTNSBO. FOP2LID+DUCIVID 309 [2 ZPK=ZTNSAO. FOP 1 LD+ZTNSBO. FOP21-1)+DUCM1) 309 Control signal [$RPM enables the loading of the RK register 730-162, positions RK 0-15 for 9-bit operands from an even cache 750 address, and 4-bit operands. Control signai.[$RPKL enables. 45 the loading of RK register 730-162, positions RK 16-31 for 9-bit operands from an odd cache 750 address, and 4-bit operands.

The boolean equations are:

[$RPKU=DUCMD 305+FDID..(ZTNSAO. FOP 1 LD +ZTNSBO.FOP2LD+ZTNSAO.FOP1LD 50. C-PCO.+ZTNSBO. FOP2LID. FCPCO) 50 +FRPK. FOPSTR. (FA-LT. FS+FAILT. FSWRT. FSI\IM) [$RPKL=DUCMD 305+FIDID. (ZTNSAO. FOP 1 LD +ZTNSBO.FOP2LD+ZTNSAO.FOP1LD FCPCO+ZTNSBO.FOP2LD.FCPCO) +FRPK. FOPSTR. (FALT. FSWFIT +FALT. FSWIRT. FSW)) Control signals [OZPKL and [OZPKR enable respectively the ZPKL switch 730- 166 and the MR switch 730-164. Control signal [1ZPKL, at logical ONE selects the ZPK 4-31 bit positions from ZPKL switch 730-166 and the RK 16-31 bit position from ZKR switch 730-164. Control 60 signal [1 ZKRU, at logical ONE, selects the RK 0-15 bit positions of the ZPKR switch 730-164.

GB 2 114 785 A 20 [UPKA=FOP 1 1-13+FOP2LID+(FOPSTR+DUCIVID 303) (FRIPK. (DIVISIDREQ11 0. RIDSCO+LIVISIDRE0OM 1 ))+F PKFMSDRN.(DMSDRLTM1 +FMSDRGTE. DIVISIDRILTIV12). FMSEQ)) [WPI(R=FOP 1 LID+FOP2LID+(FOPSTR+DUCIVID 303) (FRIPK. (DMSDREQ21. RIDSCO+DMSDREG1 0 RIDSCO)+WK. FIVISIDRIVI. (FMSDRGTE DIVISIDRILTIV1 1 +RRWCO). DIVISEQ)+ DUCIVID 309 FRR+DII EQ1FLIP+(ATIVIP 0-6). FRCIVID +(ATIVIP 0. 1.2. 3. 4. 5. 6). FRCIVIDD [UPKR=(DIVISIDRQEQ1. RIDSCO+DTECO. RDSC. FRIPK. (FOPSTR+DUCIVID 303) [1 ZIPKRU=WOP 1 LID. ZTNSA0+170P2LID. ZTNS130) RDSC1 +(FOPSTR+DUCIVICID 303). FRIPK (DIVISIDRWEQ1. RIDSCO+DTECO. RDSCO) DMSDREG1 O=DTECO+DMSDRWEQ1 DIVISIDRWEQ1V1 1 =RRWCO. FWC 1. IRRWC2. RIRWC3. RIRWC4. RIRWC5. RRWC6 DIVISIDRE0OM 1 =DTECO+DMSDRWEQM2 DIVISIDRILTIVII 1=RRWCO. DIVISIDRWEQ1V1 l DMSDRLTM2=RRWCO. (RIRWC 1. RRWC2. RRWC3. RIRWC4. RRWC5) DMSDREQ21 =DMSDRWEQ2+DMSDRWEQ1 DTECO=: RWCO. -RWC 1. RWC2. R13WC3. R13WC4. RIFtWC5. RRWC6 DIVISIDRWEQ1 =RRWCO. RRWC 1 RRWC2. RRWC3. RRWCZ. RRWC5. RRWC6 DMSDRWEQ2=RRWCO. RRWC1 RRWC2. RRWC3. RRWC4. RRWC5. RRWC6 The boolean expressions for the control signals that condition the operand words during both the 25 load and store operation are as follows:

[1 Z1 D=DUCIVID 203+DUCIVID 31 0+DUCIVID 311 +FRIPK FRCMD. DUCMD 309 [2V D 0-7=DUCMD 31 0+DUCIVID 311 +(FRIPK. FRCIVID DUCMD 309)+WRIDG-MASK [1ZDODO=([STRPKD=[UNPKDLWR+[UNPKDUPR ([1ZSMRO+[2ZSMRO) [1 ZDOD1 =([STRPKD+[UNPKDLWR+ [UNPKbOPR C ZSMR2+[2ZSMR2) [1ZDOD2=([STRPKD+[UNPKDLWR+[UNPKDUPR ([1ZSMR4 +[2ZSMR4) [1ZDOD3=([STRPKD+[UNPKDLWR+ [UNPKbuPR ([1ZSMR6+[2ZSMR6) [2ZDODO=(4STRPKD+[UNPKDUPR+[UNPKDLWR ([1ZSMRO+[2ZSMRO)) [2ZDOD1=(4STRPKD+[UNPKDUPR+[UNPKb!WR ([USIVIR2+[2ZSIVIR2)) [2ZDOD2=(4STRPKD+[UNPKDUPR+[UNPKDLWR 0 ZSIVI1R4 +[2ZSIVIR4m) [2ZDOD3=(4STRPKD+[UNPKDUPR+[UNPKDLWR ([1ZSMR6+[2ZSMR6) PZSIVIR 0-7=S IG N MASK +REWUM 0-7+REWILM 0-7 [2ZSIVIR 0-7=EX1P MASK+ REWUM 0-7+REWILM 0-7 [STRPI(D=(ZTNSA0 (DUCIVID 303+FOPSTU [UNIPKIDILWR=(ZTNSA0 (DUCIVID 303+FOPSTR). FCPCO) [UNIPKIDUPR=(ZTNSA0 (DUCIVID 303+FOPSTR). FCPCO) An AUR adder 730-62 calculates the number of zeros digits to the left of the operand necessary to fill a 64 digit block of storage. The adjusted length ZI- NADJ1 0-9 output of switch 730- 45 26 is subtracted from 64, the maximum number of digits that will be transferred between the decimal unit 730 and the execution unit 714. The output of the ACIPR adder 730-62 is stored in the RILIVIP register 730-102. The IRLIVIP 4-6 output signals, the low order 3-bits, store the number of 4-bit decimal digit positions to the left in the high order word to be forced to zero and is applied to the shift count input of a ZIDMU shifter 730-130. Those output signals ZiDMU 0-7, which indicate zero digits to the left, are forced to ZERO. This forces the indicated outputs of [WID logic control 730-132, signals [WID 0-7 to ZERO thereby forcing the selected digit positions of the Z11) switch 730-150 to ZERO of the first word of the operand received by the decimal unit 730. If the operand had a leading sign, it would have been replaced by ZERO in the ZI D 730-150 switch since the sign character position count was subtracted from each operand length in adders ALNIDA 730-18 and ALNDB 730-20 respectively. Also, rewrite characters in the operand word would be replaced by ZERO's.

An ATIVIP adder 730-30 calculates the number of zeros to the right of the least significant digit position of the operand having the larger scale factor. Switch ZASF13 730- 28 selects the number of zeros to the right for operand 1 or operand 2 during that cycle in which the operand transfers from cache 750 to the decimal unit 730.

If the operand 1 scale factor is larger than the operand 2 scale factor than the ASIF 0-9 input to -40 21 GB 2 114 785 A 21 switch ZASF13 730-28 is a positive number which is subtracted from 63 in the ATMP adder 730-30 and the difference, output signals ATIVIP 3-9, are stored in an RTIVIP register 730-100. The low order positions RT-MP 4-6 input a TMSC logiccontrol 730-106 and output as signals TMSCO-3 which are applied to the shift count input of a ZIMI- shifter 730-128. This forces the MIVIL 0-7 output signals to indicate the number of digit zeros to the right of the operands. The MIVIL 0-7 5 output signals are applied to the [EZID logic control 730-132. The [EZID 0-7 output signals condition the indicated low order digit positions of the ZID switch 730- 150 to ZERO thereby stripping trailing sign, exponent, and rewrite characters from the operand word.

Signals RTMP 0-3 the output of register 730-100 and signals RLIVIP 0-3 the output of register 730-102 indicate the cycle on which the operand word which requires the ZER0s to the right 10 is transferred from the decimal unit 730 to the execution unit 714. The 64 decimal digit maximum transfer is made up of eight words of 8-decimal digits per word. Signals RLIVIP 0-3 are a binary representation of the number of words to the left of the word containing the most significant digit that contains all zeros. Signals RTMP 0-3 are a binary representation of the number of words in the maximum transfer minus the word in which ZER0s to the right are forced. Plus 1 is added to binary signals RLIVIP 0-3 each time register RDOD 730-154 is loaded. Signals RTIVIP 0-3 and FILIVIP 03 are compared in a comparator 730-104. Signals TMSC 1-3 are forced to ZERO on the cycles where binary signals RTMP 0-3 is greater than binary signals RLIVIP 0-3 ZER0s to the right are forced in the ZID switch 730-150 on the transfer cycle where comparator 730-104 indicates that the binary values of FILIVIP 0-3 and FITIVIP 0-3 are equal.

Control signal [$RTIVIP enables the input loading of RTMP register 730100, and the RLIVIP 46 bit positions of the FILIVIP register 730-102. Control signal [$RTMP enables the output of the RLIVIP 0-3 bit positions of the RLMP register 730-102.

Control signal [ZERO/RLIVIPI- enables the output of the RLIVIP 4-6 bit positions. Control signal [CNTLIP-RLWU increments the RLIVIP 0-3 bit positions. The boolean equations are:

[$UMP=(FDLIACT. FRDP 'I +SFOP21-M [ZERO/RLMPL=(FFDO+(FOP 1 Ll)+FOP2LM. [2MM [CNTUP-RLMPU=((FOP1LD+FOP2LD). [$RDODA.SFOP2L Decimal unit-Figure 3-store operation The FPOP3 cycle loads descriptor 3 information into register RSIR 704-154 for a 3 descriptor 30 instruction. In decimal arithmetic instructions, descriptor 3 defines the field into which the results of the calculation of the descriptor 1 and descriptor 2 operands are stored. Some instructions store the result of the descriptor 1 and descriptor 2 operand calculations in the field defined by descriptor 2. In either case the RSIR register 704-154 stores the descriptor information and transfers it to the decimal unit 730 for the store operand 3 operation. The decimal unit 730 receives operand 3 from the 35 character unit 720 over the RCHU 0-35 signal bus. The decimal unit unpacks it, adds the sign and exponent if required, positions the operand 3 digits within the word, places the proper number of zeros to the left and right of the operand, adds required ASCII or E13C131C zone bits and reinstates the portion of the first and last words of the operand that are not defined as part of the operand. The decimal unit 730 sets up the necessary controls in the logic to receive operand 3, manipulate it and store it in cache 40 750 in conformance with its descriptor information.

The opQrand 3 scale factor signals RSIR 24-29 inputs switch ZSM 730-2 and are stored in register RSF2.of register bank 730-4. For the case where the input operands were such that the decimal unit 730 did the scale factor alignments, the ZSFA switch 730-6 selects the contents of the RS172 register, and the ZSF13 switch selects the contents of either the RSFO or RSF 1 register of register 45 bank 730-4. The register selected is the one storing the smaller scale factor of operand 1 or 2. The FSSM flag which is set by the scale factor comparison during the load operation makes the selection.

* Control signals 4WRRSF1 and 4WRRSF2 select 1 of the RSF 0-4 registers 7304 in which the scale factor is stored. The boolean expressions are:

[WRRSF1 =03DESC+FiVIVN) FLDCOMPL. FPOP. D1 EMP) DUCIVID 305. FCZO)+RDESC1. FPOP+YDV +17PT1_+FPFU DUCMD 308. D1 E0FI-P (FMVN+F3DESC). FPOP. FL13COMPI [WRRSF2=((FMYDV+FPTL+FPFL) DUCMD 308. FP-OP. FLDCOMPI D 1 EMP (FMVN+F3DESC)+RDESCO. FPOP + (F3DESC+FIVIVN) FLDCOMPL. FPOP. D 1 EMP) The ZSF13 switch 730-8 output is subtracted from the ZSFA switch 730-6 output in the ASF adder 730-10. The ASFO-9 output signal inputs the ALNS adder 730-24 and is also stored in the RSCLM register 730-144 where it serves as a pointer to the least significant end of the data to be actually stored.

For a floating point store operation, the RSF3 register of register bank 730-4 stores the adjusted length output of the Al-NDA adder 730-18 and the RSF2 register holds the effective digit counts of the internal results the first time the count is taken, i.e., the output of the AEDC adder 730- 22 GB 2 114 785 A 86 and the ZEDC1-3 output of the ZEDC switch 730-82 inputting the ZSM switch 730-2. In this case the contents of the RSF3 register is selected through the ZSFA switch 730-6 and the contents of the RS172 register is se lected.th rough the ZSFB switch 730-8 and are subtracted from each other in the ASF adder 730-10. Again the ASFO-9 output is applied to the input of the ALNS adder 730-24 and the RSCLM register 730-144. However, for the purposes of obtaining the zero or 5 effective digit count, the first time the operand is examined, the contents of the RSCLM register 730 144 are over written in forming up the inputs to the output zero and overflow detection logic 730-80.

After the first count, if the number of effective digits is greater than the adjusted length of operand 3, the decimal overflow flag FDOFL will be set and the calculation of the effective digit count from RSF2 register contents minus the adjusted length from the contents of the RS173 register will be enabled at 10 the output of the RSCLM register 730-144 for a subsequent zero and overflow examination.

The length field signals RSIR 30-35 are stored in register RI-ND2 of register bank 730-12 and are switched through the RI-ND2 position of the ZI-NDA switch 730-16 to input the ALNIDA adder 730-18.

Control signals [ 1 ZSFA and [MFA select the outputs of the RSF 0-3 registers 730-4 for 15 application to the plus input of ASF adder 730-10. Control signals 1 ZSFB and M1713 select the RSF 0-3 outputs for application to the minus input of ASF adder 730-10.

The boolean expressions are:

[1 ZSFA=-F-3D-E9-C. FLDCOMPL. (FMVN. D1 EMP) [MFA=F3DESC. FLIDCOMPL+FIVIM FLDCOMPL. F1 E0171-12 [1ZSFB=FMVN. L+FMVN. FSSFD FLIDCOMPL.(F3DESC+FIVIVN) 5-1 E0FI-P. (FMYDV+FPTL+FPFL) +FLDCOMPL. (F3DESC+FIVIVN). D1 EMP +FLIDCOMPL. (F3DESC+FiVIVN). D1 E0FI-P 25 (FMYDV+FPTL+FPFL)+FLDCOMPL. (F3DESC +FWM) [2ZSFB=FLDCOMPL. (F3DESC+FIVIVN). D1 E0FI-P +FLIDCOMPL. (F3DESC+FIVIVN). UT-EMP (FMYDV+FPTL+FPFL) The sign and decimal type signals RSIR 21-23 are stored in register RTNS2 of register bank 30 730-32 and are transferred through the RTNS2 switch position of the ZTNSA switch 730-36 to the decode logic 730-38 where the correction factors to the length are determined. If operand 3 is a nine-bit floating point number then 2 digits are subtracted from the length. If operand 3 is scaled with a leading or trailing sign then 1 digit is subtracted from the length. A four-bit floating point number will have 3 digits subtracted from the length. The boolean expressions for signals DBITX and DLEOFI-P 35 which are applied to the ALNIDA adder 730-18 and the ALNDB adder 730-20 were described supra.

The output of decode logic 730-38 is applied to the other inputs of the ALNDA adder 730-18 and subtracts from signals ZI-NDA 0-5. The output of the ALNIDA adder, signals ALNIDA 0-6, adjusts the length to indicate the number of decimal digits in operand 3. The ALNDA 0-6 output signals are 40 applied through the ZAI-ND switch 730-22 to the input of the ALNS adder 730-24. The scale factor signals ASF 0-9 are added to the ALNIDA length and the output signals ALNS 0-9 is the adjusted length of operand 3. The output ALNS 0-9 is applied through the zero position of the ZI-NAW switch 730-24 to input adders ARWC 730-60 and ACPR 730-62 and is stored in an RSCUM register 730-78. Adder ACPR subtracts the adjusted length ZI-NAW 3-9 from 64 and its output signals 45 ACPR 3-9 indicates the position of the most significant digit to be stored within the internal result field. Signals ACPR 7-9 indicate the position of the most significant digit within the word of the operand containing the most significant decimal digit. The signals ACPR 7- 9 are applied to the input of the ACPSC adder 730-54.

The output of the ARWC adder 730-76, signals ARM 0-6 are applied to the RRWC register 50 730-88 and indicates the location of the operand word containing the most significant digit to be transferred from the decimal unit 730 to cache 750. A ONE is added to the ARWC adder in the case of operand 3 having a leading sign which would result in another word being transferred to cache 750.

For the floating point operation during the first examination for zero or overflow, i.e., the DUCMD 304 check zero overflow command and for any subsequent examinations for which the overflow flag 55 FDOFL has not been set then the ALNIDA adder 730-18 output is selected through the ZINADJ switch 730-26. If on a floating point output result the decimal overflow flag FDOFL had been set then the ALNS adder 730-24 output is selected through the ZI-NAW switch 730-26. The ALNS adder 731-24 forms the difference between the adjusted length output of the Al- NDA adder 730-18 and the effective digit count minus the adjusted length from the ASF adder 730-10 output.

The starting character pointer signals ASFA 33-36 are stored in register RCP2 of register bank 730-42 and are selected by the RCP2 switch position of the MPA switch 730- 44. Signal WPA 0-3 inputs the ZCPNB switch 730-48. If operand 3 is made up of 4-bit characters then signals WPA 1-3 are selected and if operand 3 is made up of 9-bit characters then signals WPA 0-2 are 23 GB 2 114 785 A 23 selected as the output signals ZCPNB 0-2 to input the AC1PN13 adder 730- 50. A ONE is added to the ACPNB adder if the operand has a leading sign. The output signals AC1PN13 0-3 are applied to the input of an ACPSC adder 730-54. Switch 730-56 by means of the FI-GCOMPIL status flag selects signals ACPSC 0-3 for storage in register RDSC 730-58. The ACIPSC adder 730-54 subtracts the most significant digit position within the internal operand word as indicated by the ACIPR 7-9 signals from the digit position within the in storage word of the most significant digit as indicated by the ACPNB signal to give the value of the number of digit positions the operand to be stored is shifted. This value represented by signals ACIPSC 0-3 stored in register RDSC 730-58 is the shift count for the ZDS shifter 730-156.

The ASWC adder 730-68 output signals ASM 0-6 provides input signals to ZSM switch 10 730-70, ZRLMP switch 730-112, ZSIVIP switch 730-116 and the ZEMP switch 730-120. The outputs of the switches are applied to shifters 730-114, 730-118 and 730- 122. The shifter outputs are applied to control [1ZSMR logic 730-142 and control [2ZSMR logic 730-146 for generating the [1 ZSIVIR 0-7 and [2ZSMR 0-7 signals. These signals are applied to the ZSMR switch 730-180 for loading the sign, exponent and rewrite characters into the operand 3 words. The starting 15 character pointer signals MPA 0-3 are applied to the input of switch 730- 46 whose output, signals ZCIPM 0-2 are derived from signals ZCIPA 1-2 for a 9-bit character operand and signals ZCIPA 1 3 for a 4-bit character operand. Signals ZCPWC 0-3 are applied to the input of adder ACIPM 730 66. The decimal digit ONE is subtracted and the output, signals ACIPM 0-3 are applied to the input the ASM adder 730-68. The length field of operand 3, signals ZLNDA 0-5, are added to the 20 starting character pointer minus ONE to indicate the character pointer for the last decimal character in the operand.

The first word of operand 3 is received from the character unit 720 over signal lines RCHU 4 35, through buffer 730-168 which generates the assertion signals RCHU 4- 35 and the negation signals RCHU 4-35.

Control signals [1 ZPK and [UPK select the zero position of the ZM switch 730-160 and RCHU 4-35 appear at the output of the switch as signals ZM 0-31 and ZM 0-3 1.

For the long operand, that is operands greater than 15 decimal digits, the operand is transferred from the RCHU 720-10 a word at a time with the word containing the most significant decimal digits being transferred to the decimal unit 730 first.

If a sign is required for the operand, the firmware loads the RSGN register 720-134 over the ZADSP 3-11 signal lines from the auxiliary arithmetic and control unit 722 in response to a DUCIVID 307 command "Load the DU Sign Register". The output of the RSGN register 730-14 is applied to selected position 1 of the ZSIVIR switch 730-180. The character location in ZSIVIR switch position 1 is selected as follows. The output of the ASWC adder 730-68 points to the low order character position of a trailing sign. The output of the ZCPA switch 730-44 points to the leading sign character position.

A ZSIVIP switch 730-116 selects a trailing or leading sign for 4-bit or 9bit operands. The ZSIVIP 1-3 shift count is applied to an SIGNM shifter 730-118. The logical ZERO input to the SIGNM shifter 730-118 selects the one of the SIGNM 0-7 output signals for 4-bit operands. The logical ZERO and the ZTNSAO signals select two adjacent signals of the SIGNM 0-7 output signals for 9-bit operands. 40 The signal SIGNM 0-7 output of the shifter selects the [1 ZSMR 0-7 output signal of control 11ZSMR 730-142 which selects 1 of 8 of the switch 1 positions of the ZSIVIR switch 730-180 for the 4-bit decimal digit operand sign or 2 adjacent positions for the 9-bit character operand sign.

The exponent is added to the operand in response to the DUCIVID 308 "Load the DU Exponent Register- command. An REXP register 730-138 is loaded from the ZADSP 3-11 signal bus. A ZEXP 45 switch 730-140 selects the exponent bit configuration for an operand having 4-bit decimal characters and storing the least significant 4-bit character in an even digit location in cache 750 through the ONE position of the ZEXP switch. All other exponents are selected through the 0 position of the switch. The signal ZEXP 0-8 output is applied to the 2 position of the ZSIVIR switch ZSIVIR 730-180. The exponent character positions are selected by the [2ZSMR 0-7 signal outputs from a 50 control logic [2ZSMR 730-146. The signal is generated as follows. The boolean expressions for control signals [1 ZSMR 0-7 and [2ZSMR 0-7 are shown supra.

The ASWC 5-6 output signals of the ASM adder 730-68 indicate the location in the low order word of the operand of the low order character for 9-bit characters. Binary ONE is subtracted from this value in an ACPE adder 730-74 to give the location of the high order digit of the exponent for an operand made up of 4-bit characters. A ZEMP switch 730-120 selects the character position and the output signals ZEMP 1-3 are applied to an EXPM shifter 730-122. The EXPM 0-7 output signals are applied to the control logic [2ZSMR 730-146. The output signals USIVIR 0-7 select the two adjacent character positions in the ZSIVIR switch 730-180 to enable the exponent to be written into the low order word.

For a 4-bit operand it is possible for the most significant digit position for the exponent character to be in digit position 7 and the least significant position to be in digit position 0 of the next word. In this case the EXPM mask 730-122 generates a ONE output on the EXPM7 signal line when the ZEMP switch 730-120 pointer is at decimal 7 during the next to the last word received. When the last word is received the ZEMP switch pointer remains at 7, the DBITS input signal is forced to a ONE 65 24 GB 2 114 785 A 24 resulting in the EXPIVIO line being forced to ONE thereby activating the 0 character position of the least significant word.

The boolean expression for the DBITS signal is:

DBITS=WC0 (DUCMD 303+FOPSTR) (ACPE1. ACPE2. ACPE3) D1 EQ171-P Signals RDESCO and RDESC 'I are applied to the write select inputs of RI- NDO-3 register 730- 5 12, RTNS0-21 register 730-32 and RCPO-3 registers 730-42. Signals RDESCO and RDESC1 are binary coded 00, 01 and 10 to identify operands 1, 2 and 3 respectively.

Control signals [1 ZI-NDA and [2ZI-NDA are applied to the ZI-NDA switch 730-16 and the ZTNSA switch 730-36. Status flag FMVN is applied to the ZI-ND13 switch 730-20 and the ZTNW switch 730-34.

Control signals [1 MPA and [2WPA are applied to the XPA switch 730-44. The boolean expressions describing the signals are:

[1ZLNDA=-F3-D-Eg-C-. FI-DCOMPI [2ZI-NDA=F3DESC. FLDCOMPI [1 MPA=FRDP 1. FI-DCOMPE+F3DESC. FLDCOMPI [2WPA=F3DESC. FI-DCOMPI The ZSMR 0-35 output including decimal digits, exponents and sign are applied to the MOD switch 730-152 and are loaded into the RDOD register 730-154 for transfer to the cache 750.

In the short operand store the words are received from the execution unit 714 with the last significant word first and the most significant word last. A DUCMD 305 '7ransfer Data from RCHO to 20 RK- command is initiated by the firmware. The least significant word is received from the character unit 720 over the RCIAU 4-35 signal bus and is stored in the RPK register 730-162 through a buffer 730-168 and position 0 of the ZM 730-160 switch. If the short operand comprises 2 words then the most significant word is placed in the RCHU register on the same cycle and appears over the RCHU 4-35 signal bus on the following cycle through the buffer 730-168 position 0 of the ZM 730 switch and is applied to the input of -a ZMR switch 730-164 and a ZM switch 730-166 as signals ZM 0-3 1. If the short operand was only one word long, zeros are placed on the RCHU bus to serve as the most significant word.

The negated output of the buffer 730-168, signals RCHU 4-35 is applied to the input of an output zero and overflow detection logic 730-80 and the effective digit logic 730-81. During the 30 cycle in which the DUCMD 305 is present the least significant word is tested for zero or overflow and the most significant word is tested for zero or overflow on the following cycle which is marked by the FCZO flag being at logical ONE.

An RSCUM register 730-78 stores the operand 3 length plus scale factor output of the ZI-NAW switch 730-26. An RSCLM register 730-144 stores the operand 3 scale factor output of the ASF 35 adder 730-10. The outputs of the RSCUM and RSCLM registers input the logic unit 730-80.

The zero and overflow detection logic 730-80 masks out the non operand 3 field and indicates to the firmware if the operand 3 field is zero since the DZERO output signal of detection logic 730-80 is at logical ONE in that case and also masks out the operand 3 field and the scale factor field and indicates to the firmware if there was a non zero decimal digit in the character positions to the left of 40 the most significant character of operand 3 in the most significant word that is the DOFL output signal of detection logic 730-80 is at logical ONE. The RSCLM and RSCUM register outputs are used to mask out the non operand 3 character positions and, in addition the RSCUM register output masks out the operand 3 and scale factor character positions thereby enabling the overflow cheek.

The boolean expression for loading the RSCUM register 730-78 and the RSCLM register 730 144 is:

[LDRSCM=(FLDCOMPL (FWD+DUCIVID 314+DUCIVID 205) (DUCIVID 305+FCZ0j) The boolean expression for decrementing bit position RSCUM 0-6 and RSCLM 0-6 is:

[CNTDWNRSCM=(DUCMD 305+FCZO) A DUCMD 303---StoreOperand through Decimal Unit- command is initiated by the firmware.

Since this is a short operand operation, 2 words are sent from the execution unit 714 to the decimal unit 730 over the RCHU 4-3 5 bus. The least significant word remains stored in the RP K register 730-162 and the most significant word remains on the RCHU 4-35 bus for the processing of the instruction.

The RRWC register 730-88 stores the internal location of the most significant data word to be transferred from the decimal unit 730 to cache 750. The register is decremented each time a word made up of 4-bit characters is sent to cache 750. The register is also decremented each time a word made up of 9-bit characters is sent to an odd address in cache 750. The boolean expression for the decrementing signal [CNTDWN-RRWC are described supra.

The RDSC register 730-58 stores the shift count which is applied to the ZDS shifter 730-156 through the MSC switch 730-72.

Assuming the shift count is positive, i.e. the RDSCO bit is a zero and the RRWC register indicates a word count of greater than 1, then the zero outputs of the ZPKL switch 730-166 and ZKR 730 164 are applied to the shifter 730-156. The MS 0-31 output signals are zero and are applied to 65 1 GB 2 114 785 A 25 the Z11) switch 730-150. The ZID 0-35 output signals are applied to the ZSMR switch 730-180 where the rewrite characters and leading sign may be added to the most significant word. The ZSIVIR 0-35 output is applied to the MOD switch where for 9-bit character words, EBCDIC or AS '11 zone characters are added and the MOD 0-35 output signals loaded into the RDOD register 730-154 for transfer to cache 750. Control signal [$F1DODA at logical ONE loads the RDOD register 730-154. The boolean expression is:

[$RDODA=((FDATA-AV+DUCMD 203 +DUCIVID 310 +DUCIVID 309+FRK. DUCMD 303+ FFIPK. FALT. FSWIRT). DUCMD 311) When the count in the RRWC register 730-88 equals ONE then the most significant word 10 stored in the RCHO register 720-10 and appearing on the RCHU 4-35 signal bus is applied through the buffer 730-168 through position 0 of the ZM switch 730-160, through position 0 of the ZMR switch 130-164, through the MS shifter 730-156 where it is shifted to the right the number of digit positions equal to the MSC 1-3 binary shift count. Zeros equal in number to the shift count are inserted to the left of the most significant digit position. The MS 0-31 output signals are switched 15 through position 0 of the Z11) switch 730-150. The output signals Z11) 4- 35 are applied to the ZSIVIR switch for 4-bit characters where the word is expanded from 32 to 36 bit positions. The ZSIVIR 0-35 output signals are switched through position 3 of the MOD switch 730- 152 to the RDOD register 730-154 from which the word is transferred to cache 750.

If the word comprises 9-bit characters, then the Z11) 0-35 output signals are applied to position 20 2 of the MOD switch 730-152 if the word is written in an even address in cache 750 or applied to position 1 of the MOD switch 730-152 if the word is written in an odd address in cache 750 through the RDOD register 730-154. Assuming a word to an even address in cache 750. Then the ZID 4-35 is switched through position 2 of the MOD switch 730-152 where the 4 characters indicated by Z11) 4-19 are expanded to 36 bits by adding the EBCDIC or ASCII zone characters. On the next cycle the 25 Z11) 4-35 signals are switched through position 1 of the MOD switch where the Z0 20-35 signals are expanded to 36 bits by adding the EBCDIC or ASCII zone characters.

The RRWC register 730-88 is decremented each time a 4-bit character word is transferred to cache 750 or each time a 9-bit character word is transferred to an odd address in cache 750. The RRWC counter 730-88 is decremented to zero with the shift count MSC 1-3 a positive binary 30 number. In this case the ZM 4-31 output signals are applied through the ZM switch 730-166 and the RPK 0-3 output signals are applied through the MR switch 730-164 and the second word is processed as before.

The RRWC register 730-88 is decremented to binary -1 with the shift count MSC 1-3 a positive number. The RPK register 730-162 storing the least significant word has its RM 0-31 35 output signals applied through the ZM switch 730-166 to the MS shifter 730-156. Zeros were applied to the MS shifter 730-156 through the ZPKR switch. The MS 0-31 output signals are applied through the switches to load the RDOD register 730-154 for transfer to cache 750.

If required the FIRM register 730-88 is decremented to binary -2. Zeros are applied to the MS shifter 730-156 inputs. This cycle of operation enables the exponent of trailing sign and also 40 replacement characters to be stored in the RDOD register 730-154 after being switched through the ZEWR switch 730-180 and the MOD switch 730-152.

Each of the above store operations is enabled by the DUCIVID 303 signal set by a firmware command to load the word in the RDOD register 730-154 on a first firmware cycle and to write the word in cache 750 on a second firmware cycle. The first and second firmware cycles are repeated until 45 all of the words containing operand 3 information are transferred to cache 750.

The sequence of steps for loading cache 750 for a negative shift count, i. e., the RDSCO output signal is equal to ONE, is the same as for the positive shift count with the exception the binary value in the RRWC register 730-88 at each step is one more than its corresponding value for the positive shift count. 50 As a part of the long operand store operation the firmware initiates a DUCMD 304 "Cheek Zero/Overflow- operation. Operand 3 information is sent from the execution unit 714 to the decimal unit 730 under firmware control a word at a time starting with the least significant word. A DUCIVID 304 command is issued for each significant word to be checked and the word is put into the RCHO register 720-10, Figure 2, at the same time. The last DUCIVID 304 command is issued by the firmware for the most significant word of the long operand. The decimal unit 730 scans each word received on the cycle following the DUCIVID 304 command which is marked by the FCZO flag being set from the least significant word to most significant word, counting the number of digits to the right of, and including the most significant digit. This count is stored in the RWPC register 730-84, RLZC1 register 730-96, and RI-M2 730-98. The output of these registers is available to the firmware in 60 response to a DUCM.D 311 "Put Operand Word Count into RDOD- command.

Effective digit logic 730-81, Figure 7, examines the resultant operand word RCHU 435, received from the character unit 730. The resultant operand word was generated in the execution unit 714 and is the result of the decimal numeric operation performed on operand 1 and operand 2.

The negated signals RCHU 4-35 are applied to the inputs of NAND gates 812 through 81- 65 26 GB 2 114 785 A 26 16. Decimal digit 0!sjignals RCHU 4-7 are applied to the input of NAND gate 81-2. Decimal digit 1 signals RCHU 8-11 are applied to the input of NAND gate 81-4. In a similar manner the decimal digit 2-7 signals are applied to the inputs of NAND gates 81-6 through 81-16.

If the inputs to NAND gate 81-2 indicate that digit position 0 signals RCHU 4-7 indicates a digit which is not zero, then the DGZ-5 output signal of NAND gate 81-2, at logical ONE, is applied to the input of a NAND gate 81-42. The output signal EDC-0 at logical ONE indicates that the word contains eight significant digits. The output signal DGM, at logical ZERO, is applied to the inputs of NAND gates 81-44, 81-46 and 81-48 thereby forcing the output signals EDC1-3 to logical ZERO.

If the digit 0 signal RCHU 4-7 indicates a decimal zero, then the output of NAND gate 81-42 is10 disabled and the output of NAND gates 81-44, 81-46 and 81-48, which indicates the position of the most significant digit of the operand word, is enabled. Assume that the most significant digit is in position 5 of the 8 position operand word positions 0 through 7. Therefore the DGM output of NAND gate 81-12 is at logical ZERO and the DGZ 0-4 outputs of NAND gates 81-2, 81-4, 81-6, 81-8 and 8 1 -10 are at logical ONE.

Digit 5 signal, logical ZERO, is applied to the input of NAND gates 81-22 and 81-32. The output signals DZR56 and EZ-R5/7 at logical ONE are appliedto the inputs of NAND gates 81-28, and 81-40 respectively. The other inputs, signals M 34 and DGZ4 at logical ONE are applied to the other inputs of NAND gates 81-28 and 81-40 respectively. The output signal DZR3/6 at logical ONE is applied to the input of a NAND gate 81-36. The other input, signal M '12 at logical ONE forces the output signal M1 -4 of NAND gate 8-34 to logical ZERO, thereby forcing the output o NAND gate 81-44, signal EDC-1 to logical ZERO. The output of NAND gate 81-36, signal DZR116 is at logical ZERO since the input signal DZR34 of NAND gate 81-28 is at logical ONE. This forces the output signal DZR1/6 to logical ONE forcing the output of NAND gate 81-46, signal EDC-2 to logical ONE.

The output of NAND gate 81-40 signal DZR4/7 at logical ZERO is applied to the input of NAND gate 81-24. The output signal DZR3/7 at logical ONE is applied to the inputs of a NAND gate 8 1 - 30. The other input signal DGZ-2 at logical ONE forces the output signal DZR277 to logical ZERO thereby forcing the output of a NAND gate 81-38, signal DZR1/7 to logical ONE. This forces the output of NAND gate 81-48, signal EDC-3 to logical ONE.

Signals EDC-1, at logical ZERO, EDC-2 and EDC-3 at logical ONE, indicate that there are 3 significant digits in the operand word.

The least significant word is received by the decimal unit 730 over the RCHU 4-35 signal bus into the buffer 730-168. The negated output signals RCHU 4-35 are applied to the effective digit logic 730-81. The effective digit logic 730-81 output signals EDC 0-3 are applied to the input of 35 the ZEDC switch 730-82. The ZEDC 1-3 output signals represent a binary count of the significant digits in the word starting from the most significant digits and counting to and including the low order digits position 7. The ZEDC 0 output signal at a logical ONE, indicating that the most significant position of the word, position zero, contains a decimal digit which is not a zero, is loaded into the AEDC adder 730-96 after the first word is received and the RWPC register 730- 84 is incremented by ONE 40 each time a subsequent word is received from the execution unit 714 by control signals [ENRWPC, [CNTUP-RWPC and [LDRWPC being applied to the input terminals of the RWPC register 730-84.

Boolean expressions for control signals I-DRWPC which loads the RWPC register 730-84 and ENMPC which enables the output of t e register are as follows:

[ENRWPC=((DUCMD 305+FU0)+FCRD. DUCMD 314. DUCMD 205) [LDRWPC=((DUCMD 305+FU0) (FCRD+DUCMD 314 +DUCIVID 20b The RWPC 0-3 output signals are applied to one terminal of an AEDC adder 730-86. The ZEDCO signal is applied to another terminal of the AEDC adder 0-3 whose output is switched through the ZEDD switch 730-94 and stored in positions 0-3 of RUC1 register 730- 96 and RUC2 register 730-98 whenever the received word has a non zero decimal digit stored. The ZEDC 1-3 50 binary output signals of the ZEDC switch 730-82 which indicates the number of significant digits in the-word are stored in positions 4-6 of the RUC1 register 730-96 and the RUC2 register 730 98. The register outputs signals RUC1 0-6 and RLX2 0-6 are applied to the MC switch 730-76, whose output is available to the firmware through position 3 of the Z11) switch 730-150.

The RI 7C1 and RI 7C2 registers both store the number of significant digits in operand 3. When the first word is received from the execution unit 714, assuming position 0 contains a decimal digit, not zero, the binary quantity 8 is stored in the RUC 'I and RUC2 registers. The ZEDCO signal input to the ZEDd adder 730-84 is a logical ONE. When the second word is received again assuming position 0 contains a decimal digit, then the ZECDO signal input to the ZEDC adder is at a ONE and the RMC3 signal input is at a one. This forces the ZEDC 0-3 output to a binary 2 and the quantity binary 16 is 60 stored in the RI-M 'I and RUC2 registers. Assuming the third word contains only 3 decimal digits with the most significant digit in position 5 then the ZEDC 0-3 will store a binary 011 in the RI 7C1 and RUC2 registers 730-96 and 730-98 respectively which will now have the quantity 19 stored in the registers.

i 27 GB 2 114 785 A 27 The RLZC1 -2 and RLW2-2 bits (binary 16 bit) are again set since the AEDC 0-3 output is at binary 2. The RWPC 730-84 register was incremented from binary ONE to binary TWO. The RRWC register 730-. 88 stores the adjusted length of the operand which is calculated from length and scale factor values, as designated by the descriptor. The RWPC register 730-84 stores the number of words examined by the firmware as the result of the DUCMD 304 on a long operand.

In the long operand store operation it is necessary to compare operand 3 which is the result of the operand 1 and operand 2 calculations, as it exists internally in the execution unit 714 with the operand 3 as it is to be stored in cache 750, and to do so with a simplified firmware procedure.

Initially, the firmware issues the DUCMD 303 "Store Operand Thru DW command. This command initiates the actual store sequence in the decimal unit 730. Unlike the short operand store 10 procedure, the firmware will not prepare a write address and send a write command to cache 750 until it is permitted to do so by the decimal unit 730. The decimal unit 730 makes this decision based on the information stored in the RRWC register 730-88, the RWIPC register 730-84 and the position of the most significant digit within the word when the operand is received by the decimal unit 730 from the execution unit 714 as indicated by the output of the ACPNB adder 730-50. As in the short operand 15 case the output of the ACIPR adder 730-62 is subtracted from the output of the ACPNB adder 730 in the ACIPSC adder 730-54 to generate the shift count which is stored in the RDSC register 730-58.

It should be noted that every word stored in cache 750 requires 2 firmware cycles minimum for the store operation. The address in cache 750 in which the operand word is written is sent to cache 20 750 on the first cycle and the data to cache 750 is sent on the second cycle. The firmware therefore is organized in 2 step loops, the first step generates the address and the write command and the next step passes the data through from the decimal unit 730 to cache 750. The process starts on the cycle the firmware sends the DUCMD 303 command to the decimal unit 730. The firmware examines the start write signal RRLTRD to the execution address and branch circuits 701 -1, Figure 4, for logical ONE which indicates that a write command should be generated and issued to the cache 750.

The FSWRTflag is set to indicate to the decimal unit 730 that the firmware is sending write commands to cache 750. If the start write line RRILTRID is at logical ZERO then the firmware controls the loading of the RCHO register 720-10 of the character unit 720 with words from the execution unit 714 until the most significant word is stored. This is the case where the count in the RWIPC register 730-84 would be greater than the count in the RRWC register 730-88. The RWIPC register 730-84 is decremented each time a word is placed in the RCHO register 720-10 until the count in the RWIPC register equals the count in the RRWC register if the RDSC register 730-58 indicates a positive shift or until the count in the RWPC register is less than the count in the RRWC register if the RDSC register indicates a negative shift. For a positive shift the most significant word is stored in the 35 RCHO register 720-10. For a negative shift the most significant word is stored in the RK register 730-162 and the second word is stored in the RCHO register 720-10.

For the positive shift operation, the start write line RRLTRI) is forced to logical ONE and the firmware initiates a write into cache 750 loop when the RRWC register 730- 88 count equals the RWPC register 730-86 count. This sets the FSNID flag which strobes the previous word stored in the 40 RCHO register 720-10 into the RPK register 730-162 and indicates to the firmware to load the next word into the RCHO register 720-10 from the execution unit 714 by forcing the send data signal RREQRD to logical ONE.

The boolean expressions for the start write signal RRLTRD and the send data signal RREORD for long operand store operations areas follows:- DSEND DATA=WC1PC0 ' ZTNW+ZTNSA0). DIVISEQ, FSWRT. FIVISIDRN IDSTRTWRT=FIViSEQ. DIVISIDI1GTE. RDSCO+DMSDRGTE RIDSCO+DUCIVID 303. RRWCO RREWID=FIDUACT. DSEND DATA. M CMD 202 50 DUCMD 204. DUCMD 306 RRLTRID=FIDUACT. 13STRT-WRT. DUCMD 202. DUCMD 204 DMSDRGT=(RWPC 0-3. MINUS. 1) > ffiRR-WC0. (RRWC 'I +RRWC2). RRWC3 RRWC4. R11WC5. R11WC6 55 DIVISEQ=PC 0-3. MINUS. 1) = (RRWCO. (RRWC 1 +RRWC2). RRWC3 RRWC4. RRWC5. RRWC6 DIVISI3RGT=PC 0-3. MINUS. 1) > (RR-WC0. ffiRWC1 +RRWC2). RRWC3 60 RRWC4. RRWC5. RRWC6) 28 GB 2 114 785 A 28 The boolean expressions for the count down of the RWPC register 730-84 are as follows:

[CNTDWN-RQPC=FRPK. DUCMD 303. (ZTNSAO. FCPCO +ZTNSAO)+FRPK. (FOPSTR+ DUCIVID 303. DIVISIDRGTE). A--LT. (FSWRT DMSDRGT+(ZTNSAO. FCPCO+ZTNSAO) FSWIRT. DIVISIDIRGT)) [$1RDOD=FDATA-AV+DUCMD 203 +DUCIVID 310+ DUCMD 311 +DUCIVID 309+FRM.

DUCMD 303+FR-PR. FAETT. FSWIRT The decimal unit 730 compares the RRWC 0-6 output signals with the RWPC 0- 3 output 10 signals in a comparator 730-90. The comparator output signals DIVISEQ, DIVISIDRGT and DIVISIDIRGTE condition the register and switch control 730-91 for generating the RFILTIRD and RREQRD signals and the various signals controlling the ZM switch 730-160, the RPK register 730-162, the ZPKL switch 730-166 and the ZPKIR switch 730-164. The signals also condition the status flag control logic 730-202 for setting the FSND, FSWIRT, FIVISI3RGTE and FMSEQ flags as well as decrementing 15 the FIRM register 730-88 and the RWPC register 730-84. When the number of words stored in the FIRM register 730-88 is greater than the number of words stored in the RWPC register 730-84 then the cache write flag FSWIRT is set but the FSNID flag is not set. This results in the RDOD register 73-154 outputting words containing all zeros to cache 750 and decrementing the FIRM register 730. When the comparator 730-90 indicates an equal condition, the FSND flag is set and under 20 firmware control the most significant word is sent from the execution unit 714 to the decimal unit 730 over the RCHU 4-35 signal bus thereby inputting the buffer 730-168. The buffer 730-168 output is applied to the 0 position of the ZPK switch 730-160. The most significant word is stored in the RPK register 730-162 from the ZM switch 730-164. Control logic, not shown, enables the ZPKIR switch if a data word can be assembled and sent to cache 750. In that case, the ZMR 0-31 output signals are applied to the ZDS shifter 730-156 and the word shifted by a number of digit positions equal to the binary value of the MSC 1-3 signals. Zeros are applied on the ZM 4-31 signal bus.

The MS 0-31 output signal is switched through position 0 of the Z11) switch 730-150 to position 0 of the ZSIVIR switch 730-180 if the operand comprises 4-bit characters. If the operand comprises 9- bit characters then the MS 0-31 output signal is switched through position 0 of the ZID switch 730-150 to position 1 of the MOD switch 730- 152 if the word is to be written in an odd address in cache 750 or to position 2 of the MOD switch if the word is to be written in an even address in cache 750.

Position 0 of the ZSMR switch expands the word containing 4-bit digits from 32 bits to 36 bits after which the word is switched through position 3 of the MOD switch 730- 152 to the RDOD 35 register 730-154 where it is stored and sent to cache 750 on the next cycle.

Position 2 of the MOD switch 730-152 expands words of operands to be made up of 9-bit digits by expanding the Z11) 4-19 output signals to generate the 36-bit word by adding the ACSII or EBCDIC zone characters. Position 1 of the MOD switch 730-152 expands the Z11) 20-35 output signals to the 36-bit MOD 0-35 signal bus. The MOD 0-35 output signals from position 2 of the 40 MOD switch are stored in the RDOD register 730-154 and transferred to an even cache 750 address. The position 1 outputs of the MOD switch are transferred to odd cache 750 addresses.

In the event that the comparator 730-90 output indicates that the RIRWC 06 binary count of the RRWC register 730-88 is less than the RWPC 0-3 binary count of the RWPC register 730-84 then data words are neither received from the execution unit 714 nor sent to cache 750 by the decimal 45 unit, and the RWPC register 730-88 counts down until the output of the comparator 730-90 indicates that the RWPC 0-3 binary count equals the RRWC 0-6 binary count. This sets the FMSEQ and FSWIRT flags and the data words are clocked into the RDOD register 730-154 and transferred to cache 750.

Operands having 9-bit characters transfer 2 words to cache 750 for every word received from the 50 execution unit 714 during normal operation. The word received from the execution unit 714 has up to eight decimal digits of 4-bits each and is expanded to 2 words, each containing up to 4 decimal digits of 9-bits each. The FCPCO flag cycling on and off controls the transferring of words to odd addresses and to even addresses in cache 750.

Cycle delay The processing of short operands is speeded up by predicting, as the processing of the instruction is starting, the number of words sent from the decimal unit 730 to the execution unit 714 and the number of cycles between the time the first read command is sent to the cache 750 and the first data word is sent to the execution unit 714. The number of words and cycles of delay are calculated in the decimal unit 730 and sensed by the firmware in the execution control unit 701. The decimal unit 730 60 output signals, PK-VCTR 0-3, Figure 4, are applied to the execution address and branch circuits 701-1 and cause the firmware to branch to a particular address in the execution control store 701 4 which results in the firmware executing a subroutine to process the operand. The particular r Q 29 GB 2 114-785 A 29 subroutine selected is designed to process the exact number of words of the operand with the exact number of cycles of delay thereby processing the operand with minimum of number of microwords.

The calculation for the number of delay cycles is a function of the type of data, that is, whether the incoming operand is made up of 4-bit or 9-bit characters, the location of the most significant character in the operand coming from cache 750 and the location of the most significant digit in the operand being transferred to the execution unit 714. As an example, assume an 8-decimal digit operand made up of 9-bit characters with a leading sign. Also assume the sign was in the third character position of the first word of the operand. The second word from cache 750 contains 4 decimal characters and the third word from cache 750 contains 4-decimal characters. The decimal unit 730 would not load any decimal digits upon receiving the first word since the first word only contained 10 the sign. Four decimal digits were received from the second word, still not enough to fill the RDOD 730-154 register. Four decimal digits were received from the third word and the RDOD register was loaded with 8-decimal digits.

This load operation took 3 cycles to assemble and 0-3 transfer the word to the execution unit 714. The PK-VCTR 0-3 signals lines would indicate a one word transfer with a 2 cycle delay to the 15 firmware. The firmware by using the information indicating the number of words transferred and the number of cycles of delay performs the control of transferring data words from one register to another on a specific cycle rather than to halt or loop waiting for the data word.

The delays are a function of the data type, 4-bit or 9-bit decimal characters as indicated by the condition of the output of the ZTNSA switch 730-36 and the ZTNSB switch 730-34, ZTNSAO or 20 ZMSBO signals. The AWNB adder 730-50 gives as an output the digit position of the most significant digit of the word received from cache 750. The AMF adder 730- 52 gives the difference in positioning between the first character position for the high order digit in the first word from cache 750 and the digit position of the most significant digit as it is transferred to the execution unit 714. The output of the ZCPA switch 730-44 signal SCIPA0 identifies the word from cache 750 as being from an odd or even word address.

The Boolean equations for the number of words and cycle delay calculations are readily interpreted into functional hardware by one of ordinary skill in the art and are as follows:

P K-MR 0=0 P K-MR 1=TDBO P K-MR 2=MB 1 P K-MR 3=ARM6 TDBO=[(ZTNSAO.FDUACT.FRDP1+ZTNSBO.FRDPl) (ACPDFO. ZCP70-+ACPDFO. WIPA0. ACIPW1)l TDB1=[(ZTNSAO. FDUACT. FR13P11+MSBO. FRDIP11) (ACPDFO) +(ZTNSAY. FDUACT. FRDP 1 ±ZT-N-S-O. FRDP 1) RAMM. WIPA0)+(AMFO. WIPA&F (,-CPNBO.ACPNB1.ACPNB2.ACPNB3+ ACIPW1. AWNBO. AWNB1)+AMFO. WIPA0. ACIPI3F121 The PK-VCTR 1 signal forced to binary ONE indicates a 2 cycle delay. The K-VUR 2 signal 40 forced to binary ONE indicates a 1 cycle delay. The PK-VCTR 3 signal forced to binary ZERO indicates that 1 data word will be transferred to the execution unit 714 from the decimal unit. The PK-VCTR 3 signal forced to binary ONE indicates that 2 data words will be transferred to the execution unit 714.

For the PK-VCTR 1 calculation the ZTNSAO. FDUACT. FRDP 1 Boolean expression indicates a 9 bit operand 1 word from cache 750. The MSBO. FRDP 1 indicates a 9-bit operand 2 word from cache 750. The AWDFO. AWA0 expression indicates a left shift Louah the shifter 730-156 of the word from an even cache 750 address. The ACIPWRO. WIPA0. ZCPDFl expression indicates a left shift of from 1-3 decimal digits of a word from an odd cache 750 address.

For the PK-VCTR 2 calculation ZTNSAO. FDUACT. FRDP T. ACIPWO indicates a 4-bit operand 1 word from cache 750 requiring a left shift throuqh the shifter 730-156. MSBO. FRDP l. AWDFO 50 indicates a 4-bit operand 2 word requiring a left shift. ZTIMSA0. FDUACT. FRDP 1 +ZTNSBO. FRDP 1 indicates a 9-bit operand 1 word and a 9-bit operand 2 word.

ACIPM. ZCPAO+'ZCPDFO.-ZCPAO indicates either a zero shift or a right shift of the-word from the even cache address. ACPNbo. AWNB 'I. ACPN92. AWNB3 indicates that the high order decimal digit is in position 4 of the 4-bit character word or position zero of the 9-bit character word 55 from odd cache address. AMFI1.;kC-PNBO. AWNB1 indicates that the high order decimal digit received from cache 750 is in locations 1-3 and the shift count is less than 4 digits. ACIPM. WIPA0 ACPDFl indicates a left shift of greater than 3 digit positions from the odd cache address word. Note that the AWDFZ signals at binary ONE indicates that the adder 730-52 is set a binary ZERO. For the PK-VCTR 3 calculation, ARWC6 indicates a one word transfer from the decimal unit 730 and the 60 execution unit 714 when at binary ZERO and a two word transfer when at binary ONE.

Decimal unit 730-Figure 3-rewrite operation Operand 3 may start and end in character positions within the most significant word and the least GB 2 114 785 A 30 significant word. It may be necessary to retain the information stored in the most and least significant words of operand 3 that are not part of operand 3. In this case, the firmware initiates a DUCMD 306 ---LoadRewrite Data- command in the decimal unit 730 to load the most significant word into the REWR2 register of register bank 730-177 through the Z131 0-35 bus from cache 750, the RDID register 730-158 and the RDID buffer 730-176. The firmware initiates a second DUCMD 306 to 5 load the least significant word in the REWR3 register of the REWR 0-3 register bank 730-177.

When the firmware initiates a DUCMD 303---StoreOperand Through Decimal Unif' command the most significant word appears on the Z11) 0-35 signal bus. Assuming 4-bit decimal characters for the operand the RCP2 register of register bank 730-42 stores the starting character position of the operand 3. Since this is a descriptor 3 operation the RCP2 position of switch 730-44 is selected and 10 the ZCPA 0-3 output signal is applied to a ZRUMP switch 730-148. Position 1 of the ZRUMP switch is activated and the ZRUMP 0-2 output signal is applied to a REWUM shifter 730-149. The REWUM 0-7 output signals are applied to control [1 ZSMR logic 730-142 and control [2ZSMR 0 7 output signals select the digit positions of the ZSIVIR switch that will be selected. For example, for processing the most significant word of the 4-bit digit operand, digit positions in position 0 of the ZSIVIR 15 switch 730-180 would be selected for the operand digit data. The sign position in position 1 of the ZSIVIR switch 730-180 would be selected if the operand had a leading sign and the digit positions to the left of the operand would be selected in position 3 of the ZSIVIR switch for the rewrite data. The REWUM 0-7 signal output of the shifter 730-149 is a zero for those digit positions requiring write data. The ZSIVIR 0-35 output bus is switched through position 0 of the MOD switch 730-154 to 20 the RDOD register 730-154.

If the operand contains 9-bit decimal digits then the [1ZSIVIR 0, 2, 4 and 6 logic signals and [2ZSMRO,2,4and6 logic signals are applied to the unpack MOD logic 730-184. The [MOD 0-3 and [MOD 0-3 output signals enable the rewrite and leading sign digit positions of switch position 3 and the operand decimal digit positions of either position 1 or position 2 of the MOD switch 25 730-152.

During the load operation for a 2 descriptor operation the most significant word of operand 2 which could contain rewrite information is written into the REWRO register of the register bank 730 177 and all subsequent words are written into the REWR1 register replacing the previous word. This results in the most significant word of operand 2 stored in the REWRO register and the least significant 30 word of operand 2 stored in the REWR 'I register. The loading of these registers into the RDOD register 730-154 is as described supra.

The REWR register bank 730-177 is enabled by the control signal [$REWR. The boolean expression is [$REWR=(FDID+FLDREWRH).

Control signal [WRREWR1 is applied to terminal 1 and status flag FIDREWRI-1 is applied to 35 terminal 2 of the register select input terminals to select one of four registers REWR 0-3.. The boolean expression control signal WRREWFI1 is:

[WRREWR 1 =FOP2LD. FOP217+FI-DREWRH - FREWR The output of registers REWR 0-3 is selected through the ZEWR switch 730- 178. Signal [1 ZEWR is applied to output select terminal 1 and status flag FREWR is applied to the output select 40 terminal 2 of ZEWR switch 730-17 8. The boolean expression for control signal [1 ZEWR is:

[1ZEWR=(FREWR. FREWR2. FFOSD+FOP2S. FFOSI). FREWR).

Decimal unit 730-Figure 3-rounding constant Two DUCMD 309 "Put the Rounding Constant into RDOW commands are initiated by the firmware. For short operands the rounding constant is sent to the execution unit 714 in response to the 45 first DUCMD 309 if the constant is to be inserted in the least significant word. The rounding constant is sent to the execution unit in response to the second DUCMD 309 if the constant is to be inserted in the most significant word. For either case, a word of all zeros is sent to the execution unit for the other DUCMD 309 command. The other rounding constant, binary 5, is added to the position to the right of the scale factor pointer (decimal point). The rounding constant is stored in bit positions 4-7 of switch 50 position 3 of the ZM switch 730-160.

The ATIVIP adder 730-30 subtracts a ONE from the operand 3 scale factor stored in the RSF2 register of register bank 730-4 and is applied to the ATIVIP adder 730-20 through the ZAS1713 switch 730-28. If the ATMP6 output signal is a ZERO then the rounding constant is applied to the least significant word in response to the DUCMD 309 command. If the ATIVIP6 output signal is a 55 ONE then the rounding constant is applied to the most significant word in response to the second DUCMD 309 command.

The ATIVIP 7-9 output signals are inverted by inverter 730-147. The ATM 79 output signals are selected by the MSC switch 732 and provide the binary shift count to the shifter 730 156.

The ZPI(R switch 730-164 is enabled in response to the first DUCMD 309 command if the rounding character is added to the least significant word and enabled in response to the second DUCMD 309 command if the rounding character is added to the most significant word. In either case the binary 5 output from position 3 of the ZM 730-160 switch is transferred to the execution unit 1 31 GB 2 114 785 A 31 714 through the Z switch 730-164, the MS shifter 730-156, position 0 of the ZID switch 730-150, position 0 of MOD switch 730-152 and the RDOD register 730-154.

In the long operand store operation the decimal unit 730 responds to the first DUCIVID 309 command with a pointer to the word in scratchpad to which the rounding constant is added and responds to the second DUCIVID 309 command with the rounding constant. The ATIVIP 0-6 output signals which indicate the word to which the rounding constant is added are selected through position 3 of the MC switch 730-76, position 3 of the Z11) switch 730-156, position 0 of the MOD switch 730, the RDOD register 730-154 to the execution unit 714. The rounding constant, binary 5, is transferred to the execution unit 714 during the second DUCIVID 309 operation as in the short operandabove.

Sign extraction As each operand is received by the decimal unit 730 during the load operation the sign character is examined if it is not an overpunched sign character. The decimal unit 730 verifies that it is a legal sign character..

An RCPS 0-2 register 730-126 stores the character location within the word of the sign character. A ZCPS switch 730-124 selects the position of the sign character. The ZCPS switch position 0 identifies the leading sign position for 9 bit character operands. Switch position 1 identifies the leading sign position for 4-bit character operands. Switch position 2 identifies the trailing sign position for 9-bit character operands. Switch position 3 identifies the trailing sign position for 4-bit operands.

The RCPS 0-1 output signals select the position of a ZCH switch 730-170 that could contain the sign character. No attempt is made to select the trailing or leading vord of the operand in the ZCH switch 730-170. An operand word received from cache 750 over the W1 0-35 signal bus is stored in the RDI D register 730-158 and is applied to the ZCH switch 730-170. The ZCH 1-8 output signal is applied to a ZCHL switch 730-172 and to sign extraction logic 730-174. Position 1 of the 25 ZCHL switch is selected for 9-bit operands and 4-bit operands having an odd character pointer.

The sign extraction logic 730-174 selects either the sign character from the trailing word or from the leading word. If the sign character is coded as an illegal character then a SET ILLEGAL logic signal forces a fault indication for the software. If the sign character is coded as a correct sign then the SET SIGN logic signal sets an indication for the software. The ZCH 1-8 output signals to the sign 30 extraction logic indicate 8-bit E13CIDIC sign characters. The ZCH 1-8 output signals to the ZCHL switch indicate 4-bit sign characters in the lower half of the 9-bit character (bit position 4-13) position for 9-bit character operands. For 4-bit operand words, even pointers indicate the left 4-bits (bit positions 1-4) and odd pointers indicate the right 4-bits (bit positions 5-8), Control signals [1 ZCPS and [2WPS are applied to the terminals 1 and 2 select inputs of ZCPS 35 switch 730-124. The boolean expressions are..

[1ZCPS=(ZTNSAO. FIDUACT. FRIDP1 +ZTNSBO. FRID121) [2ZCPS=(ZTNSA1. ZTNSA2. FIDUACT. FRDP 1 + ZTNSB1.ZTNSB2.FRDPl) The RCPS register is enabled by a [SRCPS control signal whose boolean expression is:

[$RCPS=(FIDUACT. FRIDPl)+SFOP2LID) Overpunch digit correction-Figure 3 Operands made up of words having 9-bit characters may have separate signs in either a leading or trailing character position or the operand may have a sign included in the decimal digit code in a single character position.This requires that a correction be made to the decimal digit to include the 45 overpunched sign. Assume that operand 1 requires an overpunched sign correction. An ROP 1 logic signal is sent from the control store 704-2 to the decode logic 730-38. If the ZTNSA 0-2 output signal from the RTNS2 register of register bank 730-32 and the ZTNSA switch 730-36 is coded to a binary 000 or 011 indicating 9-bit characters with leading sign or trailing sign, a D1 EQ0VI logic signal output of decode logic 730-38 is forced high. The D 1 EGOVI? logic signal selects the 1 position 50 of a ZSSC switch 730-108 for a trailing sign operand. The 0 position of the ZSSC switch is selected for the leading sign. The RLIVIP 4-6 signals are coded to point to the character position of the leading sign and the RTMP 4-6 signals are coded to point to the character position of the tr ign.

The ZSSC 0-2 shift count signals are applied to a shifter 730-145 to shift a DBITT logic signal the number of bits specified by the ZSSC 0-2 count. The DBITT logic signal is forced to a ZERO for the 55 overpunched sign operations during the cycle in which the most significant word or the least significant word is read from cache 750 for the leading sign or trailing sign correction respectively. The shifter 730-145 output signals WRIDGM 0-7 are applied to the Z11) switch control logic 730-188 to select position 2 of the Z11) switch for the character position that is indicated by the one signal of the WRIDGM 0-7 signals that is at a ZERO which points to the overpunched sign position.

The RSGN register 730-134 is-loaded with the corrected overpunched sign character for operand 1 under firmware control. The- REXP register 730138 is loaded with the corrected overpunched sign character for operand 1 under firmware control. A ZUR-DU switch 730-136 selects 32 GB 2 114 785 A 32 the FISGN 5-8 output signals for the operand 1 overpunched sign correction character. The ZCR13G 0-3 signals are inverted by an inverter 730-186 and are applied to position 2 of the Z11) switch 730-150. When the word to which the corrected overpunched sign is added is received from cache 750, it is switched through the decimal unit 730 to be stored in the RDOD register 730-154. The character in the sign position is replaced by the ZCR13G 0-3 corrected overpunched sign character.

The boolean expression for the DBITT signal is:

DB"=(FOP 1 LD. D1 EQOVP. (ZTNSA1. iPF-DO+ZTNSA(1) 13MPEQ)+FOP21-1). D2EGOVP. RTNW. FFDO +ZTNSA0). DIVIPEM where DMPEQ is at logical one when the contents of the RLIVIP register 730-102 equals the contents 1 of the RTMP register 730-100.

The above equation indicates that the DBITT- signal is set to logical ZERO when operand 1 or operand 2 requires an overpunched sign correction during the load operation. E-NSA1. T-F-DU indicates a leading overpunched sign and ZTNSA1. DIVIPEO, indicates a trailing overpunched sign.

D 1 EGOVP=55- -ITX. ROP 1 2AT-NSA0) D2EGOVP=13BIT2. ROP 1 -ZT17S-BO) During the store operation the sign character is placed in the RSGN register 730-134 and inserted in the operand word through position 1 of the ZSMR switch 730-180 as previously described.

Decimal unit 730-Figure 3-Load STC Mask into RDOD The firmware initiates a DUCMD 203 Load STC Mask into RDOD command during the Store Character in Accumulator and Quotient Register Instructions (STCA and STCQ). The decimal unit 730 receives the RCHU 30-35 output signals from the character unit 720 which are applied to position 1 of the Z11) switch 730-150 through the buffer 730-168. Each of the RCHU 30-35 output signals at a ONE results in the corresponding 6 bits of position 1 of the ZID switch 730-150 being forced to a 25 ONE. These groups of 6 bits are stored in the RDOD register 730-154 through the ZDOD switch 730-152.

Figure 4 shows the relationship between the decimal unit 730 hardware and the firmware in the execution control store 701-2. The execution address and branch circuits 701-1 send the control store address locations ZECSA 0-12 to the execution control store 701-2. The microword at that 30 address location is read out and bit positions RSCR 88, 89, 94-97 input a decimal unit 730 decode logic 730-204 which consists of conventional decode logic circuitry. Table 1 shows the RSCR 88, 89, 94-97 bit configurations for the respective DUCMD 200-206, 300-315 commands.

The DUCMD 200-206 300-315 commands input a status flag control logic 730202. This unit is made up of conventional flops set and reset in a conventional manner.

The 1 cycle control state circuits 704-102 described in the aforementioned British Patent 2,008,817 generates the FPOA [POP HOLDN and the [H OLDE signals to time the decimal unit 730 to the pipeline operations of the control unit 704. These signals also input the decimal unit control logic 730-200 and the status flag control logic 730-202 whose output inputs a decimal unit control logic 730-200 as well as inputting the status flag control logic 730-202. Also applied to the decimal unit 40 control logic 730-200 are the DUCMD outputs of the decimal unit decode logic 730-204 and the descriptor information received from control unit 704-1 over signal lines RSIR 21-35 and ASFA 33-36 in the registers shown in Figure 3.

Operands stored in cache 750 are transferred to the operand processing unit 730-206 a word at a time over signal lines ZDI 0-35. The operand processing unit 730-206 is conditioned by the 45 descriptor information, the status flag signals and the register and switch control signals, receiving the operand word from cache 750 to strip non-operand an non-decimal digit characters from the word, converting the word into 4-bit decimal digits, aligning the four 4-bit decimal digits into words of up to eight 4-bit decimal digits and transferring the completed word to the execution unit 714 over signal lines RDOD 0-35. Outputting the logic 730-200 unit are the PK-VCTR 0-3 signals and the FIRLTRI), RREQRD, ADSZ and ZAMO conditional branch signals which generate branch addresses in the execution address and branch circuits 701-1.

A clock signal times the relationships between the logic units of Figure 4.

Figure 4 shows the flow of logic through the system. Where the portions of the logic blocks of Figure 4 relate to the inventions, they are shown in further detail in Figure 3.

Figure 5 shows two typical instructions processed through the decimal unit 730. The AD2D instruction-add using two decimal operands, adds the operand from the address location and in the format defined by descriptor 1 to the operand from the address location and in the format defined by descriptor 2 and places the resulting operand in the format and address location defined by descriptor 2.

The AD3D instructions-add using 3 decimal operands adds the operand from the address location and in the format defined by descriptor 1 to the operand from the address location and in the I- 19 Q 33 GB 2 114 785 A 33 format defined by descriptor 2 and places the resulting operand in the format and address locations defined by descriptor 3. The instruction word is made up of 36 bit positions 00-35.

The instruction format includes a P bit defining E13C131C data when a ZERO, and ASCII 1 data when a ONE.

Fields MFl, MF2 and MF3 describe the address modifications to be performed on descriptor 1, 2 5 and 3 respectively.

The T bit enables the truncation fault.

The RD bit enables the rounding operation.

The OP CODE specifies the operation to be performed. In Figure 5 the OP CODE 202-1 specifies the AD2D instruction and OP CODE 222-1 specifies the AD3D instruction.

1 is the interrupt inhibit bit.

For the descriptor formats, Y1, Y2 and Y3 are the main memory word locations of the most significant character of the operand specified by descriptors 1, 2 and 3 respectively.

The 0/E bit identifies the main memory word address as being either an odd,address or an even address.

M 1, M2 and M3 are codes that define the position of the most significant character within the main memory word of the operand specified by descriptors 1, 2 and 3 respectively. Codes depend on the data type as shown below:

Codes Character Numbers 9 bit characters 000 0 20 1 2 3 4 bit characters 000 0 001 1 25 2 011 3 4 101 5 110 6 30 ill 7 TW, TN2 and TN3 are codes that define the numeric data type for descriptors 1, 2 and 3 respectively. A ZERO specifies 9-bit data and a ONE specifies 4-bit data.

The S 1, S2 and S3 fields identify the sign and decimal type of descriptor 1, 2 and 3 respectively.

Unpacked data Packed data M= 1 TN=0 OW allowed orOVPnotallowed S 00 LS, OVP, scaled 01 LS, scaled 10 TS, scaled 11 TS, OW, scaled LS=Leading TS=Trailing Sign OVI=Overpunched sign S 00 Floating point, LS 01 LS scaled 10 TS scaled 11 No signs, scaled SF 1, SF2 and SF3 specify the scale factors of descriptors 1, 2 and 3 respectively. The decimal 45 point is located after the least significant digit. A positive scale factor moves the decimal point that many positions to the right. A negative scale factor moves the decimal point that many positions to the left.

N 1, N2 and N3 are the number of characters in the operand defined by descriptors 1, 2 and 3 respectively. N1, N2 and N3 maybe 4-bit codes which specify registers that contain the length of the 50 respective operand. However, for describing the invention N11, N2 and N3 are the number of characters in the operand.

Decimal unit 730-Figure 3-vector branch data Referring to Figure 3, the decimal unit control logic 730-20 generates control signals [1 PKVCTR, [2MVCTR and [41PKVCTR in response to decimal unit 730 DUCIVID command signals as 55 described supra. The vector branch logic 730-15 has applied to it signals indicative of the characteristics of the operand. The output signals of decode logic 730-38 and 730-40 which are described infra define the operand as a floating point or overpunched sign and as a scaled operand if made up of 4-bit or 9-bit decimal characters. The ZTNSA1 and ZTNSB 'I signals indicate an operand 34 GB 2 114 785 A 34 with a trailing sign if at logical ONE and an operand with a leading sign if a logical ZERO. The ALNS 3 and the ALNDA 0-3 and the ALNDB 0-3 signals identify the operand as having an adjusted length of greater than 63 decimal digits or a length of less than or equal to 63 decimal digits. The detailed logic is shown in Figure 8.

The vector branch logic 730-15 output signals PK-WTFI 0-3 are applied to the execution 5 address and branch circuits 701 -1 in response to the [1 KVCTR, [2MVCTR and [4PKVCTR control signals to indicate to the execution control store 701-2, Figure 1, the next microword to be processed by the system.

Referring to Figure 8, a PK-VCTR switch 15-72 a-d generates vector branch signals PK-VCTR 0-3 in response to microword signals which are applied to the decimal unit 730. The microword signals generate DUCMD command signals, which when combined with status flag signals generate control signals [1 PKVCTR, [2PKVCTR and [4MCTR. These control signals are applied to the 1, 2 and 4 input select terminals of switch 15-72 and select 1 of 8 input signals from each of 4 sections of the switch 15-72 a-d.

During the processing of non-decimal numeric instructions the decimal unit 730 is inoperative 15 thereby activating input terminal 0 of switch 15-72 a-d.

The type length vector signals are applied to input terminal 1 of switch 15-72 a-d. The DSHORT signal is applied to input terminal 1 of switch 15-72 a. If the ALNS adder 730-24 indicates the adjusted length of the operand as greater than or equal to binary 16 then one or more of the input signals ALNS 3-5 to AND/NAND gates 15-32, 15-34 and 15-36 respectively is at 20 logical ONE. One or more of the output signals at logical ZERO is applied to the inputs of a AND/NAND gate 15-38. The output signal ALNSGTE 16 is applied to the input of an AND/NAND gate 15-50. If this is not a decimal multiply/divide instruction then the output signal DI-NSCI-DGTE 16 is forced to logical ZERO. This signal, applied to the input of n AND/NAND gate 15-74 forces the DLONG output signal to logical zero. Signals Al-NDA1, Al-NDA2, Al-ND131 and ALN13132 are applied to the inputs of 25 AND/NAND gates 15-40, 15-42, 15-44 and 15-46 respectively. Logical ONE is applied to the other input terminals. The output signals of AND/NAND gates 15-40 and 15- 42 are applied to the inputs of an AND/NAND gate 15-52 and the output signals of AND/NAND gates 15-44 and 15-46 are applied to the inputs of an AND/NAND gate 15-64. The output signals AI-NDAGTE 16 and Al-ND13GTE 19 at logical ONE indicate the length of operands 1 and 2 are less than 16 decimal digits. If 30 the operands are not floating point operands and the adjusted length including scale factor adjustment are less than 16 decimal digits then signal DLONG, the output of AND/NAND g te 15-74, at logical ONE indicates that both operands are processed as short operan s. The DLONG signal is applied to the input of an AND/NAND gate 15-56. The output signal DSHORT, at logical ONE, indicates that the operand being processed is a long operand. Signal D1 2EQOVP is applied to the other input of 35 AND/NAND gate 15-56 and when at logical ONE indicates that neither operand 1 nor operand 2 has an overpunched sign character which is the requirement for a short operand.

The DSHORT signal at logical ONE indicating a short operand is applied to the input of a AND/NAND gate 15-58. Signal ZTNSA5 at logical ONE indicating a 9-bit per character operand is applied to the other input of NAND gate 15-58. The output signal DSHORT 9 at logical ZERO is applied to an input of an AND/NAND gate 15-62. The output signal DI- NGORST 9 at logical ONE is applied to the input terminal 1 of switch 15-72 b indicating a short 9- bit per character operand.

Logical ZERO is applied to input terminal 1 of switches 15-72 c and d.

Signals TD130 and TDB 1 are applied to input terminals 2 and 3 of switch 15-72 b and 15-72 c respectively. The boolean expressions are described supra and indicate the number of cycles of delay 45 between the cycle on which the read request is made of cache 750 and a complete word is received by the execution unit 714. The ARWC adder 730-60 signal ARWC 6 is applied to input terminals 2 and 3 of switch 15-72 d and indicates a one word operand if at logical ZERO and a two word operand if at logical ONE.

Input terminals 4 and 6 of switch 15-72 a-d are selected for the descriptor 1 vector and store 50 vector operations, respectively. Signal ROP-1 from control store 704-2 at logical ONE indicating an overpunched sign operand is applied to an input of an AND/NAND gate 15-2. The ZTNSAU signal indicating a 9-bit per character operand when at logical ONE, is applied to the other input of AND/NAND gate 15-2. Either input at logical ZERO forces the signal D1 NEW 9 which is applied to an input of an AND/NAND gate 15-14, to logical ONE. SignalsTT-NSA1 and ZTNSA2, at logical ONE, are 55 applied to the other inputs of AND/NAND gate 15-14. Output signal D1 EWLP at logical ZERO, indicating a floating point operand, is applied to the input of an AND/NAND gate 15-64. The output signal D 1 FLPORTSO at logical ONE is forced to logica 1 ONE indicating a floating point operand.

If signals ROP-1 and ZTNSAO are at logical ONE, the D1 NEW9 signal output of AND/NAND gate 15-2 is at logical ONE. If signal DBITX is at logical ONE then the output signal D 'I EQ0VI of an 60 AND/NAND gate 15-22 is at logical ZERO. This forces the output, signal D1 2EQOVP, of an AND/NAND gate 15-1219 loatcal ONE. If signal ZTNSA1 is at logical ONE indicating a trailing sign then the output signal D1 EOTSO of a NAND gate 15-26 at logical ZERO forces the D1 FLPORTSO r GB 2 114 785 A 35 signal output of AND/NAND gate 15-64 to logical ONE. Signal D1 FLPORTSO at logical ONE is applied to input terminals 4 and 6 of switch 15-72 b indicating a floating point or overpunched trailing sign operand.

Signal D 'I E0OW, the output of AND/NAND gate 15-22 is applied to input terminals 4 and 6 of 5 switch 15-72 a indicating an overpunched sign operand.

Signal DBITX is at logical ONE if signals ZTNSA1 and ZTNSA2 at logical ONE are applied to an AND/NAN2_9ate 15---4indicating an operand with no sign or an overpunched trailing sign or signals ZTNSAO, ZTNSA1 and ZTNSA2 are applied to an AND/NAND gate 15-6 indicating a 9-bit per character floating point or overpunched leading sign operand. Output signal D1 EWLP 9 of'an AND/NAND gate 15-6 at logical ZERO forces signal 5-BITX, the output of AND/NAND GATE 15-16 10 to logical ONE.

Logical ZER0s are selected from terminals 4 and 6 of switches 15-72 c and d. The firmware generates a result equals zero and an overflow check during the store vector operation. The descriptor 2 vector selects the input terminal 5 of switch 15-72 a-d. Signal D2EQ0VI is applied to terminal 5 of switch 15-72 a and when at logical ONE indicates an operand with an overpunched sign. The 15 D2EQOVP signal is generated in a similar manner as the D 1 EGOW signal which indicates an operand 1 with an overpunched sign.

Signal D2FLPORTSO generated in a similar manner as signal D1 FLPORTSO through AND/NAND gates 15-28 and 15-66 and is applied to terminal 5 of switch 17-72 b indicating a floating point operand or an operand with an overpunched trailing sign.

Switch 15-72 c, d input terminals 5 are at logical ZERO.

The long input vector selects input terminal 7 of switch 15-72 a-d. Signals D1 EMP and D2EMP are applied to the inputs of an AND/NAND gate 15-48. The output signal D1 2EMP is applied to the inputs of AND/NAND gates 15-60 and 15-70 and when at logical ZERO, indicating a floating point operand, forces signals D1 2FI-POREL and D12FLPOROVP to logical ONE. The input 25 terminal 7 of switch 15-72 a and 15-72 b at logical ONE indicates to the firmware to execute the descriptor 1 and descriptor 2 vectors.

If signal D 'I 2EMP is at logical ONE indicating scaled operands, then signal ALNSLTE63 at logical ZERO indicating a length of less than or equal to 63 decimal digits is applied to the input of AND/NAND gates 15-60 and 15-68. The output signals D12FLPOREL at logical ONE indicates both 30 operands having a length of less than or equal to 63 decimal digits. Signal D12EQOVP is applied to the other input of AND/NAND gate 15-68. The output signal D1 20VPL63 at logical ZERO is applied to the input of AND/NAND gate 15-70. The output signal D12FLPOROVP at logical ONE indicates that both operands are scaled with an overpunched sign and the lengths are less than or equal to 63 35 decimal characters.

Signal ALNSLTE63 at logical ZERO is generated as the output of an AND/NAND gate 15-8. The input signal ALNS3 at logical ONE indicates a length of greater than 63 decimal digits. WYDV is at logical ONE since this is not a multiply/divide operation. D1 2EMP is at logical ONE since neither operand is a floating point operand.

Claims

1. A decimal unit for modifying multiple-worded decimal numeric resultant operands that were processed by a data processor execution unit for storage in a memory, comprising:

means for receiving signals indicative of each word of said resultant operands least significant word first, each word being received in response to a microword; detecting means coupled to said receiving means and responsive to said word signals for 45 generating signals indicative of decimal digit positions of said least significant word and subsequent words of said resultant operand; decoding means coupled to said detecting means, and responsive to said decimal digit signals for generating a first signal in a first state indicative of a decimal digit in a first position of said word having a value greater than decimal zero, and generating binary signals indicative of the position of the most 50 significant decimal digit of said word if said decimal digit in said first position has a value of decimal zero indicated by said first signal being in a second state; word counter means responsive to a control signal for generating signals indicative of a count of one less than the number of words of said resultant operand received by said receiving means; adder means coupled to said word counter means and to said decoding means and responsive to 55 said count signals and to said first signal for generating signals indicative of the number of effective words received by said receiving means; an effective digit count register having at least a first and a second portion, said first portion being operatively coupled to said adder means for storing signals indicative of the number of effective words, and said second portion being operatively coupled to said decoding means for storing said binary 60 signals, said register storing the number of effective digits received by said unit on a cycle said word was transferred to said receiving means.

2. A decimal unit according to Claim 1 wherein said receiving means includes a buffer for 36 GB 2 114 785 A 36 receiving said word signals of said resultant operand for generating negation output signals specifying said decimal digits of said word.

3. A decimal unit according to Claim 2 wherein said detecting means is responsive to said negation signals for generating said signals indicative of decimal digit positions having said value of decimal zero and said positions having said value greater than decimal zero.

4. A decimal unit according to Claim 3 wherein said decoding means is responsive to said decimal zero signals for selectively generating signals indicative of said decimal zero signals being leading zero signals, and being responsive to said signals having said value greater than decimal zero for generating said binary signals indicative of the position of said most significant decimal digit, said decoder means generating said first signal in said first state, or said first signal in said second state and 10 said binary signals having a value greater than binary zero, being indicative of said word containing said effective digit.

5. A decimal unit according to any preceding claim further comprising:

decode logic means for generating a first status signal on a first cycle and on subsequent cycles; status flag means coupled to said decode logic means and responsive to said status signal for 15 generating a second status signal on said second cycle and said subsequent cycles; and ANDing means coupled to said decode logic means and said status flag means for generating said control signal on said second cycle and said subsequent cycles.

6. A decimal unit according to Claim 5 wherein said adder means is responsive to said count signals on said second cycle and said subsequent cycles and is responsive to said first signal in said 20 first state on each of said cycles when said word received by said decimal unit contains said decimal digit in said first position having a value greater to decimal zero.

7. A decimal unit according to any preceding claim wherein said effective digit count register is responsive to said first signal in said first state, or to said binary signals indicating a value greater than binary zero, on each cycle said word containing said effective digit is generated.

Printed for Her Majesty's Stationery Office by the Courier Press, Leamington Spa, 1983. Published by the Patent Office, 25 Southampton Buildings, London, WC2A lAY, from which copies may be obtained

7. A decimal unit according to any preceding claim wherein said effective digit count register is responsive to said first signal in said first state or to said binary signals indicating a value greater than binary zero on each cycle said word containing said effective digit is generated.

New claims or amendments to claims filed on 18.3.83. Superseded claims 17.

New or amended claims:

1. A decimal unit for modifying multiple-worded decimal numeric resultant operands that were processed by a data processor execution unit and are supplied to the decimal unit, word by word, for 30 storage in a memory, the word containing the least significant digit being supplied first, said decimal unit comprising:

means for receiving word signals representative of individual words of a resultant operand, each word being received in response to a microword; detecting means coupled to said receiving means and responsive to said word signals for 35 generating successive signals indicative of decimal digit positions of said word containing the least significant digit and the subsequent words of said resultant operand; switch means coupled to said detecting means, and responsive to said decimal digit position signals for generating a first and a second signal on a first output, said first signal being indicative of a decimal digit in a first position of a word in said receiving means having a value greater than decimal 40 zero and said second signal being indicative that said word has the value zero, and having a second output enabled by the said second signal, said switch means providing on said second output binary signals indicative of the position of the most significant decimal digit of said word; word counter means responsive to a control signal for generating signals indicative of a count of one less than the number of words of said resultant operand received by said receiving means; adder means coupled to said word counter means and to said switch means and responsive to said count signals and to said first signal output of the switch means for generating signals indicative of the number of words containing effective digits received by said receiving means; an effective digit count register having at least a first and a second portion, said first portion being operatively coupled to said adder means for storing signals indicative of the number of words 50 containing effective digits, and said second portion being operatively coupled to said switch means for storing the binary signals on said second output, said register storing the number of effective digits received by said unit during a cycle that the respective word was transferred to said receiving means.

2. A decimal unit according to Claim 1 wherein said receiving means includes a buffer for receiving said word signals of said resultant operand, said buffer incorporating means for generating 55 negation output signals specifying said decimal digits of said word.

3. A decimal unit according to Claim 2 wherein said detecting means is responsive to said negation signals of the buffer for generating said signals indicative of decimal digit positions having said value of decimal zero and said positions having said value greater than decimal zero.

' 4. A decimal unit according to Claim 3 wherein said switch means is responsive to said decimal 60 zero signals for selectively generating signals indicative of said decimal zero signals being leading zero signals, and being responsive to said signals having said value greater than decimal zero for generating said binary signals indicative of the position in the respective word of said most significant decimal r 1 Ir )i z IQ 37 GB 2 114 785 A 37, digit, said binary signals having a value greater than binary zero being indicative of said word containing an effective digit.

5. A decimal unit according to any preceding claim further comprising:

decode logic means for generating a first status signal on a first cycle and on subsequent cycles; status flag means coupled to said decode logic means and responsive to said status signal for 5 generating a second status signal on a second cycle and subsequent cycles; and ANDing means coupled to said decode logic means and said status flag means for generating said control signal on said second cycle and the respective subsequent cycles.

6. A decimal unit according to Claim 5 wherein said adder means is responsive to said count signals on said second cycle and the respective subsequent cycles and is responsive to said first signal 10 in said first state on each of said cycles when said word received by said decimal unit contains said decimal digit in said first position having a value greater than decimal zero.