DE3000006A1 - DECIMAL UNIT - Google Patents

Description

DIPL. ING. HEINZ BARDEHLE Munich PATENT ADVOCATE

, ^k | " Yes

| " Jan fopn

File number: My reference: * 298b

Honeywell Information Systems Inc. 200 Smith Street
Waltham, Mass.
V. St. v. A.

Decimal unit

0300 2 8/0876 BAD ORIGINAL

Λ P 298b

description

The invention relates generally to microprogrammed data processing systems and, more particularly, to the Generation and storage of the leading zero number of the operand, which is to be processed in accordance with a decimal numeric computer instruction, and to the generation and storage of an effective digit number of a resulting operand during the Processing of a decimal-numeric command or »a decimal-numeric instruction»

Data processing systems process data that is stored in a memory in the form of an operand, which consists of decimal digits. The field in memory that is used to store a particular Is allocated to the operand, contains as many memory locations as required to store the operand are or would be to store the largest possible number of decimal digits for the relevant operand,

In many cases, the operand stored in the relevant field of the memory requires fewer decimal digits than is given by the maximum _e Therefore, the memory field is filled with zeros on the left-hand side of the most significant character of the operand, i.e. leading zeros. If the operand is the result of system processing of a decimal-numeric command, then it is necessary to determine the number of effective digits in the resulting operand »

When processing computer commands that request a decimal arithmetic operation, the speed is =

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^ ——- r

Operands count in order to increase the throughput or the data rate of the system or plant.

Finally, an improved arrangement is to be provided which controls the number of effective digits counts when the words of the resulting operand are included such that the throughput or the data rate of the system has increased.

The object indicated above is achieved by the invention covered in the patent claims.

According to the present invention, a decimal unit for modifying decimal-numeric operands is provided, which are processed by a micro-programmed execution unit. This decimal unit has a first signal receiving device, the signals indicative of the length of the field of each operand allowed to record. Furthermore, a complement formation device is provided which selectively determines Field length signals that are delivered to the first signal receiving device to be complemented, where the particular field length signals in question are indicative of the number of words to be to be added to the number of words contained in the field length of the operand, which are the same of a certain length. Furthermore, one has at least a first part and a second part Register for the leading zeros or the leading zero. With the complement formation facility and the A first memory device is connected to the relevant register, which stores the complement signals in the first part allowed to save. Furthermore, a second signal recording device is provided, which has a number of Allowed to record signals which are characteristic of a word of the highest order and subsequent words the operands. There is also a detector device

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BhO ORiGlNAI,

Increased the speed with which the decimal arithmetic instructions are processed when the system stores the number of leading zeros in the operand. In the Honeywell 6000 mainframe computer system, counting logic is always used for the leading zero. In addition, the computer system in question has a relatively complicated scheme for counting the number of leading zeros. In the subject system, high order data words containing a plurality of decimal digits are stored in a register in a first cycle. The word in the register is then time control special logic elements checked in the second cycle under the control of, on the number of zeros that are included in the data word ₀ The special treatment of leading zeros requires a significant link arrangement whereby the system cost increases and is introduced an additional delay cycle _e This leads to a reduction of the data rate or _e of the throughput during the processing of decimal numeric commands.

If the effective digit number or digit count for Storage of the resulting operand is required, then the leading zero count of 64 = decimal digits, the maximum operand size, subtracted

This solution takes up a number of machine cycles and requires a relatively large amount of hardware as a result the throughput of the system is reduced at an increased cost.

The invention is accordingly based on the object of providing a microprogrammed data processing system with a to create improved or increased throughput »

In addition, an improved arrangement is to be created which determines the number of leading zeros in the

030Ü28 / 087S BAD AL

provided, which is connected to the second signal recording device and the leading zeros within of the operand words. With the detector device is an incrementing device connected, which increment the content of the first part by a certain number in the case allows the detector device in question to enter Output signal is generated which provides an indication that the word of the operand to be passed to the second Storage device is delivered, contains a total of leading zeros. Finally, with the detector device a second memory device is connected which allows signals encoded in the second part to be stored, which are indicative of the number of leading zeros in the word with the digit highest priority for the transmission to the execution unit are included.

The invention also provides a decimal unit, the decimal-numeric result operands allows modification which have been processed by means of a microprogrammed execution unit The operands concerned are available for storage in a memory. This decimal unit includes a signal pickup device for picking up signals indicative of each word of the resulting Operand issued by the execution unit, with the lowest significant word first is delivered and each word is recorded in response to a microword. With the signal recording device a detector device is connected which, in response to the respective word signals, generates signals which decimal digits of the word least significant and of subsequent words of the resulting operand. A decoding device is connected to the detector device which responds to the decimal digit signals allowed to generate a first signal, which

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is indicative of a decimal digit in the high significance digit of the word lowest significance with a value that is greater than the decimal value zero. The decoder in question also generates binary signals which are indicative of the position of the decimal digit of the highest significance of the word, specifically for the case that the decimal digit has a decimal value zero in the digit of high significance. Furthermore, a word counter device is provided which, in response to the occurrence of a control signal, generates a count or number which is 1 lower than the number of words of the resulting operand which are received by the memory device. An adder device is connected to the word counter device and the decoder device and, in response to the relevant count and the first signal, generates signals which are indicative of the number of effective words which are received by the first memory device. A counting register is also provided for the effective digit. This count register has at least a first region and a second region to _0. The first area is operatively connected to the adder means, for storing signals indicative of the number of effective words "The second region is operably connected to the detector means to the To store binary signals which are indicative of the number of decimal digits in the resulting word, which comprises the most significant decimal digit of the resulting operand, the storage taking place when each of the respective words in the first memory means has an effective digit. The relevant register stores the number of effective digits accepted by the unit in the cycle in which the word is transmitted by the execution unit «

A preferred embodiment of the present

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Invention comprises a data processing system with a cache memory for storing operands and Commands or instructions that include .descriptors. Furthermore, a decimal unit is provided, which represents the relevant Operands and descriptor information, which includes the operand and an execution unit describes that processes the operands in accordance with a decimal-numeric instruction.

The operand as stored in memory has a length, i.e. a number of decimal points, defined by the descriptor information stored in the decimal unit. The execution unit has a 64-decimal digit field to store the operand used for processing is recorded from the decimal unit. The execution unit requires a count of the number of leading lMulls, which are required for the 64-decimal digit field to fill in; the relevant execution unit receives the relevant count from the Decimal unit based on a microword command.

The decimal unit loads the upper area of an HLZC1 counting register (730-96 ) for the leading zero with a number or count of the number of words in the operand that the decimal unit will not send to the execution unit. An ARWC adder (730-60) calculates the number of words that the decimal unit will send to the execution unit based on the descriptor _{information o} The output signals of the ARWC adder are inverted by means of an inverter (730-92), and the upper range of the RLZC1 -Registers is loaded with the number of full words that the decimal unit will not send out to the execution unit to fill in the 64 decimal digit field. When the operand words are cached and processed by the decimal unit, the word being higher

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Significance is transmitted first. ₉ , if the word contains leading zeros, a binary 1 is added to the upper area of the RLZC1 register in the relevant cycle. When the the most significant digit containing W _O rt processed by the decimal, then the count or counter position is stored the number of leading zero digits in the lower portion of RLZC1 register; the RLZC1 register stores the number of leading zeros required to fill in the 64 decimal digit field in the execution unit.

For example, if the operand defined by the descriptors shows a length of 24 decimal digits, then shows the output of the ARWC adder a decimal indicating that three words are being sent out to the execution unit. Then saves the upper area of the RLZC1 register is a number of five words. If the first from the decimal unit recorded word contains a total of leading zeros, then the upper area of the RLZC1 register becomes a number of store six words. If the next word taken from the decimal unit has three leading zeros, then a binary 3 or 011 is stored in the lower area or part of the KLZC1 register. That RLZC1 register stores a number leading from 51 Zeros that are required to enclose the 64-decimal digit field to be filled in in the execution unit ,, The decimal unit Holds 24 decimal digits, 11 of which are leading zeros and 13 of which are significant Digits are. These 13 digits and the 51 leading zeros fill the 64 decimal digit field in the execution unit the end.

The decimal unit replaces the non-decimal digit information and transfers the operands to the output

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4 (

management unit for the purpose of processing in one Calculation process. The resulting operand becomes the Transfer decimal unit with the required sign, exponent, new inscription characters and zone bits are added and the operand is put back into the scratchpad memory called the cache memory is saved.

in the worst cases, the number of significant decimal points in the operand is less than that Length of the field in the cache address location into which the resulting operand is written will. Since the operand is written to the cache word by word at the respective point in time, the throughput is or the data rate of the system increased when the number of significant decimal points in the resulting Operand is known. This allows the system to use only as many firmware cycles as required to transfer the resulting operand to the cache.

The resulting operand or the result operand is determined by the decimal unit from the execution unit recorded, with the word of low order recorded first. A RWPC register (730-84) is opened increments each word after the first word is recorded. The RWPC register saves a number that is 1 less than the number of words represented by the decimal unit of an execution unit are included. An AEDC adder (730-86) adds the output of the RWPC register to a signal which occurs as logic signal 1 when the recorded by the decimal unit Word contains a decimal O in the high-order digit position of the word. An output of the AEDC adder is stored in a word count area of the RLZC1 register (730-96). The RLZC1 register will but not loaded in a decimal unit cycle,

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in which the processed word is decimal in total
Contains zeros. If the word contains a number of decimal zeros in the high order positions of the word, which is followed by a digit that is not a decimal zero, then the binary count of the number of high order digits in a word counter area of the
RLZC1 register. When the entire result operand has been processed by the decimal unit, the RLZC1 register contains the count of the number
the effective decimal digits in the result operand. It should be noted that the RLZC1 register in
has been loaded in the same cycle in which the
Decimal unit a word has been processed which contains a digit that is not a decimal zero.

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BM)

The invention is explained below with reference to drawings for example explained in more detail.

1 shows, in an overall block diagram, a main processor with which a cache memory unit and a System integration unit are connected. Fig. 2 shows in a block diagram an execution unit and part of a drawing unit of the main processor.

3 shows a detailed block diagram of a Decimal unit.

4 shows the decimal unit in an overall block diagram.

Figure 5 shows instruction and descriptor formats for two decimal-numeric instructions.

6 shows a logic diagram of counting circuits with a leading zero.

Fig. 7 shows effective numeric circuits in a logic diagram.

8 shows a diagram of vector branching logic.

General description of the processor 700 -

From Fig. 1 it can be seen that a main processor 700 includes an execution control unit 701, a control unit 704, an execution unit 714, a drawing unit 720, an auxiliary computing and control unit (AACU) 722, a multiple ILJLvidier unit 728 and a decimal unit 730. These units are with each other in the manner shown tied together. In addition, the control unit 704 has a number of connections to the illustrated cache memory or notepad memory 750.

The execution control unit 701 includes an execution control memory Address formation and branching input

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called 701-1 and an execution control memory 701 = 2 " The memory 701-2 and the unit 710-1 are via bus lines 701-3 and 701-6 as shown connected with each other.

The control unit 704 contains a control logic unit 704-1, a control memory 704-2, an address generation unit 704-3, a data and address output circuit 704-4 and an XAQ register area 704-5 , the respective devices being connected to one another as shown .

The control unit 704 provides the necessary control for the execution of the address formation operations, the command call / execution operations and the sequential control for the various cycles of operation and / or for the machine states “The control is through the logic circuits of block 704-1 and by execution control unit 701 with respect to the various Areas of the control unit 704 caused or executed.

The XAQ register area 704-5 contains a number of program view registers, such as index registers, an accumulator register and a quotient register “Further so-called Program view register or register visible for the program, like the instruction counter and the address registers, are included in the address forming unit 704-3.

As can be seen from Fig. 1, region 704-5 takes signals from the unit 704 = 3 to «These signals, which are characteristic of the content of the command counter, are sent via the Lines RIC 00-17 «In addition, lines ZRESA 00-35 Output signals from execution unit 714, where these output signals correspond to the results of the operations, which are executed on different operands

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will. The area 704-5 also receives an output signal from the auxiliary computing and control unit the lines RAAUO-8.

The area 704-5 specifies signals which are characteristic of the content of one of the registers contained in the area, the relevant signals being output as input signals for the address formation unit 704-3 via the lines ZXO-20 and ZXA 24-35. The address generation unit 704-3 outputs the information to the execution unit 714 via a switch, specifically via the lines ZDO 0-35 « can be transmitted via the lines ZEB 00-35. Finally, the content of selected registers of these registers can be transferred from area 704-5 to the multiplication division "Unit 728 via lines ZAQ 00-35 "

The address generation unit 704-3 generates addresses from the contents of various registers ₅ contained in the relevant unit; it outputs the resulting Yer · = link addresses ^ the effective addresses and / or absolute addresses for distribution to the other units via the lines ASFA 00-35. The address formation unit 704-3 accepts the results of operations on which with respect to two operands are executed by the Ausfünrungseinheit 714 ₉ and via lines ZRESB 00-35 "The unit 704 = 3 takes the content zxtfeier base pointer register characterizing signals from the control logic unit 704 via the lines RBASA and RBASAO-1 to «, The output signals from the multiplication / division unit 728 are output to the address formation unit 704-3. Finally, the content of a second or secondary command register (RSIR) is sent as an input variable via the RSIR 00 = 35 lines to the input

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300000 is

called 704-3 released »

The data and address output circuits 704-4 generate j the cache address signals _o proposed for the circuits concerned to the cache memory unit 750 via the lines RADO / ZADO 00-35 These address signals correspond to signals of a number of the series of input lines ZDI 00- 35, 00-35 and ASFA ZRESB are supplied 00-35 _p wherein the series in question is selected by switches in the circuits of block 704-4 Sindo addition itferden word address signals over lines 32-33 given ASFA

Control logic unit 704-1 provides data paths that interface with various units • have ^ those contained in the cache memory unit 705 sindo The lines ZIB 00 = 35 represent an interface with a command buffer that is stored in the cache memory 750 is included «The lines ZDI 00-35 are used for this purpose ^ data signals from the cache memory 750 to the control logic unit 704-1

As can be seen from FIG. 1, the control logic unit 704-1 supplies a number of groups of output signals. These output signals contain the content of certain registers _9, for example a basic instruction _{register (RBIR) 9,} the content of which as an input variable to the control store 704-2 via the lines RBIR 18- 27 is supplied «, the control logic unit 704-1 receives certain control signals that are read from the control memory 704-2 via the lines CCSDO 13-31 _{or the like}

The control logic unit 704-1 also contains a secondary or »second command register (RSIR), which parallel to the basic command register at the beginning of the

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Processing of a command or an instruction is loaded. The content of the second command register As mentioned above, RSIR 00-35 is fed as an input variable to the address generation unit 704-3. Additionally becomes part of the content of the relevant second instruction register as an input variable of the auxiliary arithmetic control unit 722 via lines RSIR 1-9 and 24-35 and the decimal unit 730 via lines RSIR 21- = 35 fed.

The control store 704-2 is used, as explained here, for the initial decoding of a program instruction operation code, which is why the memory in question is designed in such a way that it contains a number of memory locations (1024) contains, one for each possible command or Instruction opcode.

As mentioned, the signals provided on lines RBIR 18-27 are applied as input signals to control store 704-2. These signals select one of the possible 1024 memory locations. The content of the selected memory location is output to the lines CCSDO 13-31 and CCSDO 00-12, as is illustrated in FIG. 1. The signals provided on lines CCSDO 00-12 correspond to the address signals used to address execution control unit 704, as explained.

The execution unit 714 ensures the execution of the instructions, the unit 714 performing arithmetic and / or shifting operations on operands selected from the various input signals. The results such operations are delivered to selected outputs. Execution unit 714 takes Data from a data input bus line that corresponds to the lines RDI 00-35, their signal source is control logic unit 704-1. The contents of the

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Accumulator and quotient registers contained in area 704-5 are, as mentioned above, output to execution unit 714 via lines ZEB 00-35 from address generation unit 704-3 to input bus lines ZDO 00 = 35 Signals v / ground via switches contained in execution unit 714 as output signals on lines ZRESA 00-35 and ZRESB 00-35, as is illustrated in FIG Auxiliary computing and control unit 722 on _p which are output via the lines ZRESPA 00 = 06 »In addition, the unit 722 sends shift information to the unit 714 via the lines ZRSC 00-35 ο

The drawing unit 720 is used to execute the drawing commands or instructions that require operations such as the translation and processing of data fields. As will be explained, these types of commands or instructions are used as extended instruction set instructions (EIS ) are designated. Such instructions or "instructions, which executes the drawing unit 720 include displacement = or" Move-j, sample and compare instructions _o characteristic of the operand signals v / grounded via the Lei = obligations ZRESA 00 = 35 output information relating to the The type of character position within a word and with regard to the number of bits x is sent to the character unit 720 via the input lines ZDB 00-07 «

Information that characterizes the results of certain data operations is transmitted via lines ZOG 00-08 Such information supplied to the unit 722 includes exponent data and data in hexadecimal form «Die

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Character unit 720 gives output operand data and control information to unit 722, to unit 730 and to unit 728 via the lines RCHU 00-35.

The auxiliary arithmetic and control unit 722 carries out arithmetic operations based on control information; like exponents used in floating point operations, calculating operand lengths and pointers and generating counting information. The results of these operations are delivered to execution unit 714 via lines ZRSPA 00-06 and via lines ZRSC 00-06, as mentioned above. The information signals corresponding to characters, such as 9-bit characters, 4-bit characters, ₅ input hexadecimal data converted into decimal data, quotient information and sign information ^ are sent to the area via lines RAAU 00-08 704-5 submitted.

As is apparent from Figo 1, 722 takes the unit comprising a number of input signals to _0. The character pointer information is supplied respectively over lines ASFA 33-36 leave "A numerical scale factor information EIS is applied to the unit 722 via lines RSIR 24-35 Other signals issued relating to the calling of special commands are issued via the lines RSIR 01-09. Exponent signals for floating point data are sent to unit 722 via lines ZOG 00 = 08, while floating point exponent data signals are sent from unit 704-1 via lines RDI 00-08. Shift counting information signals for certain commands or instructions (for example for binary shift commands) are sent to the unit via lines RDI 11-17. With regard to the input signals sent to lines RCHU 00-35, it should be noted that lines 24 = 35

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Emit signals that correspond to the length of the EIS command fields while lines 18-23 correspond to address modification signals hand over to unit 722 »

The multiply / divide unit 728 causes execution of multiply and divide instructions at high speed ₀ This unit can be regarded as built in a conventional manner; they may have the shape of the multiplication unit, as set forth in US-PS 40 41 292 "The unit 728, as is indicated in FIG _o 1, takes multiplier, dividend and divisor input signals over lines RCHU 00 = 35 on. The multiplicand input signal from the register area 704-5 is fed via the lines ZAQ 00 = 35 »The results of the calculations carried out by the unit 728 are transmitted as output signals to the lines ZMD 00-35»

The decimal unit 730 is under firmware control effective during the processing of the decimal-numeric instructions »The instruction or command format and its associated descriptor words will be explained in detail with reference to Fig. 5, The instruction word and the descriptor word information i '/ ground from the decimal unit 730 via the lines RSIR 21 = 35 and ASFA 33-36 included. The concerned Signals cause the decimal unit 730 to extract the operand described by the descriptor word from the Including cache memory 750 over the line ZdT 0-35. The decimal unit 730 removes the sign and exponent characters from the operand word that packs the Stores data in up to eight 4-bit characters per word the data in 32-bit words, makes an alignment and transmits the data words to execution unit 714 over lines RDOD 00-35, ZMD 00-35 and ZDO 00-35o The data words stored in the cache memory contain up to four 9-bit characters out of eight

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4-bit characters in a 36-bit word. The 9-bit character contains five zone bits and four data bits. The zone bits are separated from the 9-bit character, and the remaining data bits are placed in a 32-bit register which can contain up to two cache memory data words consisting of 9-bit characters ^ or where a cache data word of 4-bit characters consists. The assembled data words of the operands are assembled in the execution unit 714 and processed in accordance with the decimal numeric command. The operand that is the one you want Represents the result of the numerical command, the decimal unit 730 is transmitted via the lines ZRESA 00-35, character unit 720 and then decimal unit 730 on lines RCHU 4-35. In this unit the operand is processed in accordance with the encoded information in a descriptor word. Of the Operand is sort of unpacked, adding the required signs and exponents, and over the lines ZADSP 0-11, and where the EBCIDC or ASC11 zone characters are added if 9-bit decimal characters are indicated by the information encoded in the descriptor word. Furthermore, there is another Storage in cache memory 750 at an address indicated by an address field in the descriptor word is designated. The data is stored in the cache memory 750 via the lines RDOD 00-35, ZMD 00-35, ASFA 00-35 and RADO / ZADO 00-35 saved. The decimal unit 730 is under firmware control via the lines MEM-DO 88, 89, 94-97. The signals PK-VCTR 0-3 from the decimal unit 730 show the Execution address and branch circuit 701-1 the status information as a function of firmware commands which are received by the decimal unit 730 via the lines MEM-DO 88, 89, 94-97. the from execution address and branch unit 701-1

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BATH ORIGINAL

Recorded signals PK-VCTR 0-3 lead in the execution control memory 701-2 to a branch to a specific microprogram subroutine ,, The branch logic associated with the execution control memory 701-2 is described in more detail elsewhere (see FIG US patent application, Serial No »853 937) ο

The data and control signals are passed between cache memory 750 and a system interface unit Via the data interface line 600 and between the Cache memory 750 and the processor 700 via the lines of the interface device 704, Finally, the cache unit 750 receives addresses and data signals from the data · = and address output circuits 704 = 4 via lines RADO / ZADO 00-35 and via the lines ASFA 32-33 ο

Execution Unit 714 - FIG. 2

The unit 714 contains addressable short-term register banks 714-10 and 714 = 12 as main units, an arithmetic logic unit (ALU) 714-20 _0, a shifter 714-24 and a notepad memory 714-300. In addition, the unit 714 contains a number of a plurality position-adjustable data selector switches 714 = 15, 714-17 * 714-22, 714-26, 714-28, 714-34, 714-36 and 714-38j to ensure flexibility with regard to the selection of operands and output results «

During operation, the operands are grounded via the ZOPA switch 714-15 and the ZOPB switch 714-17 from one of the registers of register banks 714-12 and 714-10 or from other input lines, ie the lines shown ZEBO-35 or RDIO-35 selected »The ALU unit 714-20 and shifter 714-24 perform operations on selected operands, and the

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Results are selected using switches 714-24, 714-36 and 714-38 on the output bus lines ZRESA 0-35 and ZRESB 0-35 submitted. In a corresponding manner, the contents of a notepad memory space that can be accessed by the signals that have been output by the AACU unit 722 via the lines ZRSPA 0-6 is selected can be read out via switches 714-34, 714-36 and 714-38.

The selected output results or other data are then loaded into the other registers within processor 700, including the temporary register banks 714-12 and 714-10 or the notepad memory 714-30 of execution unit 714.

In detail, the sources of the operands for both ZOPA and ZOPB switches 714-15 and 714-17 are identical. The selection of the switch position for the ZOPA switch and for the ZOPB switch is under the control of the Microinstruction word. The ALU unit 714-20 performs logic operations, decimal operations and binary operations Operations on the selected operand data Mn under the control of the microinstruction word.

The shifter 714-24 is a combinatorial link network, which is used to align binary data under a microprogram control, to move or rotate. The input data signals from the ZSHFOP and ZEIS switches 714-28 and 714-22 can be viewed as concatenated so that a single double word input signal is formed. the Slider 714-24 provides a 36-bit output signal, which is shifted in accordance with the shift counter position. The ZSHFOP switch 714-28 is controlled by the microinstruction word, while the shift counter setting is controlled by the sequencer constant field of the microinstruction word is determined which

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3000008

appropriately selected via the auxiliary computational control unit 722. For the purposes of the present invention, the ALU unit 714-20 and shifter 714-24 can be viewed as being constructed in a conventional manner control, are described in more detail elsewhere (see US patent application, Serial No. ₀ 853 944) "

The notepad memory 714-30 provides a working space for the storage of various data that are required for the execution of certain commands or instructions as well as for various constants and descriptor values to save the preparation command table value, which is required for the execution of print editing operations ο The writing in the notepad memory 714 = 30 first includes the loading of the RSPB buffer register 714-32 with input data which are supplied via the ZRESB switch 714-38 " During a next cycle, the content of register 714 = 32 is written into the memory location which is designated by the signals that are output from the AACU unit 722 to lines ZRSPA 0-6 of the microinstruction word (RSP-FeId) occurs as binary signal 1 _β

With regard to the other switches that have been mentioned, it should be noted that those supplied by the unit 714 Results via the ZALU switch 714-26, the BSPI switch 714-34, the ZRESA switch 714-36 and the ZRESB switches are issued under microprogram control. The Sahalter ZALU and ZSPDI are laying a first Selection level for the ZRESA and ZRESB switches, which define a final selection level «As the two

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ZRESA and ZRESB switches have identical input signal sources they can deliver the same output data. · ■

Operands from the decimal unit 730 are assigned via the Lines ZDO 00-35 added and stored in selected RTRL O-3 registers 714-12 and RTRH registers 714-10, as described above. Long operands are thereby stored in the notepad memory 714-30 saved. The resulting operand is transferred to the RCHO register 720-10 of the ZRESA switch 714-36 Character unit 720 and read out into the decimal unit 730 via the line RCHU 0-35.

Decimal unit 730 - General Description - System

Referring to Figure 3, the decimal unit 730 operates under firmware control; it processes decimal-numeric commands and accepts data words from the cache memory 750, the consist of 4-bit characters or 9-bit EBCDIC or ASCII characters. The data word can be followed by a Contain a sign or a leading sign, which can be part of an overlaid sign; it also contains an exponent if the data word is part of a floating point operand.

The decimal unit 730 removes the sign and / or the exponent from the data word, compresses the data words from 36-bit words to 32-bit words, packs both 4-bit and 9-bit decimal digits into data words that are made from 4-bit decimal digits and transfers the resulting 32-bit data words to the execution unit 714 for the purpose of processing, as specified by the command or by the instruction.

The words most significant and least significant

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of the operand picked up from the cache memory 750 may contain information that is not part of of the operand. This rewriting information is stored in registers and associated with the words highest priority and lowest priority of the operand are added, provided this is done during the Memory operation is required.

The decimal unit 730 processes operands from Consist of decimal digits and which are either short operands or long operands. Have short operands a length of 15 decimal digits or a shorter length. Long operands have a digit length of 16 to Decimal digits. Operands with more than 64 decimal digits are not processed in the decimal unit 730, rather, they are processed by the firmware.

Short operands with one or two data words. will to the short-term registers RTRL 0-3 714-12 and RTRH 4 = 7 714-10 in the execution unit 714 ,. Longing Three to eight word operands are transferred to scratch pad memory 714-30 in execution unit 714.

The decimal-numeric commands include an instruction word which defines the execution of an arithmetic operation, furthermore a descriptor word ₉ which defines the properties of an operand 1, a descriptor 2 word which defines the properties of an operand 2 , and a descriptor = 3 word, which defines the properties of a resulting operand 3 «Some commands or instructions use the descriptor 2 _{9 to} define the properties of the two operands 2 vsnd 3. The command and descriptor formats are

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illustrated in fig.

The decimal unit 730 takes operands 1 and 2 from the cache memory 750 under the firmware control, aligns them and transfers them to the execution unit 714. The two operands are checked for an illegal sign or for illegal digits. The resulting operand 3 is transferred from the execution unit 714 to the decimal unit 730, in which it is, as it were, unpacked from 32-bit data words to 3b-i3it-data words, with ASCII or EBCDXC zone characters being added for 9-bit words . If necessary, exponent signs and signs are added. The operand ~ 2 ° or the operand-3 = -New write «Information that has previously been saved can be added. The operand is checked for zero / overflow ™ states, rounded down or shortened, if necessary, and stored in the Cahee memory 750 again.

The operands defining descriptors sizid in the RSIR register (in the drawings not shown) of the control logic unit 704 = 1 stored "The RSLR = bit positions 21 to 35, the gates of the bit positions of the Beskrip = · as shown in FIG _o 5 correspond ,, are transmitted to the decimal unit 730 and stored in registers of this unit.The RSIR bit positions 17 = 20 are transmitted to the decimal unit as signals ASFA 33 = 36, which are also stored in a register in the decimal unit 730 ,,

As shown in Fig. 5, the descriptor fields are defined as follows

ASFA 33 is the least significant bit of the address of the most significant word of the operand, which indicates an odd or even word address "

030028/0876

ASFA 34 = 36 points to the digit position within the

Word of the highest value of the higher value

Character of the operand, RSIR 21 shows an operand of 4-bit characters in

the case that a 1 or 9 bit character

if there is a zero »RSIR 22 = 23 defines the operand type and the prefix

character positiono

00 leading sign =, floating point or perforated leading sign _{, etc.}

01 leading sign in the standard

10 following sign in scale »

11 no sign in the scale or the following perforated sign.,

RSIR 24 = 29 is the scale factor, d _o h "is the

Position of the decimal point “A negative Number moves the decimal point to the left of the lowest significant digit “One positive number shifts the decimal point to the right of the least significant digit ο

RSIR 30 ™ 35 shows the number of characters in the operand ₀ The characters contain the decimal digits, signs and exponents,

The firmware controls the decimal unit with the signals RCSR 88-89, 94-97ο The signals represent output signals of the execution control memory 701-4 "With the exception of the fields CLK ₉ ZAM ₉ MPYREG and DUCMD, the firmware word is described in more detail elsewhere (see US patent application i, Serial No. ₀ 853 944) "

Θ30028 / 0876

Table 1

Linkage RCSR signals Description name of the

Firmware ge-88, 89, 94, 95, 96, 97 controlled signals

Type F CLK, ZAM, MPYREG

O 0.00 Set FMYDV if DUCMD-200

FP0P1D, otherwise zero

0 0 0 1 Select result = zero DUCMD-201

Display 1

0 0 10 selection 0P1 = zero, DUCMD-202

OP2 = zero displays

0 0 11 Loading of STC MASK DUCMD-203

in RDOD

0 1 0 0 Selection of the DU over DUCMD-204

running and cancellation indicators

0 1 0 1 Reset the zero / over- DUCMD-205

run test logic

0 1 10 Set FUMPW, DUCMlJ-206

if FPOPtD

0 1 11 Not used

Type F DUCMD link arms

0 0 0 Set FMVN if DUCMD-300

FP0P1D, otherwise zero

0 0 1 Read the operand via DUCMD-301

YOU

0 10 Delivery of the full charge DUCMD-302

permanent status

0 11 Saving the operand DUCMD-303

about YOU

1 0 0 Checking zero / overflow DUCMD-304

1 0 1 Transfer of data from DUCMD-305

RCHO to RPK

1 10 Loading of new enrollment DUCMD-306

data

1 11 Load the DU sign DUCMD-307

Register (RSGN)

0 0 Loading the DU exponent DUCMD-308

Registers (REXP)

0 1 Insertion of the rounding DUCMD-309

Constant in RD0D

10 Introduction of the leading DUCMD-310

Zero counting of the

Operands in RD0D

030028/0876

000006

Type F. 1 1 DUCMD 1 1 1 1 1 O O O 1 1 1 1 O 1 1 1

1110

11 1111

description

Insertion of the operand word counter position in RD0D Not used

Selection of descriptor = - Vector advertisements

Display memory op vector selection

Linkage = name

DUCMD-311

DUCMD-313

DUCMD-314

Show

of long op vector DUCMD-315

It should be noted that the RSCR bit positions 88 and the type F field p the fields defining the RSCR bit positions 94 = 97 are designated "If the field type F contains a ¹ MO", then v / ground the micro \ rortfields CLK ₅ ZAM and MPYREG expansive. If the field type F contains an "11", then the micro \ rortfield DUCMD is selected

DUCMD 200 sets the FMYDV indicator during a

Multiplication = or division decimal

Instruction ₀

DUCMD 201 selects the ADSZ condition branch ₀ DUCMD 202 selects the RRLTRD condition branch

show if the operand 1 equals zero _s

and the RREQRD conditional branch indicator

\ tf is selected if the operand is 2

Zero is o
DUCMD 203 transmits the output signals RCHU3O = -35, which are in

STC = _s mask are stored to the RDOD-Re = -

register 730-154o
DUCMD 204 selects the RRLTRD = condition branch display

for an overflow and the RREQRD = condition

branch display for an abort operation

tion from "

DUCMD 205 resets the flags FCRD and FDOFL »DUCMD 206 sets the flag FCMPN _P if the FP0P1D-

Indicator set to link value 1

is ο

Ö30Q28 / Q876

DUCMD 300 sets the FMV mark, provided that

FPOP1D flag is set to logic value 1.

DUCMD 301 starts the operand load operation in decimal unit 730.

DUCMD 302 promotes the completion of the load operation by setting the FLDCOMPL and FRDP1 are set,

DUCMD 303 starts the storage result in or through

the decimal unit 730 by setting the flags FOPSTR and FMSDRN ₀

DUCMD 304 sets the FCZO flag for a check of zero / overflow of the in the RCHO register 720-10 stored word «"

DUCMD 305 sets the indicators FCZO and FRPK.

DUCMD 306 sets the FLDREWR flag and selects the RREQRD state branch indication for an abort operation, _{or the like}

DUCMD 307 causes the sign register RSGN 730-134ο to be loaded

DUCMD 308 causes the exponent register RE) [P 730-138 to be loaded and also to load the RSF3 scale factor register of register bank 730-4! Driving a floating point FP0P3 ~ Cycleo

DUCMD 309 controls the loading of the rounding constant stored in the ZPK switch 730 = 150 into the correct character position of the RDOB register 730-154 and sets the FRCMD _{0 flag}

DUCMD 310 controls the loading of the leading zero counters = position of the operand in the RDOD register 730-154,

DUCMD 311 controls the loading of the operand word counter position into the RDOD register 730 = 154 «,

Q 3 c α 2 a / ο δ 7 8

DUCMD 312 not used, DUCMD 313 selects the descriptor 1 vector and

Descriptor 2 vector displays off and

sets the indicator FDVC1, DUCMD 314 resets the indicator FCRD and dials

the memory vector _{displays o} DUCMD 315 selects long input vector displays ο

The decimal unit 730 responds to the firmware requirements with the PK VCTR 0-3 signals given below.

Table 2 Vector branching data

PK-VCTR

0 12 3

Type length

0 0 0 0 Short operand and 4-bit data. 0 10 0 Short operand and 9-bit data 10 0 0 Short operand and (4 or 9-bit data) and

Overlapped sign 110 0 Long operand

Descriptor 1 vector

0 0 0 0 Execution of the descriptor 2 vector 0 10 0 Descriptor 1 = floating point, 10 0 0 Descriptor 1 = perforated leading prefix

character _{9 to} scale 110 0 descriptor 1 = perforated following sign, to scale

Deskrrptor »2 ~ vector

0 0 0 0 Descriptor 2 ^ floating point or punched sign

0 10 0 Descriptor 2 = floating point

10 0 0 Descriptor 2 = perforated leading sign, true to scale

110 0 Descriptor 2 = punched subsequent sign, true to scale

930028/0876

Vector branch data PK-VCTR
12 3

Memory vector

0 0 0 Check for result = zero, overflow 10 0 floating point result - check the result = ses = zero, overflow

0 0 Overturned leading sign output = signal - check for result = zero, overflow

0 Overperforated subsequent sign output signal - check the result = zero, Overflow

Long input signal

0 0 0 Both operands are true to scale and the set length of descriptor 1i63 and the set length of descriptor 2i63 as well as the perforated sign

10 0 Both operands are true to scale, with the set length of the descriptor 1 ^ L 63 and the set length of the descriptor 2 <. 63 and a perforated sign are present.

0 0 Both operands are true to scale and set length of descriptor 1 Λ 63 or set Length of descriptor 2> 63 »

0 Execute the descriptor 1 vector and the Descriptor 2 vector.

Predicted number of delay cycles for processing descriptor-1 or Descriptor 2 operands

Delay cycles 0 0 1 1 2 2

0 0 0 Data words 0 0 0 1 1 0 0 1 0 2 0 0 1 1 1 0 1 0 0 2 0 1 0 1 1 0 2

030028/0876

The following Boolean expressions illustrate the Firmware selection of the vector branching data

[1 PKVCTR = FDUACT (DUCHM 315 + DUCMD 313 - FDCV1 + (DUCMD 313 DUCMD 314 ° DUCMD 315))

[2 PKVCTR = FDUACT (DUCMD 314 + DUCMD 315 + DUCMD 301 + DUCMD 313 · FRDP1)

[4PKVCTR = FDUACT (DUCMD 313 + DUCMD 314 + DUCMD 315)

[PKVCTR = 1

IPKVCTR = 2 or 3

[PKVCTR «4

- C

selects the type-length vector from _P which shows the firmware ^ whether the operand is a short or a long operand, that is 4 ~ bit ~ characters or 9 = -bit = character _p and whether then »if a short operand is present, a Punched sign in the descriptor = tor = 1 ~ or descriptor ~ 2 = 0perands in front of the isto

selects for a short operand from the number of delay cycles that are required j after the first read command to the cache memory 750 has been sent to the output of the first data word to the execution unit 714 "This forecast simplifies the firmware processing of short operand ₀ selects the Descriptor-1 vector which defines descriptor 1 as a floating point _{operand 5} selects an operand with a perforated leading or trailing scale sign or indicates to the firmware that the descriptor-2 = vector is to be executed

selects the descriptor-2 vector that Descriptor 2 as a floating point or scaled operand with a perforated leading or trailing sign determines »

030028/0876

^ PKVCTR = 6 selects the storage vector that the

Firmware indicates that a specific check regarding the resulting Operand is to be made that is equal to zero.

[PKVCTR = 7 selects the long input vector and

shows the firmware the comparison between the operand lengths and 63 in terms of scale Operands on. The vector also shows the firmware the execution of the Descriptor 1 and Descriptor 2 vectors.

The decimal unit 730 gives a number of conditional branch indications to execution address and branch circuit logic 701-1.

Condition branch ^ displays Name Source

STARTMiRT RRLTRD Send data RREQRD OPI = NuIl RRLTRD 0P2 = zero RREQRD Overflow . RRLTRD Abort RREQRD Result = NuIl ADSZ Data AVA ADSZ CK-STR-VECT ZAMO

The RRLTRD signal is generated as follows %

1, during a BUCMD command 202 ₉ verm. FOP1Z the flag is set, indicating that the Qperaa <ä1 zero _o

2. During a command DUCMD 204 _p is set vierni FDOFL the indicator, thereby indicating that an operand overflow was present,

930028/0876

3o during a startup write operation to update the firmware indicate that write commands are to be sent out to cache memory 750 o

The RREQRD signal is generated as follows? 1o During a command DUCMD 204 or DUCMD 306, where the termination signal occurs as a link signal 1 and indicates that the digits of the lowest value of a Operands are lost,

2 "during a DUCMD 202 command if the identifier F0P2Z is set, indicating that the operand Is zero,

3o during a send data operation to indicate the firmware that data is to be transferred to the decimal unit 730 from the execution unit 714 o

The ADSZ signal is generated?

1. During a DUCMD instruction, if the operand is zero,

2o νίβΏη data are not available, however with the exception during a command DUCMD 201 "

The ZAMp signal is generated to test a memory vector function display like a floating point, a punched character, an overflow, result = null operando

The conditional branch indicators are grounded by the Firmware called and they result in an execution control store = 701 = 2-branch "

Now the description of the decimal unit status = mark, including the Boolean expressions for setting and resetting the mark? F3DESC Set for processing operand 3,

which is defined either by descriptor 2 or by descriptor 3 “The Boolean

030028/0876

¥ 1

Expression is %

Set F3DESC (FPOP RDESCO.RDESC1) F3DESC reset (FPOA)

FALT Set during the save operation in

alternative cycles. The decimal unit forms one word for the RDOD register 730-154 in one Cycle and transfers the word to execution unit 714 in the next cycle. The set FALT signal means that a Word released in the RDOD register «, The Boolean expression is;

Set FALT: ((DUCMD 303 + FOPSTR) "PALT * .FP" ÖT) Reset FALT: (FOPSTR'FALT + FPOA)

FCMPN Set for a firmware command DUCMD 206

regarding a comparison of a numerical instruction. The Boolean expression is: FCMPN set; (FPOP1D DUCMD 206) FCMPN reset: (FPOA)

FCPCO Set when loading or saving

9-bit data words from odd addresses in the cache memory 750 are made. The Boolean Expression reads:

Set FCPCO: ((ZCPAO (FDUACT-FRDP1 + SF0P2LD + FLDCOIiPL- (DUCMD 303 + FOPSTR)) + FCPCO · (F0P1LD.SF0P2LD

+ F0P2LD) * (FDID + FDFD) + FCPCO

• (DUCMD 303 + FOPSTR) STRDOD)

• FPOA)

FCPCO reset: (ZCPAO · (FDUACT »FRDP1

+ SF0P2LD + FLDCOMPL

.DUCMD 303 + FOPSTR)) + PCPCO. (F0P1LD.SF0P2LD + F0P2LD) • (FDID + FDFD) + FCPCO. (DUCMD 303 + FOPSTR). SRDOD + FPOA)

030028/0876

FDADIS

Set during an operand load operation if one of the operands is long "This indicator lets the second load-DU _{operand = · the command CDUCMD 301J start a load process e} A long operand causes the decimal unit ρ to issue the first load-DU operand (DUCMD 301) to allow the firmware to be set to process a long operand. " The firmware always assumes a short _{operand = operation a} The Boolean expression reads FCRP1 Set (CDUCMD 301 ° FRDP1 <, (D1SQQVP

+ D2EQ0VP + LONG)) ° FPOA) FCRP1 reset (FPOA)
Set by a firmware command DUCMD 305 or by an FCZO symbol for a check = zero / overflow operation _p and reset by a command DUCMD 205 or 314 _O Remain in the set state during the entire operation processing o The BoQl expression is

FCRD set C (DUCMD 305 + FCZO) ₀ FPOA) FCRD reset (DUCMD 314 -j- DUCMD 205 + FPOA) Set by a firmware command DUCMD 304 or 305 to check for zero / overflow of the in the RCHO = register 720 = 10 saved word "The Boolean expression is s

FCZO setting ((DUCMD 305 + DUCMD 304)) ° FPÖA) FCZO reset (SFCZO + FPOA) Set for 9-bit = decimal digits = Loads in alternating cycles to two 4-digit words from cache 750 and in the RDOD register 730 = 154 as an 8-digit word

030028/0876

FDATA-AV

If ¹ DlD

Vt

The Boolean expression is:

FDADIS Set: ((ZTNSAO «FRDP2 + ZTNSBO

• FRDP2) .DATA-AV-FPÖÄ · SF0P2LB) FDADIS reset: (SFDADIS. (SRDI-PC + SFDFD

+ FDFD-RFDFD) + SF0P2LD)

is set to load the RDOD register 730-154 by controlling the strobe signal SRDODA. Of the Boolean expression is:

FDATA-AV set: (DATA-AV «FPÖI) FDATA -AV reset: SFDATA-AV + FPOA) is set during a load operation to indicate that the complete operand has been taken from the cache memory 750 by the decimal unit 730 ;. The Boolean expression is:
FDFD Set: (DFCO'EDID- (RFDFD) «FPÜA · (FOP1LD

• SF0P2LD + F0P2LD)) FDFD reset: (FPOA + DFCO * FDID · DTECO

- [SRDODA + DFCO · FDID. FDTED + DTECO. ■ SRÜOUA-FDFD)

Set when operand data is loaded into RDID registers 730-158. The Boolean expression 3aitefc: Set FDID ((SRDI-PC · FLDREWR · FRDP1) FDID reset: (SFDID) Set if an operand overflow is detected during a check zero / overflow operation, and reset by DUCMD 205. The Boolean Expression is %

FDOFL seters ((DUCMD 305 + FCZO) ° DÖPL.FP "ÖA) FDOFL reset: (DUCMD 205 + FPOA) Set when all decimal digits of the operand have been sent to the execution unit 714 and not all of the operand information has been received by the decimal unit ; for example the exponent or sign information _e

030028/0876

FFOSD

Set when the first data word to be stored in the cache memory 7!? U is loaded into the RDOD register 730 = 154 _o The Boolean expression is s FFOSD Set; ((FOPSTR + DUCMD 303) ° SRDODA

FILLY

FLDCOMPL

FFOSD reset (FPOA) Set ^ if an illegal digit or an illegal length is included in the decimal unit 730. This becomes the System signals an error and the FLDGR flag is reset one cycle later ,, The Boolean expression is s

Set FILLDIG ((SRDODAo (FOPILD + F0P2LD)

• DZIDEQID + ILLEGALLENGTH ° (SF0P1LD + FCZO)) ο (FLDGR

+ FPOA))

FILLDIG Reset (FLDGR + FPOA) Set if both operands belong to the execution unit 714 have been transferred “The Boolean expression reads; Set FLDCOMPL (((F0P1LD ° FMVN + F0P2LD

-SRDODA + DFCOoFDIDoFDTED + DTECOoSRDODA "FDFD) + DUCMD 302) · FPOA) FLDCOMPL reset (FPOA)

Set at the point in time at which the FILLDIG = indicator is included in the decimal unit 730 , doho if an illegal digit or length is included there »FILLDIG is reset one cycle later _o The Boolean expression is

030028/0876

FLDRi) WR

FLDREWRH

FMSDRGTE

FMSDRN

Set FLDGR ((SRDODA- (FOPILD + F0P2LD) • DZIDEQID + ILLEGALLENGTH »(SFOP1LD + FCZO)). FFOT) FLDGR resetJ (FPOA)
Set by the firmware by a load rewrite data signal DUCMD 306 to start the sequence by which the first or last word specified by descriptor 3 in REWR 0-3 register bank 730-177 is stored. The Boolean expression is:
Set FLDRETO (DUCMD 306)

FLDREWR reset; (DUCMD 306) One cycle after setting the FLDREWR flag set to the first or last word in register REWR2 or REWR3 of RBWR 0-3 register 730-177 during a Key in descriptor 2 memory operation «The Boolean expression is: FLDREWRH Set: (FLDREWR)

FLDREWRH Reset: (FLDREWR) During a memory operation to a Firmware command DUCMD 303 is set when the word count is in the RRWC register is greater than or equal to the word counter position in the RWPC register at the time at which the DUCMD 303 instruction is used will. The Boolean expression is: FMSDRGTE Set: (DMSDRGTE · DUCMD 303) «FALT

• (DUCMD 303'RRWCO + FMSDRN)

• FPÖT)
FMSDRGTE reset: (FPOA)

Set on the firmware command DUCMD 303, for the storage of a long Operands if the word count in the RRWC register is initially negative. The Boolean expression is:

030028/0876

FOPILD

FMSDRN set CDUCMD 303-RRWCO ° FPÖA) FMSDRN reset CFPOA;
Set during a memory sequence to store a long operand, if

the creation of words in the RRWC register

is the same as the word counter position in the RWPC register »The Boolean expression reads; FMSEQ set CDMSEQ CFSWRTο DMSDRGTE + FSWRT ο CZTNSAO + ZTNSAO FCPCOJ j ⁰ CDUCMD 303 + FOPSTR) = FATt

⁰ CDUCMD 303 ° RRWCO + FMSDRNj

ο FPOAJ

FMSEQ reset (FPOAj
Set for a numeric move command (Move) »The Boolean expression is

FMVN setting CDUCMD 3OO ° FPOP1D)

FMVN reset (FPOA)

Set for multiplication and division

Instructions _o This indicator is suppressed

the scale factor alignment and does the

Right-justified operands on a load operation

hin ₀ The Boolean expression is

FMYDV setting (DUCMD 200-FP0P1D)

FMYDV reset (FPOA)

Set for the 0perand ~ 1 load operation “The

Boolean expression reads

Set F0P1LD (DUCMD 301 FRDPI = FPOAo (D1EQOVP

c DJ EQOVP LONG + F.CRP1))

F0P1LD reset (FPOA + F0P1LD-DFC0 ° DTECO

° FDIDoSRDODA + F0P1LD ° DFC0 "FDID FDTED + F0P1LD" DTECO ο SRDODA "FDFD)

Set if the operand 1 is equal to zero ₀

The Boolean expression is

F0P1Z setting (SRDODA ° FOP1LD ° DZIDEQZ'FPOA)

F0P1Z reset (FPOA)

Q30028 / 0876

FOPSTR

FOP 2F

F0P2LD

Through the memory operand DUCMD 303 via

the firmware command of the decimal unit 730

set. The Boolean expression is:

Set FOPSTR: (DUCMD 303'FPOT)

FOPSTR reset: (FPOA)

Set for an operand-2 load, and for

the case that the first data word in the

RDID register 730-155 is included. Of the

Boolean expression is:

F0P2F Set: (FDID • FOP2LD.FPÖA · DFCO)

F0P2F Reset: (FPOA + DFCO FDID)

Set for the operand 2 load operation.

The Boolean expression is ι

F0P2LD Set: ((FOP1 LD »FM. (DUCMD 301

+ FRDP2) (DFCO, EDID-DTECO • SRDODA + DFCO · FDID · FDTED + DTECO SRDODA.FDFD) Ί & ΌΡ1 LD ♦ FMVN · DUCMD 301 «FRDP1) .FPOT)

F0P2LD reset: (FPOA + F0P2LD (DFCO.FDID

• DTECO.SRDODA + DFCO-FDID • FDTED + DTECO.SRDODA-FDFD)) Set upon an operand 2 load operation when the second word in RDID register 730-158 is stored. The Boolean expression is: F0P2S Set: (FOP2FFDID.FPOT) F0P2S reset: (FPOA)

Set when operand 2 is zero. The Boolean expression is? F0P2Z Set: (SRDODA'F0P2LD.DZIDEQZ · FPOA) F0P2Z reset: (FPOA)

Set if the operand 1 or the operand is designated as a floating point operand. Of the Boolean expression is:

Set FPFL: ((D1EQFLT + D2EQFLP) F0P1LD «FP0Ä)) Reset FPFL: (FPOA)

030028/0876

FRDIDH

FRDP2

Set by a firmware command DUCMD 309, lim the rounding constant in the RDOD register 730-154 · zu leseru The Boolean expression is? Set FRCMD (DUCMD 309 ° FPOA) FRCMD reset; (FPOA)

Set to indicate that the requested information is not stored in cache 750 is and that the cache memory must request this information from the auxiliary memory = When the data is cached and sent out to the decimal unit 730, the FRDIDH tag combines the recovery signal for keying the data into the RDID register 730-158 “The Boolean expression reads s

FRDIDH Set? ([SRDI-PC)
FRDIDH Reset: (FRDIDH) Is set by the firmware commands DUCMD 301 or DUCMD 302 to indicate that the command for reading out the first operand has been sent to the decimal unit 730 »The Boolean expression is s

FRDP1 set; ((DUCMD 301 · (D1EQOVP »D2EQ0VP "LONG + FCRP1) + DUCMD 302)

FRDP1 reset; (FPOA)

Set by a firmware command DUCMD 301,

when the FRDP1 flag is set to

to indicate that the command is for reading

of the second operand to the decimal unit

has been delivered «, the Boolean expression

reads s

FRDP2 set; (DUCMD 301 »FRDP1 ° FPÖA)

FRDP2 reset; (FPOA)

030028/0876

FREWR2

F3DESC

FP0P3D

SQ

Is set by the FLDREQRH flag in the cycle that follows the setting of the FLDREQRH = flag »The flag is used to read out the rewrite = data from REWR2 and REWR3 during the operand storage process. The Boolean expression is.
FREWR Set? (FLDREWRH «FPÜA) FREWR Reset; (FPOA) Is set by the two set indicators FREWR and FLDREWRH. The command causes the REWR3 register to be used to provide the rewrite data for the last word of operand 3. The Boolean expression is: FREWR2 Set: (FLDREWRH · FRlSWRοFP07) FREWR2 Reset: (FPOA) Is set for the descriptor 3 ~ operation _o The Boolean expression is:

F3DESC Set: (FPOP RDESCO RDESC1) F3DESC Reset: (FPOA) Is set for the cycle that follows the FP0P3 cycle of the control logic unit 704-1. The Boolean expression is:

FP0P3D Set: (FPOP RDESCO.RDESCT)

FP0P3D Reset: (FPOA + FP0P3D (DUCMD

+ FCZO))

Is set for the status that the set length, the length plus the scale factor difference, is greater than 63 characters. The Boolean expression is: FPTL Set: (ALNSLTE63 F0P1LD-FPÖA) FPTL Reset: (FPOA)
Is set to a data transfer command DUCMD 305 from the RCHO to RPK firmware command and for short operation storage

030028/0876

FSSFD

FSWRT

FP0P1D

300,000

exploited The Boolean expression is? FRPK Law;

(DUCMD 305 ⁰ DIEQFLP = FPOA) FRPK reset? (FPOA + DUCMD 205) Is set ρ when the send data bit is sent as a 1 bit »The send data indicate to the firmware that a new word is to be loaded into the RCHO register 720-10 while a long operand is being stored.« The FSND => The identifier causes the word previously stored in the RCHO register to be keyed into the RPK = register 730-162 <, The Boolean expression is? FSND set? (FALT »SEND-DATA ° FPOA) FSND Reset? (FALToSEND-DATÄ + FPOA) Is set if the scale _{factor difference is negative 0} The Boolean expression is? FSSFD set? (ASF2oFDUACT »FRDP1) FSSFD Reset? (ASF2 · FDUACT.FRDP1 + FPOA) Is set when the signal STRT-WRT for the firmware is issued as a 1 signal To begin the procedure that concerns the storage of a long operand “The FSWKT command informs the DU hardware control device that the firmware is issuing write commands 6 The Boolean expression is? FSWHT set? (FALT ° STRT-WRTο (DUCMD 303

+ FOPSTR) ° FPOA) FSWRT Reset? (FPOA) Is set for the cycle "which follows the FP0P1 cycle of the control logic unit 704-1" The Boolean expression is?
FP0P1D set; (FPOP · RDESCO · RDESC1) FPOP1D Reset? (SFPOP1D)

030028/0876

FTDBO are set as a 2-bit counter to the number FTDB1 of the delay cycles for keying in the operand word into the RDOD register 730-154 count down for transfer to execution unit 714. The Boolean Expression reads:

FTDBO Set: CTDBO-DUCMD 301 FPÖÄ) FTDBO reset: (TDBO-DUCMD 30I + (F0P1LD

+ F0P2LD) .DUCMD 301 · SRDI-PC + FPOA) FTDB1 Set: ((TDBl-DUCMD 301 + FTDBO

• (FOPlLD + FOP2LD) -DUCMD 301

• [SRDI-PC) 'FPOA)

FTDB1 reset: (TDHfT-DUCMD 301 + FTDBl

• (FOPlLD + FOP2LD) · DUCMD • [$ RDI-PC + FPOA)

FZCF Is set during the operand loading procedure when the first non-zero character is determined in the input data. It indicates the end of the number of leading zeros in the operand »
FZCF Set: CtSRDODÄ- (FOPlLD + FOP2LD)

FZCF Reset: (SF0P2LD + FPCA))

The following are the Boolean expressions for functions not previously described:

SFCZO - (DUCMD 3 05 + DUCMD 304) fTpOA

SFDADIS - (ZTNSAO «FRDP2 + ZTNSBO-FRDP2) · DATA-AV · FP" ÖÄ • SF0P2LD

SFDFD «DFCO-FDID- (RFDFD) -FPOT

SFDATA-AV «DATA-AV-Pp15A *

[$ RDI-PC - ENABIZ + FTRF + FHT- (SSKBCTF- (RDIN.EQ. (1-11)) + TYPE · (MISREG.EQ.4) + TYPD- (IBUF.EQ.3)) + FMT - ((IBPIPE.EQ.1) -FE12 + TYPBD (2) - (MSKD.NEQ.0) + TYPBD (3) -STL) + FREQCA- (RMEM-Eq ₁ (S-IO)) + FREQDI + FDIDBL

030028/0876

SFDID "[SRDI-PC · FLDREWR-FRDPl

DOFL indicates an overflow condition

DZIDEQID - (ZID4-UID5 + ZID6)) + (ZID8- (ZID9 + ZIDlO)) + (ZID12 (ZID13 + ZID14)) + (ZID16 (ZID17 + ZID18)) + (Z1D20- (ZID21 + ZID 22)) + (ZID24 - (ZID25 + ZID26)} + (ZID28 (ZID29 + ZID30)) + (ZID32- (ZID33 + ZID34))

ILLEGALLENGTH «ALNDAO + ALNDBO + ALNDAZ + ALNDBZ

DZERO indicates that the operand word contains only zeros. Decimal unit - logic

The scale factors for operands 1, 2 and 3, also referred to above as scale factors, are used in the Decimal unit 730 via a 4-position switch ZSFN 730-2 from the control logic unit 704-1, via the signal lines RSIR 24-29. The concerned Scale factors are stored in registers RSFO, RSF1 and RSF2 of register bank 730-4. The signal lines ZADSP 3-11 send the scale factor to position 1 of the switch when the scale factor has been changed by the firmware is calculated. The signal lines ALNDA give the set length of the operands to position 2 of the Switch off during a floating point operation. The signals AEDC and ZEDC are set to position 3 of the switch issued to store the number of effective digits during a floating point operation. This process will as part of the store operation.

The switch positions 730-2 selected. The Boolean expressions are:

[iZSFN = ((F3DESC + FMVN) * FLDCOMPL * FPÖP * (DI EQFLP + DUCMD 305 + FCZO;)

(2ZSFN = ((F3DESC + FMVN) .FLDCOMPL ⁰ FToT ⁴ DIEQFLP)

030028/0876

© AD ORiGiMAL

For non-floating point operands, the operand becomes 2 scale factor selected by the RSF1 position of a ZSFB switch 730-8 and an input of an ASF adder 730-10 supplied, in which the operand-2 scale factor of the Operand 1 scale factor is subtracted from the RSFO position of a ZSFA switch 730-6 is selected. When the operand 1 scale factor is greater than the Operand-2 scale factor, then the signals are ASFO-9 indicative of a positive number, and the bit position ASF2 is given by a logic 0 signal. If the Operand 2 scale factor is larger, then the Signals ASFO-9 have a negative number, and bit position ASF2 carries a logic signal 1.

The length or the number of numeric characters for the operands 1, 2 and 3 is determined via the signal lines RSIR 30-35 received by the control logic unit 704-1 and in the registers RLNDO, RLND1 and RLND2 of a register bank 730-12 saved. An ALNDA adder 730-18 and an ALNDB adder 730-20 calculate the number of decimal digits in operand 1 and operand 2. This is what makes made that the number of non-digit characters in the operand, such as signs and exponents, depends on the Length is subtracted. The output of a decoding logic 730-38 and decoding logic 730-40 becomes an ALNM adder 730-18 and an ALNDB adder 730-20, respectively to set the lengths of operands 1 and 2.

The sign and decimal type for operands 1, 2, and is received via the signal lines RSIR 21-23 from the control logic unit 704-1 and into the register RTNSO, RTNS1 or RTNS2 of register bank 730-32 loaded. A ZTNSA switch 730-36 selects this in the RTNSO register and outputs the stored operand 1 signs and the decimal type stored in this register Information to the decoding logic 730-38. An under-

030028/0876 BATH ORIGINAL

An unsigned operand or operand with a scale factor leads to a zero output signal, while a signed operand with a scale factor results in a 1 output signal; a Floating point operand with 9-bit decimal digits results in a 2 output signal, and a floating point operand with 4-bit decimal digits result in a 3-output signal from decoding logic 730-38. The output value is subtracted from the operand 1 length in the ALNDA adder 730-18, in order to receive the signals ALNDA 0-6 as the output variable, which indicate the number of decimal digits in the Display operand 1. The number of decimal digits in operand 2 as indicated by the ALNDB 0-6 signals are calculated in the same way.

The signals DBITX and DBITZ indicate as logic signals 1 that a binary signal 1 from the ALHDA adder 730-18 or from the ALNDB adder 730-20 is subtracted. The Boolean expressions are:

DBITX = ((ZTNSA1 «ZTNSA2) + (ZTNSA0« ZTNSA1 «ZTNSA2)) DBITZ = UZTNSBVZTNSB2) + (ZfNSBO-ZTNSBI «ZTNSB2))

The signals D1EQFLP and D2KQFLP indicate as logic signals 1 that a binary two from the ALNDA adder 730-18 or subtracted from the ALNDB adder 730-20 will. The Boolean expressions are:

D1EQFLP = (ZTNSA1-ZTNSA2 · CZTNSAO + ROP1)) D2EQFLP = CZTNSB1 ΖΤΝ3Β2 (ZTNSBO + R0P1))

ROP1 indicates an overlaid sign command.

A ZALND switch 730-22 selects the set length of the operand with the larger scale factor and outputs the output signal to an ALNS adder 730-24 from which the relevant signal to the absolute value of the scale factor output signal ASF 0-9 of the adder

050028/0876

BAD ORiQiNAL

ASF 730-10 added. The bit position ASF2 selects the operand with the larger scale factor. the Bit position ASF2 indicates, when it carries a logic signal 1, that the operand-2 scale factor is bigger.

From the output of a ZLNADJ switch 730-26, the set Length fed to an ARWC counter 730-60 and an ACPR counter 730-62. The inputs or input signals for the ZLNADJ switch 730-26 are described below.

If the operand 1 scale factor is larger, then choose the switch turns off the input signals ALNS 0-9 for the operand and the input signals ALNDB for the operand 2. if the operand 2 scale factor is larger, then the selects Switch off the input signals ALNDA-O-6 for operand 1 and the ALNS input signals for operand 2. A Floating point operand or a multiply or divide instruction therefore does not require scale factor alignment, where the input signals ALNDA 0-6 and ALNDB 0-6 for operand 1 and for operand 2, respectively to be selected. The input signals RLZCt become during the occurrence of a floating point memory operand selected; they provide the number of leading zeros in the operand.

The control signals 41ZLNADJ and 42ZLNADJ select one of four positions of the ZLNADJ switch 730-26 from »The Boolean expressions are

(IZLNADJ - (FLDCÖMPL · FRDPl- (PSSFD + FMYDV + DlEQFLP + + D2EQFLP + ALNS 2} + l'LDCOMPL (F 3Di) SC + ■ FMVN) DlEQFLP FDOFL)

[2ZLNADJ - (FDOACT · FRDPl · ÄSfT + FRDPLFSSFD)

DlEQFLP.D2EQFLP + ALNS2 FLDCOMPL

+ FLDCÖMPL (F3DESC + FMVN) .DlEQFLP + DlEQFLP - FDOFL)

030028/087

If the output signals of the ALNDA adder 730-18, the ALNDB adder 730-20 and the ALNS adder 730-24 are all given by fifteen decimal digits or less, then this indicates that there are no floating point decimal instructions are or will be executed in short operand mode. This mode of operation leads to an increased System throughput with regard to the processing of decimal commands compared to the known arrangements, since most of the operand manipulation takes place using a logic arrangement, which executes many of the operand setting functions in parallel. There are many in the previously known arrangements the functions have been executed serially. The Boolean expression for the short operand is:

Short = ( ALMDAl.ALMDA2) (ALNDBl-ALkDB2) (ÄLNSJ. ÄLNST • ALNÖT + FMYDV) (DlEQFLP + D2EQFLP)

It should be noted that the scale factor setting for multiply or divide instructions or commands are not executed »

The ARWC adder 730-60 calculates the number of words to go to the execution unit 714 for short and long Operands are to be transferred. The ONE / ARWCB signal becomes fed to the minus input of ARWC adder 730-60; when this signal occurs as logic signal 1 ;, becomes it is subtracted from the signal ZLNADJ 0-9 relating to the set length for a load operation it is ensured that when the set length as indicated by the signals ZLNADJ 0-9 - by eight decimal digits was given, which means that the signal ZLNADd 6 was a 1 signal, a one subtracted becomes, whereby the ßitposition ARWC6 receives a zero and which loads the eight decimal digits into the first word. Disregarding the bit positions ARWC7-9 the bit position ARWC6 remains, which is the number of

030 0 28/0876

Indicates words for the short operand. A one in bit position ARV / C6 indicates a short operand of two words and a zero indicates a short operand of one word. The Boolean expression for the control signal ONE / ARWCB is:

(ONE / ARWCB »(FLDCOMPL + CZ7FT5XE IrÖPI + ZTNSAtJ

+ ZTNSA2)) + (FRPK * ZLNADJ7 * ZLNADJ8

• ZLNADJ9 'FLDCOMPL))

The output signals ARWC 0-6 indicate the number of words in the operand that are available for the firmware, when the execution control memory 701-4 sends out a firmware word which is contained in the decimal unit 730 as a command or signal DUCMD 311 is decoded (add operand word counter setting to the RDOD signal). In addition, the Word counter setting via a ZLZC switch 730-76, via position 3 of a ZID switch 730-150, via the Position 0 of a ZDOD switch 730-152 for an RDOD register 730-154 is made available from which the relevant counter position to the execution unit 714 is transmitted.

The ACPR adder 730-62 subtracts the set length in decimal digits, which is indicated by the signals ZLNADJ 0-9 are decoded by the decimal value 64. The size 64 represents the maximum number of digits in an operand that processed by the decimal unit 730. The resulting output signals ACPR3-9 give the number of zero digits to the left of the most significant digit position for the 64-decimal-digit operand. This value will stored in an RLMP register 730-102. The bit positions RLMP4-6 store a binary code that represents the Indicates the number of significant positions in the first word of the operand recorded by the decimal unit 730 has been taking these positions to zero

030028/0876

are doing. The signals RLMP 4-6 are used by a ZIDMU sliding device 730-130 fed »The number of significant digits to the left of the Most significant digit positions that are to be set to zero are determined by the number of consecutive Signals are displayed that begin with the ZIDMU 0 signal, which are output as zero signals. the Signals ZIDMU 0-7 are sent to an EZID link control device 730-132 delivered. The output signals EZID 0-7 suppress the output signals of the ZID switch 730-150 to zero, and also give it the digit positions of the ZID switch 730-150 starting with the digit position of the highest value are free. Of the Part of the RLMP register 730-102 which stores the bit positions RLMP 0-3 has the property of each Operand word to be increased or incremented, which from the decimal unit 730 to the Signal CNTUP-RLMPU is received. The Boolean expression is:

[CNTUPRLMPU »((FOPlLD + FOP2LD) · [$ RDÜDA'SFOP2LD) The Boolean expression for the ONE / ACPNBB signal is:

[ONE / ACPNBB - (ZTNSAl (RÖTT + rZTNSAO + ZTNSA2) ((FDUACT.FRDPl) + FLDCOMPL ■

• ZLNADJ7.ZLNADJ8.ZLANDJ9)) + (ZTNSBl (HOPl + ZTNSBO + ZTNSB2}) - (FRDPl

• FLDCOhPL)}

An ATMP adder 730-30 calculates the number of zeros to the right of the least significant digit of the operand with the larger scale or scale factor. The ZASFB switch 730-28 selects the set Scale factor binary signals ASF 0-9, which are added to the size, provided the operand 2 scale factor is larger, or there is a subtraction from size 63 if the operand 1 scale factor is larger.

030028/0878

The output signals ATMP 3-9 are stored in an RTMP register 730-100 loaded. The bit positions RTMP 0-3 store a binary count of the number of Words of the operand to the left of the word that has the digit position of the lowest significance. the Bit positions RTMP4-6 store a binary number which indicates the bit position of the lowest significance. The signals RTMP 4-6 indicate the number of zeros to the right of the least significant digit.

A comparator 730-104 compares the signals RTMP 0-3 and RLMP 0-3. The difference, which is equal to the number of Words of the operand is received from cache 750 by decimal unit 730. The binary word counter position RLMP 0-3 is increased or incremented every time a word of the operand is inserted into the RDOD register 730-154 is loaded. The difference between the binary signals RTMP 0-3 and RLMP 0-3 is Zero if the last word of the operand is included in the decimal unit 730, causing the output A = B of the comparator 730-104 is enabled. This makes the output signal TMSC 0-3 of the TMSC logic controller 730-106 released; this output signal is a binary counter signal of the number of zeros on the right side of the lowest significant digit. This counter setting becomes the TMSC link controller 730-106 fed by the RTMP 4-6 signals. The counter setting TMSC 0-3 becomes a ZIDML shifting device 730-120 supplied. The number of low-order digit positions to the right of the Least significant digits to be set to zero are determined by the number of consecutive Signals displayed that are brought to zero starting with the ZIDML signal. The signals ZIDML 0-7 are delivered to the EZID O-7 link controller 730-132. The output signals EZID 0-7 give the

030028/0876

Signal states of the signals ZMIDL 0-7 and indicate the positions of high significance of the ZID switch 730-150 free, which means the lower significant positions on the right side of the digit are lowest Valence can be made zero.

The signals ASFA 33-36 are received by the address generation unit 704-3 for the operands 1, 2 and 3 and _{stored in the registers RCPO 5} RCP1 and RCP2 of a register bank 730-42 »

The ASFA 33 signal indicates the least significant bit of the cache 750 address of the high order word of the operand, indicating whether this word comes from an odd or an even number Memory Address Space This message appears when clustering operands with 9-bit characters that are in the decimal unit 730 are included, with 4 decimal points per word to 8 decimal points per word, which is delivered to the execution unit 714 will.

In the case of 9-bit operands, the signals ASFA show 34 and 35 indicates the position of the leading character in the high order word of the operand. With 4 ~ bit character operand words show the signals ASFA 34 = 36 the Position of the leading character in the high-order word of the operand.

The operand pointer stored in the RCPO register is activated via the RCPO position of a ZCPA switch 730-44 selected and fed to a ZCPNB switch 730-48 “Die Position ZCPA 0-2 of ZCPWB switch 730-48 is selected if the operand 1 contains 9-bit characters, and the position ZCPA 1-3 is selected if the operand has 4-bit characters. The ONE / ACPNBB signal

030028 / Q876

is fed to one input of the ACPNB adder 730-50 and, in addition, 0-2 is added to ZCPNB if operand 1 has a leading sign. this will indicated by the 1 bit of the RTNSO register as a zero bit. The output signal ACPNB 1-3 of the adder points to the decimal digit position of the highest significance of the Word of high significance of operand 1, if this is in decimal unit 730 from the cache memory unit is recorded here.

An ACPDF adder 730-52 subtracts the digit position high significance of the output signal ACPR 7-9 des ACPR adder 730-62. A binary signal ACPR 7-9 shows the number of zeros to the left of the most significant digit in the high-order operand word, which is to be transferred to the execution unit 714. The subtraction of the binary signals ACPNB 1-3 from ACPR 7-9 in the ACPDF adder 730-52 results in a binary value output signal ACPDF 0-3, which is the size of the operand taken from cache 750 and is shifted so that it is properly aligned to the execution unit 714 to be transferred. This shift value is stored in an RDSC register 730-58 via a switch 730-56. The output signal of the RDSC register 730-58 is sent to a shifting device 730-156 via a ZDSC switch 730-72 submitted. The ACPDF adder 730-52 performs a calculation separately for operand 1 and for operand 2 and aligns the operands relative to one another in order to enable numerical processing in the execution unit 714 to be able to make.

A ZCPWC switch 730-46 selects the operand pointer for 4-bit and 9-bit character operands and outputs the relevant pointer to an ACPWC adder 730-66, in which a magnitude is subtracted from one

030028/0876

BATH ORIGINAL

to provide an output signal ACPWC 0-3. A ZLNT switch 730-64 selects the operand 1 length for the loading of operand 1 and the operand 2 length for loading operand 2 for input purposes to an ASWC adder 730-68, in which the relevant variables are added to the binary signal ACPWC 0-3 will. A ZSWC switch 730-70 selects a switch position ASWC 0-4 for a 9-bit character operand and a switch position ASWC 0-3 for a 4-bit character operand and outputs the binary output signal ZSWC 0-4 for storage in an RSWC register 730-110.

The RSWC register 730-110 stores a binary count of the number of words in the operand, the is to be transferred from the cache memory 750 to the decimal unit 730. The count in the RSWC register 730-110 is decreased by a signal CNTDWN-RSWC each time a word in the RDID register 730-158 is recorded. The Boolean expression for the signal is:

[CNTDWN-RSWC - (ILDRRWC (FDID. (FOPlLD + F0P2LD)

• DFCO + [$ RDODA. (DUCMD 30 3+ FOPSTR))) [LDRKWC - (FDUACT · FREpT + SF0P2LD

+ FLDCOMPL * (FOPSTR + DUCMD 30 3)) DFCO - ISWCU "· RSWCl. RSWC2 · RSMC3 · r3Wc4 [SRDODA »(FDATA-AV + DUCMD 20 3+ DUCMD 310 + DUCMD 309 + FRPK · DUCMD 30 3 + FRPK-FALT

• FSWRT) .DUCMD 311

The RSWC register 730-110 at zero indicates that all of the words in the operand have been taken from the decimal unit have been; the DFCO output signal sets the FDFD code » character in the status code control logic 730-202 »

030028/0876

The ARWC adder 730-60 provides the output signals ARWC 0-6 which are stored in an RRWC register 730-88, \ rerm. the signal LDRRWC is a logic 1 signal. The RRWC register 730-110 stores the number of words in the operand to be transferred to the execution unit 714 during the load operation. Each time a word of an operand is loaded into the RDOD register 730-154, the content of the RRWC register 730-110 is decremented by one if the signal CUTDWN-RRWC is a logic 1 signal. The Boolean expression is:

[CNTDWN-RRWC - (DTECO. (FOPlLD + F0P2LD) · [$ RDODA ' + ((FOPSTR + DUCMD 303- (BHSMSfE + (DMSEQ.RDSCO))). FÄLT- (FSWRT

• DMSDRGTE + (ZTNSAO · FCPCO + ZTNSAO)

• FSWRT)) «FRPK + FRPK-DUCMD 30.1

• (ZTMSAO-FCPCO + ZTNSAO)) DTECO - RRtoCÖ. RRW (Ul ÜRSfcT RRWC3 RRWC4 RRWCS RRWC (

The RRWC register 730-110 at zero indicates that all decimal digits of the operand are sent to the execution unit have been sent out by the DTECO output signal, by placing the FDTED flag in the status flag control logic 730-202 is set.

The FOPILD flag is set by the firmware, whereby the delivery of a signal DUCMD 301 is triggered. This indicates an operation that is reading a Operands related to the decimal unit. The FOPILD mark is reset when the output signals DFCO and DTECO indicate that the two registers, ' namely, RSWC register 730-110 and RRWC register 730-88, reset to zero during the operand 1 load operation have been. The FRDP1 flag series indicates that the DUCMD 301 command has been issued to the

030028/0876

Read operand 1 via deciraal unit 730 »

The F0P2LD flag is set by the firmware to read operand 2 when the DUCMD with the FRDP1 indicator set, " The F0P2LD flag is reset and the FLDCOMP flag is set to indicate that the load operation is complete when the two registers RRWC and RSWC during the 0perand-2 ~ 0operation have been reset to zero, meaning that both operands 1 and 2 are processed in decimal unit 730 and transmitted to the execution unit 714 have been"

An RLZC1 register 730-96 and an RLZC2 register 730-98 are used to indicate to the firmware the number of zeros to the left of the non-zero digit of the highest significance in operand 1 or _o in operand 2 »Die Register_stellen RLZC1 1 -3 and RLZC2 1-3 are loaded with the output signals Ä ~ RWÜ 4-6 of the ARWC counter 730-60 »This essentially biases the word counter part of the registers RLZC1 and RLZC2, whereby the bit positions RLZC1 and RLZC2 0-3 with the Value of seven words minus the number of words that are to be sent to the execution unit (binary value of the bit positions ARWC 4-6 of the ARWC counter 730-60), with an equalization with the number of words that are not sent to the execution unit 714 «The number of leading zeros to the left of the respective operand is determined at the output of switch ZID 730-150. The ZID 04-35 signals are provided to the load zero count logic 730-182, and the LZC 0-3 output signal indicates the number of leading zeros in the word. The signal LZCO indicates as one that all decimal digits

030028/0876

continue to be zero; a one is added to the registers RLZC1 or RLZC2 in bit position 3, and the next word is picked from cache 750. If the word contains all zeros again, if the signal LCZO is a 1 signal, and a one is again added to bit position 3 and further the next word from the cache memory 750 is picked up. Assume that the next from the Cache 750 recorded word does not contain all zeros. In this case the signals LZC1-3 show the Number of zeros to the left of the first non-zero decimal digit. This becomes the FZCF license plate is set, indicating to the logic that the zero for the left counter position with respect to this Operand is completed. This counter setting is transferred to registers RLZC1 via a ZEDC switch 730-82 and RLZC2 transmitted and stored in the bit positions RLZC1 4-ö and RLZC2 4-6 for the operands concerned.

Those in the RLZC1 register 730-96 and in the RLZC2 register 730-98 stored binary values represent the counting or counting of the number of decimal digits to the left of operands 1 and 2, respectively, in order to fill 64 decimal digit parts that are in the execution unit 714 are reserved for each operand.

The output signals of registers RLZC1 and RLZC2 are supplied to the RDOD register 730-154 under the firmware control via position 3 of a ZLZC switch 730-76. The input signal ARWC of the ZLZC switch 730-76 provides the number of words that are required for a long Operands are transferred. The input signal ATMP provides the word storage space for which the rounding constant is added. The RCZC1 register 730-96 and the RCZC2 register 730-98 for the purpose of loading the The following Boolean expressions controlling register positions of the relevant registers are:

030028/0876

[SRLZClL - tlSRDODA. FOPlLD.FIcT + (DUCMD

+ PCZO) -DEDCZ) ISRLZC2L - (. [$ RDODA. FOP2LD-FZCT + (DUCMD 30

+ FCZO) -DEDCZ) The Boolean expressions for loading the register positions high value of the registers are

(LDRLZC1U ■ SFOPlLD + (DUCMD 305 + FCZO) -DEDCZ [LDRLZC2U - SFOP2LD + (DUCMD 305 + FCZO) -DEDCZ DEDCZ -

The contents of the registers are incremented according to the following expressions;

[CNTUPRLZCIU - [$ RDODA-FOPILD-FZCF-LZCO [CNTUPRLZC2U - ($ RDODA-FOP2LD.PZCF.LZCO SFOPlLD- (DUCMD 301 FRDP1.fTÖX (ÜIeQOVP-D2EQOVP

+ FCRPl))

SFOP2LD - (FOPILD.PmW. (DUCMD 301 + FRDP2) (DFCO .FDID.DTECO. I $ RDODA + DFCO-FDID · FDTED + DTECO * [5RDODA. FDFD) Ψ .DUCMD 301 -FRDPl) FP15A ")

DlEQOVP - (DBlTk-ROPl-2TNSAO) D2EQOVP - (DfilTZ-ROPl-ZTOSBO)

LONG - ALNDAGTE16 + ALNDDGTE16 + ALNSGTE16

• FMYDV + DlEQFLP + D2EQFL? ALNDAGTE16 »ALNDAl + ALNDA2 ALNDBGTE16 - ALNDBl + ALNDB2 ALNSGTE16 - ALNS3 + ALNS4 + ALNS5

030Q28 / Q876

Decimal unit - load operation

Operands are transferred from the cache memory unit 750 to the decimal unit 730 via the signal bus line ZDI 0-35 and transferred to an RDID register 730-158 under firmware control loaded. The firmware triggers a command or a DUCMD 301 command, which reads of an operand is affected by the decimal unit. This sets the indicators FRDP1 and FOP1LD, around the linking device of the decimal unit 730 in to enable the state to receive operand 1 from cache memory 750.

The number of words to be picked up from cache memory 750. The RRWC register 730-88 becomes di · - number of words to be sent out to execution unit 714. RSWC register 730-110 is checked for content decreased by one for each word taken from cache 750. The RRWC register 730-88 is regarding its content is reduced by one for each word that is sent out to the execution unit 714 will. The Boolean expressions for loading and decrementing the contents of RSWC and RRWC registers 730-110 or 730-88 are:

[LDRSWC "= ((FDUACT-FRDfT) + (FLDCOMRL-DUCMD 30 3 FOPSTR) + SF0P2LD)

[CNTDWN-RSWC - ([LDRRWC (FDID (FOPlLD + F0P2LD)

• DFCÖ + [$ RDODA- (DUCMD 30 3 + FOPSTR))) [LDRRWC - (FDUACT-FRDPl + SF0P2LD + FLDCOMPL (FOPSTR + DUCMD 30J))

[CNTDWN-RRWC - (DTECO- (FOPILD + F0P2LD) * [$ RDODA + ((FOPSTR + (DUCMD 30 3 (DMSDRGTE + (DMSEQ- RDSCO)))) -FaTTF · (FSWRT

♦ DMSDRGTE + (ZTNSAO-FCPCO -f ZTNSAO)

• FSWRT)) · FRPK + FRPK-DUCMD 30 3

• (ZTNSAÖ »FCPCO + ZNTSAO))

030028/0876

The FOPILD flag is reset in the cycle following the countdown of the contents of the RSWC = and RRWC register to zero by the output signals DFCO and DTECO appearing as logic signal 1

follows "The Boolean equations have been set forth above, * This indicates that all 0perand ~ 1-words have been received by the decimal unit 730 and sent to the execution unit 714 ₀ The firmware solves another command DUCMD 301 from which the F0P2LD Plate sets, since the FRDP1 flag is still set, which causes the decimal unit to accept the operand 2 words. The number of words is reloaded into the RSWC register 730-110 and into the RRWC register 730-88 which have been received from the cache memory 750 and which have been passed to the execution unit 714 »Furthermore, the content of the relevant register is counted down to Hull to indicate to the decimal unit 730 that operand 2 has been received, processed and transferred to the execution unit 714 has been »The FOP2LD flip-flop is then reset

The operand can contain 4-bit or 9-bit decimal digits » Operands that contain 4-bit decimal digits are processed differently using the 730 decimal unit as operands containing 9-bit decimal digits »Assume that the operands are words with 4-bit decimal digits and that the first word is stored in the RDID register 730-158- The control signal 1ZPK is emitted as a 1 »signal, whereby the position a ZPK switch 730-160 is selected. The output signal RDID 0-35 is converted from a 36-bit word into a 32 = bit word in the selected position 1 of the ZPK switch 730-16O huddled together and over the signal bus line ZPK 0-31 submitted. This allows up to eight

030028/0876

4-bit decimal digits are displayed. The negated bus line output signal ZPK 0-31 is stored in an RPK register 730-162. The decimal digits of this data word are the high-order digits of the operand. If the decimal digits of the first word of the operand sent to the ZPK switch 730-160 are sufficient Number of decimal digits to be sent out to the execution unit 714, as is done by the logic device the decimal unit is set to 730, then the required switches are set by their causes corresponding control signals to load the RDOD register 730-154. In this case the output signals are grounded ZPKO-31 via a ZPKR switch 730-164 selected. The output signals ZPKRO-31 are used by the shifting device 730-156 fed in, in which they turn right around a size can be shifted by the binary shift counter output signal ZDSC 1-3 of the RDSC register 730-58 is designated. The output signals ZDS 0-31 are fed to a ZID switch 730-150, in which non-decimal digits, such as signs and exponents and also non-operand exchange signs, under the control of the ZID switch release output signal EZID 0-3 of the EZID control logic 730-132 can be replaced by zero. The output signals ZID 4-35 are in position 0 of the ZDOD switch 730-152 selected. The ZDOD 4-35 output signals are stored in the RDOD register 730-154.

If the data word, which consists of 4-bit digits, does not have a sufficient part of the RDOD register 730-154 for transmission to execution unit 714, then the first word remains in the RPK register 730-162 and the next data word of 4-bit digits is transferred from cache 750 to the RDID register 730-158 transferred under firmware control. The second data word is sent to the shifter 730-156 via the ZPK switch 730-160 and the ZPKR switch 730-I64

030028/0876

submitted. The first one stored in the RPK register 730 = 162 Datenvrort is via a ZPKL switch 730-166 output to the shifting device 730-156. 32 of the 60 inputs of the Shifting device 730-156 selected The output signals ZDS 0-31 are in the RDOD register 730-154 via the ZID switch 730-150 and the ZDOD switch 730-152 saved. Required zeros will be left and right added to the sliding device output signal ZDS 0-31 under the control of the release signals EZID 0-7, while the operand word via the ZID switch 730 = 150 is switched.

If the from the cache memory 750 to the decimals · = · The operand returned for the 730 is a 9-bit decimal digit then the first data word, which contains a maximum of four decimal digits, is stored in the RDID register 730-158 saved. The 9-bit decimal digits are grounded from the five Higher-order bits of each decimal digit are freed and as a compact word using the selected position 2 of the ZPK switch 730-160 switched through and either stored in the left 16 bits of the RPK O-15 register 730-162, provided that the digits in question come from an even address in the cache memory 750, or the The digits concerned are stored in the right 16 bits of the RPK 16-31 register 730-162 if they are off an odd address in the cache.

If a data word can be provided to be delivered to execution unit 714, then it is delivered to the sliding device 730-156 via the ZPK switch 730-160 and the ZPKR switch 730-164. It should be noted that the decimal digits are in the ZPK 0 = 15 and ZPK 16-31 switch positions be repeated as the digits are set using the switch ZPK 0-31

030028/0876

get away _o The unrelated digits, the sign, the exponent and the rewrite digits are removed from the data word in the ZID switch 730-150 »The output signal ZDS 0-31 of the shifter 730-156 is in the RDOD register 730-154 via the 0 positions of the ZID switch 730-150 as well as the ZDOD switch 730-150 and the ZDOD switch 730-152.

It is assumed that the first data word, which has 9-bit characters, of one has an even address having memory space of the cache memory 750 and stored in the RPK 0-15 register 730-162 has been and that the second data word from a memory location having an odd address of cache memory 750 and stored in RPK 16-31 register 730-162.

The second data word is sent to the shifter 730-156 via the ZPK switch 730-160 and the ZPKR switch 730-164 issued after the relevant data word of the higher-order five bits of the respective 9-bit decimal digit freed and accommodated or packed in both halves of the data word ZPK 0-31. The first data word, which is stored in either the odd address half or the even address half of the RPK register 730-162 is sent via the ZPKL switch 730-166 to the shifter 730-156.

The control signals 1ZPK and 2ZPK select one of four positions of the ZPK switch 730-160. the Position 0 is selected for the store operation, position 1 is selected for the 4-bit digit operand, position 2 is selected for the 9-bit digit operand and position 3 is selected for the Rounding operations selected. The Boolean equations are:

030028/0876

[IZPK - ZTNSAO-FOPILD + ZTNSBO-FOP2LD + DUCMD [2ZPK »ZTNSAO.FOPlLD + ZTNSBO-FOP2LD + DUCMD

The control signal SRPKU indicates the loading of the RPK register 730-162, the positions RPK 0-15 for 9-bit operands from an even address of the cache memory 750 and free for 4-bit operands “The control signal SRPKL enables the loading of the RPK register 730-162, namely positions RPK 16-31 for 9-bit operands from a odd address of cache memory 750 and for 4-bit operands.

The Boolean equations are;

(SRPKU «DL ¹ CMD 305 + FDID- (ZTNSAO-FOPILd + ZTNSBO-FOP2LD + ZTNSAO - FOPlLD

• FCPCO + ZTNSBO · F0P2 LD · FCPCO)

+ FlM'FOPSTR. (FXEt-fswrt + fold

• FSWRT.FSND))

[$ RPKL «DUCMD 305 + FDID- (ZTNSAO-FuPILD + ■ ZTNSBO. FOP2LD + ZTNSAO · FOPlLD

FCPCO + ZTNSBÖ-F0P2 LD · FCPCO

FOPSTR. (FÄLT-FSWRT + FALT FSWRT.FSND))

The control signals OZPKL and OZPKR give the ZPKL switch 730-166 or the ZPKR switch 730-164 free »The control signal IZPKL selects the logic signal 1 as the Bit positions ZPK 4-31 from the ZPKL switch 730-166 and the bit position RPK 16-31 from the ZPKR switch 730-164 off »The control signal 1ZPKRU selects 1 as logic signal the bit positions RPK 0-15 of the ZPKR switch 730-164.

030028/0876

[OZPKA - FOPlLD + FOP2LD + (FOPSTR + DUCMD 303)

• (FRPK- (DMSDREQlO'RDSCO + DMSDREQOMl

• RDSCO) + FRPK FMSDRN · (DMSDRLTMl + FMSDRGfIT * DMSDRLTM2) 'FMSEQ))

[OZPKR »FOPlLD + FOP2LD + (FOPSTR + DUCMD 303)

• (FRPK '(DMSDREQ21 · RDSCO + DMSDREQ10

• RDSCO) + FRPK.FMSDRN '(FMSDRGTE

■ DMSDRLTMl + RRWCÖ) -DMSEQ) + DUCMD 309

+ DlEQFLP + (ATMP 0-6) * FRCMD

+ (ATMP 0 · 1 · 2 · 3.4 · 5 · 6) .FRCMD)) [IZPKL - (DMSDRQEQl · RDSCO + DTECO-RDSCO) • FRPK · (FOPSTR + · DUCMD 303)

[IZPKRU - (FOPlLD-ZTNSAO + FOP2LD-ZTNSBO) • RDSCl + (FOPSTR + DUMCD 303) -FRPK • (DMSDRTOQl-RDSCO + DTECO-RDSCO)

DMSDREQ10 = DTECO + DMSDRWEQl DMSDRWEQMl - RRWCO · FFWCl · RRWC2-RRWC3 · RRWC4 · RRWC5-RRWC6 DMS DREQOMl · »DTECO + DMSDRWEQM2 DMSDRLTMl - RRWC0 «DMSDRWEQMl

DMSDRLTM2 - RRWCO (RRWCl - RRWC2 RRWC3.RRWC4.RRWC5) DMSDREQ21 - DMSDRWEQ2 + DMSDRWEQl DTECO - RRWCÖ RRWCl RRWC2.RRWC3 RRWC 4 RRWCS RRWCÖ DMSDRWEQl - RRWCÖ · RRWCl · RRWC2 · RRWC3 · RRWC4 · RRWC5 · RRWC6 DMSDRWEQ2 - RRWCO · RrTTcT- RRWC2 .RRWC3 · RRWC4 · RRWC5 · RRWC6

The Boolean expressions for the control signals that the Display operand words during the load operation and the store operation are as follows:

[IZlD - DUCMD 203 + DUCMD 310 + DUCMD 311 + FrTK

'F ¹ RCMD'DUCMD 309
[2ZlD 0-7 "= ■ DUCMD 310 + DUCMD 311 + (FRPlC-FRCMD • DUCMD 309) + ZCRDG-MASK

[IZDODO - ([STRPKD + [UNPKDLWR + [UNPKDUPR ([IZSMRO + [2ZSMRO)

030028/0878

- IYC-.

[IZDODI »((STRPKD + [UNPKDLWR + [UNPKDUPR ([1ZSMR2

+ [2ZSWR2) [1ZDOD2 - ([STRPKD + [UNPKDLWR + [UNPKDUPR ([1ZSMR4

+ [2ZSMR4) [] ZDOD3 ·> ([STRPKD + [UNPKDLWR + [UNPKDUPR ([1ZSMR6

+ [2ZSMR6)

[2ZDOD0 » (4STRPKD + [UNPKDUPR + [UNPKDLWR ([IZSMRO

+ [2ZSMRO)) [2ZDOD1 - (4STRPKD + (UNPKDUPR + [UNPKDLWR ([1ZSMR2

+ (2ZSMR2)) [2ZDOD2 - (4STRPKD + [UNPKDUPR + [UNPKDLWR ([1ZSMR4

+ [2ZSMR4)) [2ZDOD3 "(4STRPKD + [UNPKDUPR + [UNPKDLWR ([1ZSMR6

+ [2ZSMR6)

[IZSMR 0-7 - SIGNMASK + REWUM 0-7 + REWLM 0-7 (2ZSMR 0-7 - EXPMASK + REWTJM 0-7 + REWLM 0-7 [STRPKD = (ZTNSAO (DUCMD 303 + FOPSTR)) [UNPKDLWR - (ZTNSAO (DUCMD 30 3 + FOPSTR) -FCPCO) [UNPKDUPR - (ZTOSAO (DUCMD 30 3 + FOPSTR) TCPCO)

An ACPR adder 730-62 calculates the number of zero digits on the left side of the operand, which are required to fill a 64-digit block of memory. The length-adjusted output signal ZLNADJ 0-9 of switch 730-26 is subtracted from 64, the maximum Number of digits between the decimal unit 730 and execution unit 714 are transferred. The output of the ACPR adder 730-62 is in the RLMP register 730-102 stored The output signals RLMP 4-6, these are the three low order bits, store the number of 4-bit decimal digit positions on the left Side of the word of high value, which are to be given as zeros. The relevant signal is sent to the shift count input fed to a ZIDMU pushing device 730-130 “Those Output signals ZIDMU O-7, which show zero digits on the left side, are thereby set to zero the displayed output signals of the EZID linkage

030028/0876

controller 730-132, namely the signals EZID 0-7, set to zero, whereby the selected digit positions of the ZID switch 730-150 to zero "with respect to of the first word of the operand that is or will be accepted by the decimal unit 730, If the operand had a leading sign, this would be through a zero in the ZID switch 730-150 has been replaced as the sign position count is from the respective operand length in the ALIiDA adder 730-18 or has been subtracted in the ALNDB adder 730-20. In addition, the rewrite characters would be in the operand word has been replaced by zeros.

üin ATMP adder 730-30 calculates the number of zeros on the right side of the digit position of the lowest significance of the operand with the larger scale factor. The ZASFB switch 730-28 selects the number of zeros on the right hand side for operand 1 or for the operand during the cycle in which the operand is transferred from cache 750 to decimal unit 730.

If the operand 1 scale factor is greater than the ¹ operand 2 scale factor, then the input signal ASF 0-9 for the switch ZASFB 730-28 is a positive number which is subtracted from 63 in the ATMP adder 730-30 , and the difference, that is the output signals ATMP 3-9, are stored in an RTMP register 730-100. The low-order digits RTMP 4-6 are fed to a TMSC logic controller 730-106 on the input side, and the relevant signals are output on the output side . Output signals TMSC 0-3 to the shifting counter input of a ZIDML shifting device 730-128. As a result, the output signals ZIDML 0-7 are output, which indicate the number of digit beads on the right-hand side of the operands. The output signals are ZIDML 0-7

030028/0876

BAD ORlGIMAL

delivered to the EZID link controller 730-132. Transfer the output signals EZID 0-7 set the designated lower digit positions of the ZID switch 730-150 to zero, which means that the The sign, the exponent and the rewrite characters are removed from the operand word at the end.

The signals RTMP 0-3 at the output of register 730-100 and the signals RLMP 0-3 at the output of register 730-102 zc? indicate the cycle in which the operand word, which requires a transfer of the zeros to the right, from of the decimal unit 730 to the execution unit 714 will »The maximum transfer of 64 decimal digits is made by eight words with eight decimal digits per word executed. The RLMP 0 = 3 signals are a binary representation of the number of words to the left of the Word that contains the most significant digit that has a total of zeros. The signals RTMP are 0-3 a binary representation of the number of words in the maximum transmission minus the word with zeros on the right side, one plus 1 is added to the binary signals RLMP 0-3 each inside, when the register RDOD 730-154 is loaded, Dio signals RTMP 0-3 and RLMP 0-3 are compared in a comparator 730-104. The signals TMSC 1-3 are shown as zeros in the Cycles in which the binary signals RTMP 0-3 are greater than the binary signals RLMP 0-3, with zeros on the right in the ZID switch 730-150 the transfer cycle are released, the comparator 730-104 indicates that the binary values of RLMP 0-3 and RTMP 0-3 are the same

The control signal SRTMP indicates the loading of the RTMP register 730-100 and the bit positions RLMP 4-6 on the input side of the RLMP register 730-102 free. The control signal SRTMP gives the output or the output signal of the bit positions

030028/0876

BATH

unit 730 sets up the necessary controls in the logic device to accept operand 3, to manipulate it and store it in the cache memory 750, in accordance with its descriptor information.

The operand 3 scale factor signals RSIR 24-29 are the Singang side of the ZSFN switch 730-2 fed and in stored in register RSF2 of register bank 730-4. In the event that the operands on the input side are that the decimal unit 730 has made the scale factor alignments, the ZSFA switch 730-6 selects the content of the RSF2 register and the ZSFB switch selects the content of either the RSFO register or the RSFI register of register bank 730-4. The selected register is the one that has the smaller one Saves the scale factor of operand 1 or operand 2. The FSSFD indicator, which is determined by the scale factor comparison is set during the load operation causes the selection.

The control signals 4WRRSF1 and 4WRRSF1 select one of the RSF O-4 register 730-4, in which the scale factor is stored. The Boolean expressions are:

[WRRSFl " ((F3DESC + FMVN) FLDCOMPL.FPOP-DlEQFLP) (DUCMD 305-FCZO) + RDESCl-FPOP 4- (FMYDV

+ FPTL + FPFL) DUCMD 308-DlEQFLP (FMVN + F3DESC) · Ρρ15ρ "· FLDCOMPL [WRRSF2 - ((FMYDV + FPTL + FPFL) DUCMD 308 * FPOP * FLDCOMPL • DlEQFLP (FMVN + F3DESC) + RDESCO-FPOP + (F3DESC + FMVN) FLDCOMPL * FPOP-DlEQFLP)

The output signal of the ZSFB switch 730-8 is from Output of ZSFA switch 730-6 in the ASF adder 730-10 subtracted. The output signal ASFO-9 becomes

0300 2 8/0876

.ξ 300,000

RLMP 0-3 of RLMP register 730-102 free.

The control signals ZERO / RLMPL enable the outputs of the bit positions RLMP 4-6. The control signal CNTUP-RLMPU increments the bit positions RLMP 0-3 »The Boolean Are equations?

[$ RTMP - (FDUÄCT-PRDPl + SF0P2LD)

[ZERO / RLMPL «(FFDO + (FOPlLD + FuP2LD) · [2ZIDA)) [CNTUP-RLMPU = ((FOPlLD + FOP2LD) · [$ RD0DA · SF0P2LD)

Decimal Unit - Figure 3 - Store Operation

In the FPOP3 cycle, descriptor 3 information is loaded into RSIR register 704-154 in response to a 3 descriptor instruction. In the case of decimal calculation instructions, the descriptor 3 defines the field in which the results of the calculation of the descriptor 1 and descriptor 2 operands are stored. Some instructions store the result of the descriptor 1 and descriptor 2 operand calculations in field _{0 identified} by the descriptor 2. In each case, the RSIR register 704-154 stores the descriptor information and stores it in the decimal unit 730 for the Memory operand 3 operation on "The decimal unit 730 takes the operand 3 from the character unit 720 via the signal bus line RCHU 0-35" The decimal unit unpacks the relevant signals, adds the sign and the exponent to them, if necessary, positioned the operand 3 digits within the word, provides the correct number of zeros on the left and right sides of the operand, adds the required ASCII or EBCDIC zone bits and reproduces the state of the range of the first and last words of the operand her ₉ that have not been specified as part of the operand »The decimal

Q30028 / 0876

BAD ORfGiMAL

fed to the input side of the ALNS adder 730-24 and also stored in the RSCLM register 730-144, in which the signal in question serves as a pointer to the least significant end of the data that is actually are to be saved.

For a floating point store operation, the RSF3 register of register bank 730-4 stores this as to output signal of the ALNDA adder set to the length 730-18, and the RSF2 register holds the effective digit counts of the internal results when the count occurred the first time, which means that the output of the AEDC adder 730-86 and the output ZEDC1-3 of the ZEDC switch 730-82 on the input side of the ZSFN switch 730-2. In this case " the content of the RSF3 register is selected via the ZSFA switch 730-6, and the content of the RSF2 register is selected via the ZSFB switch 730-8, and in the ASF adder 730-10 the relevant values are from each other subtracted. In addition, the output signal ASFO-9 is applied to the input of the ALNS adder 730-24 and the RSCLM register 730-144 supplied. For the purpose of achieving zero or effective digit counting, if the operand is checked the first time, the contents of the RSCLM register 730-144 are overwritten by the input signals for the zero output and the overflow detector logic 730-80 can be formed. After the first count, if the number of effective digits is greater than the set length of operand 3, the decimal overflow indicator FDOFL set, and the calculation of the effective digit count from the contents of the RSF2 register minus the set length from the content of the RSF3 register, at the output of the RSCLM register 730-144 released for a subsequent zero and overflow test.

030028/0876

000006

The length field signals RS1R3O-35 are stored in the register RLND2 of the register bank 730-12 and via the position RLND2 of the ZLJMDA switch 730-1 b to Input of the ALWDA adder 730-18 switched through.

The control signals 1ZSFA and 2ZSFA select the outputs the RSF O-3 register 730-4 for output to the plus input of the ASF adder 730-10. The control signals 12SFB and 2ZSFB select the outputs RSF 0-3 for the Transfer to the minus input of the ASF adder 730-10 from »The Boolean expressions are?

[IZSFA - F3DESC-FLDCOMPL- (FMVN-DlEQFLP) [2 ZSFA * ■■ - * 3DESC.FLDCOMPL + FMVN-FLDCOMPL

• FlEQFLP
[IZSFB - FHvTT.FLDCOMPL + FMVN-FSSFD -FLDCOMPL- (F3DESC + FMVN)

.dleqflp- (fmydv + fptl + fpfl) + fldcompl- (f3desc + fmvn) -d1eqflp + fldcompl- (f3desc + fmvn) -dleqflp - (fmydv + fptl + fpfl) + fldcompl- (f3desc + Fmvn)

[2zsfb -'fldcompl- (f3desc + fmvn) -d1eqflp + fldcompl. (f3desc + fmvn) -dleqflp • (fmydv + fptl + fpfl)

The sign and decimal type signals are RSIR 21-23 stored in the register RTNS2 of the register bank 730-32 and via the RTNS2 switch position of the ZTNSA switch 730-36 to decode logic 730-38 in which the correction factors for length are determined o if the operand 3 is a 9-bit floating point number ;, then become two digits subtracted from the length »if the operand is preceded or followed by a sign then one digit is subtracted from the longitudinal. A 4-bit floating point number means that three Digits to be subtracted from the length. The Boolean

030028/0876

Expressions for the signals DBITX and DIEQFLP corresponding to the ALNDA adder 730-18 and the ALNDB adder 730-20 are supplied have been described above.

The output of the decode logic 730-38 becomes the fed to other inputs of the ALNDA adder 730-18 and causes the subtraction from the signals ZLNDAO-5. At the output of the ALNDA adder, the signals ALNDA 0-6 which set the length in such a way that the number of decimal digits in operand 3 is displayed. the Output signals ALNDA 0-6 are sent via the ZALND switch 730-22 to the input of the ALNS adder 730-24. The scale factor signals ASF 0-9 are added to the ALNDA length and the output signals ALNS 0-9 represents the set length of operand 3. The output signal ALNS 0-9 is via the zero position of the ZLNADJ switch 730-24 delivered to the input adders ARWC 730-60 and ACPR 730-62 and in an RSCUM register 730-78 saved. The adder ACPR subtracts the set length ZLNADJ 3-9 from 64, and its output signals ACPR 3-9 indicate the position of the most significant digit to be stored in the internal result field. The signals ACPR 7-9 indicate the position of the most significant digit within the word of the operand that is the decimal digit contains the highest value. The ACPR 7-9 signals are fed to the input side of the ACPSC adder 730-54.

The output signals of the ARWC-i ^ ddierers 730-76, the when the ARWC signals are 0-6, are applied to the RRWC register 730-88; they show the location of the digit operand word containing the highest significance, which is sent from the decimal unit 730 to the cache memory 750 is to be transferred. A one is given to the ARWC adder in the case of an operand with a leading sign

030028/0876

-ff.

added, which would lead to another Word is transferred to the cache memory 750.

In the sliding conuna operation, during the first check for zero or overflow, doh “when it occurs of the Check Zero Overflow Command DUCMD 304, and at each subsequent check, during which the overflow indicator FDOFL has not been set, the output signal of the ALNDA adder 730-18 is selected via the ZINADJ switch 730-26. If on a floating point output result the decimal overflow indicator FDOFL was set, then the output signal of the ALNS adder 730-24 via the ZLNADJ switch 730-26 selected. The ALIMS adder 731-24 forms the difference between the output signal indicating the set length of the ALNDA adder 730-18 and the effective number count minus the set length from Output signal of the ASF adder 730-10 «

The start character pointer signals ASFA 33-36 are in the Register RCP2 of register bank 730-42 stored; they are in switch position RCP2 of the ZCPA switch 730-44 selected. The ZCPA 0-3 signal is fed to the input side of the ZCPNB switch 730-48. if if operand 3 consists of 4-bit characters, then signals ZCPA 1-3 are selected, and if operand 3 is off 9-bit characters, then the signals ZCPA 0-2 are selected as output signals ZCPNB 0-2, those of the input side of the ACPNB adder 730-50. A one is added to the ACPNB adder if the operand has a leading sign. The output signals ACPNB 0-3 become the input side of a ACPSC adder 730-54. The switch 730-56 selects the ACPSC 0-3 signals for storage in the RDSC register using the FLDCOMPL status identifier 730-58 off. The ACPSC adder 730-54 subtracts

030028 / 087S

the digit with the highest value within the internal operand word, which is indicated by the signals. ■ ACPR 7-9 is designated by the digit position in the memory word of the highest significant digit as it denoted by the ACPHB signal to the value of the The number of digits by which the operand to be stored is or will be shifted. This The value is characterized by the signals ACPSC O-3, stored in RDSC register 730-58; this Value represents the shift counter for the ZDS shifting device 730-156.

The output signals ASWC O-6 of the ASWC adder 730-68 provide the input signals for the ZSWC switch 730-70, for the ZRLr-IP switch 730-112, for the ZSMP switch 730-116 and for the ZEMP switch 730-120. The output signals the switches are attached to the sliding devices 730-114, 730-118 and 730-122 delivered. The slider output signals are sent to the Control 1ZSMR logic 730-142 and to the control 2ZSMR LOgIk 730-146 issued to the signals 1ZSMR 0-7 and generate 2ZSMR 0-7. These signals are provided to the ZSMR switch 730-180 to indicate the sign den Exponents and the rewrite characters in the operand 3 words to load. The start character pointer signals ZCPA 0-3 are fed to the input side of switch 730-46, its output signals, these are the signals ZCPWC 0-2, of the ZCPA 1-2 signals for a 0 Mt character operand while these are the signals ZCPA 1-3 for a 4-bit character operand acts. The signals ZCPWC 0-3 are fed to the input side of the adder ACPWC 730-66. The decimal digit v / ird is subtracted, and the output signals ACPWC 0-3 are applied to the input side of the ASWC adder 730-68. The length field of operand 3, the signals ZLNDA 0-5, is or become the start character pointer minus a one

030023/0876

BATH ORIGINAL

added to display the character pointer for the last decimal point in the operand,

The first word of operand 3 is indicated by the pointer unit 720 via the signal lines RCHU 4-35 and the Buffer 730-168 added, which contains the determination signals RCHU 4-35 and the negated signals or iMegation signals RCHU 4-35 generated.

The control signals 1ZPK. and 22PK select the! Mull position of the ZPK switch 730-160 off, and the signals RCHU 4 = 35 occur at the output of the switch as signals ZPK 0-31 and 0-31.

With a long operand, i. bui operands that are larger or longer than 15 decimal digits, the operand becomes transferred from the RCHU register 72Ο-1Ο, one word being transferred to the decimal unit 730 first will. The word in question contains the most significant decimal digits.

If a sign is required for the operand, the firmware will use the RSGN register 720-134 via the Signal lines ZADSP 3-11 from the auxiliary computing and Control unit 722 is loaded upon the occurrence of a DUCMD instruction relating to loading the DU sign register. The output of the RSGN register 730-14 becomes to the selected position 1 of the ZSMR switch 730-180-delivered. The character position in the ZSMR switch position is selected as follows: »The output signal of the ASWC adder 730-68 points to the character position of the lower value of a subsequent or "attached sign" The output signal of the ZCPA switch 730-44 points to the leading sign position ,, A ZSMP-Sehalter 730-116 selects a subsequent or leading sign for 4-bit or 9-bit operands »The shift counter ZSMP1-3 is connected to a SIGNM sliding device 730-118

030028/0876

submitted. The input link signal O for the SIGNM shift device 730-118 results in the selection of one of the output signals SIGNM 0-7 for 4-bit operands. The logic signal O and the ZTNSAO signals select two adjacent signals of the output signals SIGNM 0-7 for 9-bit operands. The output signal SIGNM 0-7 of the shifting device selects the output signal 1ZSMR 0-7 of the control device 1ZSMR 730-142, which one of eight switch 1 positions of the ZSMR switch 730-180 for the 4-bit decimal digit operand sign or selects two adjacent positions for the 9-bit character operand sign.

The exponent is assigned to the operand on the DUCMD 308 added, which affects the loading of the DU exponent register. An RSXP register 730-138 is taken from the signal bus line ZADSP 3-11 loaded. A ZEXP switch 730-140 selects the exponent bit configuration for an operand with 4-bit decimal point and saves the least significant 4-bit characters in an even digit in the. Cache memory 750 via the 1 position of the ZEXP switch. All other exponents are given by the zero position of the Switch selected. The output signal ZEXP 0-8 is fed to position 2 of the ZSMR switch ZSMR 730-180. The exponent character positions are selected by the output signals 2ZSMR 0-7 from the control logic 2 ZSMR 730-146. The signal is generated as follows. The Boolean expressions for the control signals 1ZSMR 0-7 and 2ZSMR 0-7 have already been given above.

The output signals ASWC 5-6 of the ASWC adder 730-68 line the position of the low-order word of the operand of the low-order character in the case of 9-bit characters. One Binary 1 is subtracted from this value in the ACPE adder 730-74 to place the digit with higher significance of the exponent for an operand that consists of

03002 8/0876

4-bit characters. A 2MIP switch 730-120 selects the character position and the output signals ZEMP1-3 are sent to an EXPM shifter 730-122 submitted. The output signals EXPM 0-7 v / ground to the control logic 2ZSMR 730-146. The output signals 2ZSMR 0-7 select the two adjacent character positions in the ZSMR switch 730-180 to enable the writing of the Free exponents in the word of low order.

For a 4-bit operand, it is for the digit position highest value with the exponent sign possible that this is in digit position 7, and the The lowest significant position can be in the digit position 0 of the next word. In this case the EXPM masking device 730-122 produces a 1 output signal on the signal line ΞΧΡΜ7 when the ZEMP switch 730-120 pointer in the decimal 7 itself while the penultimate word is being recorded. When the last word is recorded, the remains ZEMP switch pointer to 7, and the DBITS input signal is output as a 1-signal, whereby a binary signal 1 is output on the EXPMO line. This will make the Zero character position of the word least significant activated. The Boolean expression for the DBITS signal reads:

DBITS - DFCO (DUCMD 30 3 + FOPSTR) (ACPEl * ACPE2 * ACPE3) DlEQFLP

The signals RDESCO and RDESC1 are applied to the write select inputs of the RLNDO-3 register 730-12, the RTNSO-3 register 730-32 and the RCPO-3 register 730-42 The signals RDESCO and RDSSC1 are binary coded 00, 01 and 10 to identify the operands 1, 2 or 3 »

The control signals 1ZLNDA and 2ZLNDA are sent to the ZLNDA switch 730-16 and to the ZTNSA counter 730 = 36

030028/0876

The status identifier FMVN is sent to the Z LNDB-S ew e 730-20 and handed over to the ZTNSB counter 730-34-.

The control signals 1ZCPA and 2ZCPA are sent to the ZCPA switch 730-44 delivered. The Boolean expressions describing the signals are as follows:

[IZLNDA »F3DESC · FLDCOMPL
[2ZLNDA - F3DESC · FLDCOMPL

[IZCPA - FRDPI · FLDCOMPL + FiDESC · FLDCOMPL [2ZCPA «F3DESC · FLDCOMPL

The output signal ZSMR 0-35 contains decimal digits, Exponents and signs; this signal is delivered to the ZDOD switch 730-152 and into the RDOD register 730-154 loaded for transfer to cache 750.

When storing short operands, the words from of execution unit 714, with the word least significant first and the word most significant last. The command or the DUCMD 305 command (data transfer from RCHO to RPK) is initiated by the firmware. The word lowest Significance is received from the character unit 720 via the signal bus line RCHU 4-35 and in the RPK register 730-162 stored in a buffer 730-168 and the position 0 of the switch ZPK 730-160. if the short operand is two words then the most significant word in the RCHU register will be in the same Cycle housed; it occurs on the signal bus line RCHU 4-35 on the following cycle, across the buffer 730-168 and the position 0 of the switch ZPK 730-160. The signals in question become the

030028/0876

Input side of a ZPKR switch 730-164 and one ZPKL switch 730-166 as signals ZPKO-31. If the short operand was only one word long then zeros are put on the RCHU bus line to be used as Word of utmost importance to serve.

The negated output signals of the buffer 730-168, the Signals RCHU 4-35, are the input side of an output zero and overflow detector logic 730-80 and the effective digit logic 730-81 supplied. During the cycle during which the DUCMD 305 command is present, the least significant word is checked for zero or overflow and the most significant word is checked for Checked zero or overflow in the following cycle, which is marked by the fact that the FCZO flag is in the link state 1 is.

An RSCUM register 730-78 stores the operand 3 length plus the scale factor output of the ZLNADJ switch 730-26. An RSCLM register 730-144 stores the operand 3 scale factor output of the ASF adder 730-10. The output signals of the registers RSCUM and RSCLM become the input side of the logic unit or "logic unit 730-80 supplied"

The zero and overflow detector logic 730-80 masks the non-operand 3 field and indicates to the firmware when the operand 3 field is zero, since the DZERO output signal of the detector logic 730-80 in the case a logic signal is 1 and also there :; Operand 3 field and masks the scale factor field and provides an indication to the firmware in the event that one is non-zero Decimal digit in the character positions on the left side of the most significant character of the operand 3 in the most significant word is present, which means that the DOFL output of the detector logic 730-80 as

030 0 28/0 87

Link signal 1 occurs. The output signals of the registers RSCLM and RSCUM are used to generate the Mask non-operand 3 character positions, and also masks the RSCUM register output the operand 3 and scale factor character positions, which enables the overflow check.

The Boolean expression for loading the RSCUM register 730-78 and the RSCLM register 730-144 is:

LDRSCM = (FLDCOMPL (FCRD + DUCMD 314 + DUCMD 205) (DUCMD 305 + FCZO))

The Boolean expression for decrementing the bit position is RSCUM 0-6 and RSCLM 0-6 CNTDWNRSCM = (DUCMD 305 + FCZO)

ß ± n Command DUCMD 303 (operand storage by the decimal unit) is initiated by the firmware. Since this is a short operand operation, two words are sent out from the execution unit 714 to the decimal unit 730 via the bus line RCHU 4-35. The least significant word remains stored in the RPK register 730-162 and the most significant word remains on the RCHU 4-35 bus line for instruction processing.

The RRWC register 730 ^ 88 stores the internal position of the Data word of the highest significance, which is to be transmitted from the decimal ^ unit 730 to the cache memory unit 750 is. The content of the register is reduced whenever a word consisting of 4-bit characters is sent out to the cache memory 750. The register is also reduced in terms of its content in each case when a word of 9-bit characters is sent out to an odd address memory location in the cache memory 750 will. The Boolean expression for the decrement signal CNTDWN-RRWC has already been described above been.

030028 / 087Θ - BATHROOM

The RDSC register 730-58 stores the shift counter position sent to the ZDS shifter 730-156 is issued via the ZDSC switch 730-72.

Assuming the shift count is positive, meaning that the RDSCO bit is a zero, and that the RRWC register indicates a word count greater than one, the ZPKL switch 730-166 and the ZPKR switch 730-164 to the slide device 730-156. The output signals ZDSO-31 are zero; they are handed over to the ZID counter 730-150. The output signals ZID 0-35 are sent to the ZSMR switch 730-180, in which the rewriting characters and the leading sign can be added to the word with the highest value. The output signal ZSMR 0-35 is sent to the ZDOD switch, in which 9-bit character words, EBCDIC or ASC11 zone characters are added, the output signals ZDOD 0-35 in the RDOD register 730-154 for a ^r -: Transfer to cache memory 750 is loaded. The control signal SRDODA loads the RDOD register 730-154 as logic signal 1. The Boolean expression is;

[5RDODA - ((FDATA-AV + DUCMD 203 + DUCMD 310 + DUCMD 309 + FRPK · DUCMD 30 3 +

FALL. FSWRT) DUCMD 311)

If the count in RRWC register 730-88 is 1, then the word becomes highest Significance, which is stored in the RCHO register 720-10 and which is on the signal bus line RCHU 4-35 occurs via the buffer 730-168, the position 0 of the ZPK switch 730-160, the position 0 of the ZPKR switch 730-164, the ZDS shift device 730-156, in which the relevant word is shifted to the right, delivered, vrobei the number of digit positions equal to the binary

030028/0876

BATH ORIGINAL

ZDSC shift count is 1-3. Here are zeros equals the number of shift count inserted _r on the left side of the ZiffernpQsition most significant. The ZDS 0-31 output signals are switched through when the ZID switch 730-150 is set to 0. The output signals ZID 4-35 are sent to the ZSMR switch for 4-bit characters, whereby the word is expanded from 32 bit positions to 36 bit positions. The output signals ZSMR 0-35 are switched through via position 3 of the ZDOD switch 730-152 to the RDOD register 730-154, from which the word is transferred to the cache memory.

If the word has 9-bit characters _r then the output signals ZID 0-35 are output to position 2 of the ZDOD switch 730-152, provided the word is written into an even address of the cache memory 750 _r or the relevant output signals are on the position of the ZDOD switch 730-152 is released when the word is written into an odd address of the cache memory 750 via the RDOD register 730-154. Assume that a. Word for an even address is present in the cache memory 750. Then the signal ZID 4-35 is switched through via position 2 of the ZDOD switch 730-152, the four characters displayed by ZID 4-19 being expanded to 36 bits by adding the 3BCDIC or ASCII zone characters. On the next cycle, the signals ZID 4-25 are switched through via position 1 of the ZDOD switch, the signals ZID 20-35 being expanded to 36 bits by adding the EBCDIC or ASCII zone characters.

The RRWC register 730-88 is reduced in terms of its content each time a 4-bit character word is added is transferred to the cache memory 750, or each

030028/0878

Ii

when a 9-bit character word is transferred to an odd address in the cache memory 750. the The count of the RRWC counter 730-88 is set to zero decreased, the shift count signal ZDSC1-3 a is positive binary number. In this case, the output signals ZPK 4-31 are issued via the ZPKL switch 730-166, and the output signals RPK 0-3 are via the ZPKR switch 730-164 released. In addition, the second word is processed as before.

The content of the RRWC register 730-88 is reduced to the binary value -1, the shift count signal ZDSC 1-3 being a positive number. The RPK register 730-162, which stores the word with the lowest significance, sends its output signals RPK 0-31 to the ZDS shift device 730-156 via the ZPKL switch 730-156 _o This means that zeros are sent to the ZDS shift device 730- 156 delivered via the ZPKR counter. The output signals ZDS 0-31 are output via the switches for loading the RDOD register 730-134 for the purpose of transmission to the cache memory 750.

If necessary, the value of the RRWC register 730-88 is reduced to the binary value -2. Included zeros are sent to the inputs of the ZDS shifter 730-156. The operating cycle gives the Exponents of the following sign and also the Exchange character for storage in the RDOD register 730-154 free after switching through the ZZJWR switch 730-180 and the ZDOD switch 730-152 is.

Each of the above memory operations is enabled by a signal DUCMD 303, which is triggered by a firmware command is set whereby the word is loaded into RDOD register 730-154 in the first firmware cycle and whereby

030028/0876

ff

the word in the cache memory 750 is written in the second firmware cycle. The first firmware cycle and the second firmware cycle are repeated until all words containing the operand 3 information have been transferred to the cache memory 750.

The sequence of steps to load cache memory 750 to achieve a negative shift count, that is, that the output signal RDSCO is equal to 1 is same as the sequence of steps for a positive shift count, with the exception that the binary value in the RRWC register 730-88 for the respective step by 1 is higher than the corresponding value for the positive shift count.

As part of the long operand store operation, the firmware initiates a DUCMD-304 operation (check for zero / overflow). The operand 3 information is sent from the execution unit 714 to the decimal unit 730 under firmware control, one word being sent out in each case, starting with the word with the lowest significance. A DUCMD 304 instruction is issued for each meaningful word to be checked, the respective word being entered into the RCHO register 720-10 according to FIG. 2 at the respective point in time. The last command DUCMD 304 is issued by the firmware for the word of the highest order of the long operand. The decimal unit 730 samples each word included in the cycle following instruction DUCMD 304, which is marked by the FCZO flag being set. The scanning takes place from the word of the lowest value to the word of the highest value, with the number of digits on the right-hand side including the digit of the highest value being counted. This number is stored in RWPC register 730-84, RLZCI register 730-96 and RLZC2 register 730-98.

030028/0876

BATH

The output signal of this register stands for the firmware to the issuance of the command DUCIO 311 (Enter operand word count in RDOD).

By the effective digit logic 730-81 according to FIG. 7 the resulting operand word RCHU 4-35, which is received by the character unit 730, is checked. That resulting operand word was in the execution unit 714 have been generated; it represents the result of the decimal-numeric operation on the operand and has been executed on operand 2.

The negated signals RCHU 4-35 are sent to the inputs given by NAND gates 81-2 to 81-16. The decimal digit zero signals RCHU 4-7 are fed to the input side of the NAND gate 81-2. The decimal digit 1 signals RCHU 8-11 are fed to the singing side of the NAND gate 81-4. The Decimal digit 2-7 signals are applied to the inputs of NAND gates 81-6 to 81-16.

If the input signals for the NAND gate 81-2 indicate that the signals RCHU 4-7 in the digit position 0 indicate a digit that is not zero, then the output ssignal DGZ-O of the NAND gate 81-2 is used as a logic signal 1 fed to the input of a NAND gate 81-42. The output signal EDC-O indicates as logic signal 1 that the word contains eight significant digits. The output signal DGZO is output as logic signal 0 to the inputs of the NAND gates 81-44, 81-46 and 81-48, whereby the output signals EDC1-3 are output as logic signals.

If the signal RCHU 4-7 shows a decimal 0 in the digit 0, then the output signal of the NAND gate 81-42 is blocked, and the output signal of the NAND-

030028/0876

Links 81-44, 81-46 and 81-48 are released; this output signal shows the position of the highest digit Significance of the operand word. It is assumed that the digit with the highest value is in the 5 of the eight-digit operand word with the digits 0 to 7. Therefore, the output signal occurs DGZ5 of the NAND element 81-12 as a logic signal O, and the output signals DGZ 0-4 of the NAND elements 81-2, 81-4, 81-6, 81-8 and 81-10 are output as logic 1 signals.

The signal of the number 5 is output as logic signal O to the input of the NAND elements 81-22 and 81 = 32. The output signals DZR56 and DZR5 / 7 are sent as logic signals 1 to the inputs of the NAND elements 81-28 and 81-40 output »The other] Singangssignals _s namely the signals DZR34 and DGZ4 are output as logic signals to the other inputs of the NAND elements 81 = 28 or _B 81-40. The output signal DZR3 / 6 is output as logic = signal 1 to the input of a NAND- member 81 = 36 output the other input DZR12 performs as logic signal 1 to _s that the output signal DZR1-4 of the NAND gate 8-34 acts as a logic signal O, whereby the output signal EDC-1 of the NAND gate 81 = 44 as the link signal O occurring ο The output signal DZRI Jb of the NAND element 81-36 occurs as a link signal 0 _p because the input signal DZR34 of the NAND element 81 = 28 occurs as a link signal 1 »This means that the output signal DZR1 / 6 is used as a link signal gnal 1 emitted ^ whereby the output signal EDC-2 of the NAND gate 81 = 46 is emitted as logic signal 1 _e

The output signal DZR477 of the NAND element 81-40 is fed as a logic signal O to the input of the NAND element 81-24. The output signal DZR3 / 7 is fed as a logic signal 1 to the inputs of a NAND element 81 = 30 _o

030028/0876

The other input signal DGZ-2 causes, as logic signal 1, the output signal DZR2 / 7 as logic signal O ₅ , whereby the output signal DZR1 / 7 of a NAND element 81-38 is given as logic signal 1 = thus the output signal EDC-3 of the NAND - Link 81-48 issued as link signal 1 »

The signal EDC = I as logic signal O and the signals EDC-2 and EDC-3 as logic signals 1 indicate that there are three significant digits in the operand word ο

The word with the lowest value is received by the decimal unit 730 via the signal bus line RCHU 4-35 in the buffer 730 = 168. The negated output signals RCHU 4-35 are output to the effective digit logic 730-81. The effective digit logic 730-81 gives the output signals SDC 0-3 to the input of the ZEDC switch 730-82. The output signals ZEDC 1 = 3 featuring a binary counter position or number of significant digits in the word _5, and starting with the digits most significant and counting up to the digit position 7 least significant ₉ which is towards included in the count with. The output signal ZEDCO indicates, as logic signal 1, that the highest value digit of the word "this is the digit 0, has a decimal digit different from O." This output signal is loaded into the AEDC adder 730 = 96 ^ after the first word has been recorded RWPC register 730 = 84 is incremented by 1 each time a subsequent word _{is received by the execution unit 714 o} This is done by the control signals ENRWPC ₅ CNTUP = RWPC and LDRWC _{9 sent} to the input connections of the RWPC register 730-84

The Boolean expressions for the control signals LDRWPC which load the RWPC register 730-84 and for the signals ENRWPC ₃ which enable the output of the register are

^follow! ■ §30028 / 0876

[ENRWPC »((DUÖMD 30 5 + FCZO) + FCRD * DUCMD 314

• DUCMD 205)

[LDRWPC - ((DUCMD 305 + FCZO) (FCRD + DUCMD 314. · + DUCMD 205))

The output signals RWPC 0-3 are fed to one connection of an ASDC adder 730-86. The ZEDCO signal will another connection of the AEDC adder 0-3 is fed to its output signal via the ZEDD switch 730-94 switched through and in positions 0-3 of the RLZC1 register 730-96 and the RLZC2 register 730-98 is saved if the respective recorded word is one of zero has different stored decimal digits. The binary output signals ZEDC 1-3 of the ZEDC switch 730-82, which indicate the number of significant digits in the word, are in positions 4-b of the RLZCI re-cister 730-96 and the RLZC2 register 730-98. The register output signals RLZC1 0-6 and RLZC2 0-6 are fed to the ZLZC switch 730-76, its output signal for the firmware via position 3 of the ZID switch 730-150 made available! The registers RLZC1 and RLZC2 both store the number of significant digits in operand 3. When the first word is received by execution unit 714 and accepted position 0 has a decimal digit other than 0, then the binary fourth becomes 8 in the registers RLZC1 and RLZC2 saved. The input signal ZEDCO to the ZEDC adder 730-84 is a Veikjaüpfungssignal If the second word is included and presumably contains a decimal digit again in position 0, then the ZEDCO input signal for the ZEDC adder occurs as 1 signal on, and the RWPC3 input signal is a binary signal 1 ο This means that the output signal ZEDCO-3 is used as a binary 2 is output, and the binary quantity 16 is stored in registers RLZC1 and RLZC2. Suppose that the third word only contains three decimal digits, with the highest significant digit in position 5 is included. In this case, the initial

030028 / 087S

signal ZEDCO-3 a binary value 011 in the RLZC1 resp. RLZC2 registers 730-96 and 730 = 98, which is now in size 19 is saved in the registers "

The bits RLZC1-2 and RLZC2-2 (binary 16-bit) are set again because the output signal AEDC 0 = 3 is a binary 2 is "The RWPC register 730 = 84 is from the binary 1 has been incremented into binary 2 »The RRWC register 730-88 saves the set length of the operand, which has been calculated from the length and the scale factor = values as specified by the descriptor o The RWPC register 730 = 84 stores the number of words that are checked by the firmware, as a result of the DUCMD 304 instruction on a long operand.

With the long operand memory operation it is necessary to the operand 3 ■ = which is the result of the operand 1 "and the calculations concerning operand 2 and which exists internally in execution unit 714 to compare with operand 3 as it is in the cache 750 is to be saved and this process is to be carried out with a simplified firmware procedure »

First, the firmware issues the DUCMD 303 command, which concerns the storage of an operand by the DU unit ο This command triggers the actual storage sequence in the decimal unit 730 no write address before and does not send a write command to the cache memory 75O ₁ until this is pulled by the decimal unit 730. The decimal unit 730 makes this decision on the basis of the information contained in the RRWC register 730 = 88 in the RWPC -Register 730 = 84 and is stored in the position of the most significant digit within the word if the operand is replaced by the

030028/0878

Decimal unit 730 received by execution unit 714 as indicated by the output of the ACPWB adder 730-50. As in the case of the short operand becomes the output of the ACPR adder 730-62 from the output of the ACPNB adder 730-50 in the ACPSC adder 730-54 to produce the shift number which is in the RDSC register 730-58 is saved.

each

It should be noted that / are stored in cache memory 750 Word requires a minimum of two firmware cycles for the memory operation. The address in the cache 750, under which the operand word is written, is sent to the cache memory 750 in the first cycle sent out ^ and the data for cache memory 750 is sent out in the second cycle. The firmware is therefore organized in two step loops in the first In the second step, the address and the write command are generated, and in the next step, the data is sent from the Decimal unit 730 to cache memory unit 750 The process begins in the cycle in which the firmware the command or «, the DUCMD 303 command sends to the decimal unit 730» The firmware checks the start write signal RRLTRD for the execution addressing and routing circuits 701-1 of FIG the presence of a link signal 1 «This link signal indicates that a write command should be generated and issued to the cache storage unit 750,

The FSWRT flag is set to indicate to the decimal unit 730 that the firmware is sending write commands to the cache memory 750. If the start write line RRLTRD carries a logic signal 0, then the firmware controls the loading of the RCHO register 720 = 10 of the character unit 720 with words from the execution unit 714 until the most significant word is stored. This is ₀

Q30028 / 0878

the case when the counter position in the RWPC register 730-84 is greater than the counter position in the RRWC register 730-88. The content of the RWPC register 730-84 is reduced whenever a word is accommodated in the RCHO register 720-10, until the counter position in the RWPC register is equal to the counter position in the RRWC register ₉ if the RDSC Register 730-58 indicates a positive shift, or until the counter position in the RWPC register is less than the counter position in the RRWC register, provided the RDSC register indicated a negative shift RCHO Registers 720-10 Stored On a negative shift, the most significant word is stored in RPK register 730-162 and the second word is stored in RCHO register 720-10

In the operation relating to the positive shift, the start write line RRLTRD will carry a logic signal 1, and the firmware triggers writing into a loop of the cache memory 750 if the counter position of the RRWC register 730-88 is equal to the counter position of the RWPC register 730 -8b is »This sets the FSND number by which the word previously stored in RCHO register 120-10 is keyed into RPK register 730-162. In addition, the firmware is indicated _s that the next word is to be loaded into the RCHO register 720-10 from the execution unit 714, in that the send data signal RRSQKD is output as logic signal 1 ₀

The Boolean expressions for the start write signal RRLTRD and for the send data signal RREQRD with regard to memory operations relating to long operands are the following %

Q30028 / 0878

DSEND DATA DSTRTWRT RREQRD

RRLTRD

DMSDRGTE

DMSEQ
DMSDRGT

The ßoolean RWPC registers

[CNTDWN-RQPC

(FCPCO

• FSWRT · FMSDRN

FMSEQ · DMSDRGTE

ZTNSAO + ZTNSAO)

DMSEQ

- FDUACT

RDSCO + DMSDRGTE RDSCO + DUCMD 30 3 · RRWCO DSEND DATA

DUCMD 202

• DUCMD 204 · DUCMD 306 FDUACT · DSTRT-WRT · DUCMD 202

• DUCMD 2QA

(RWPC 0-3 * MINUS * 1) 3 (RRWCO * (RRWCl + RRWC2) * RRWC3

• RRWC4 · RRWC5 · RRWC6 (RWPC 0-3 · MINUS · 1)

(RRWCO * (RRWCl + RRWC2) * RRWC3

• RRWC4 · RRWC5 · RRWC6

(RWPC 0-3 · MINUS · 1)> (RRWCO · (RRWCl + RRWC2) · RRWC3

• RRWC4 · RRWC5 · RRWC6)

Expressions for counting down in the 730-84 are;

FRPK DUCMD 303 (ZTNSAO FCPCO

+ ZTNSAO) + FWK · (FOPSVR + "

DUCMD 303 DMSDRGTE) FAXT (FSWRT

[$ RDOD

• DMSDRGT + (ZTNSAO · FCPCO + ZTNSAO)

• FSWRT · DMSDRGT))

FDATA-AV + DUCMD 203 + DUCMD 310 + DUCMD 311 + DUCMD 309 + FRPK · DUCMD 303 + FRFk · FALT · FSWRT

The decimal unit 730 compares the output signals RRWC 0-6 with the output signals RWC 0-3 in a comparator 730-90. The comparator output signals DMSEQ, DMSDRGT and DMSDRGTE cause the register and the Switch control 730-91, the signals RRLTRD and RREQRD as well as to generate the various signals which the ZPK switch 730-160, the RPK register 730-162, the ZPKL switch 730-166 and the ZPKR switch 730-164

030028/0876

steer. The signals also cause the status flag control logic 730 = 202, the flags FSNDs, FSWRT, FMSDRGTE and FMSEQ. and to reduce the content of the RRWC register 730 = 88 and the RWPC register 730-84. If the number of words stored in RRWC register 730-88 is greater than the number of words stored in RWPC register 730 = 84, then the cache write flag FSWRT is set but the FSND = flag <, this results causes the RDOD register 73 = 154 to output words containing all zeros to the cache memory 750 and to decrement the contents of the RRWC register 730. If the comparator 730-90 indicates an equality condition, then the FSND flag is set ₉ and under firmware control, the word of the highest significance is sent out from the execution unit 714 to the decimal unit 730 via the signal bus line RCHU 4-35 to position 0 of the ZPK switch 730-160 ^, the word of the highest significance is stored in the RPK register 730-162 by the ZPK switch 730-164. A control logic (not shown) gives d en ZPKR switch free when a data word can be put together and sent to the cache memory 750 ₀ In this case, the output signals ZPKR 0 = 31 are sent to the ZDS shifter 730 = 156, and the word is shifted by a number of digits , which is equal to the binary value of the signals ZDSC 1 = 3 "Zeros are output to the signal bus line ZPKL 4 = 31. The output signal ZDS 0 = 31 is changed via position 0 of ZID switch 730 = 150 to position 0 of ZSMR = switch 730." = 180 switched through if the operand contains 4 = bit characters _o If the operand has 9 ~ bit = characters ₉ then the output signal ZDS 0 = 31 is set via position 0 of the ZID switch 730 = 150 to position 1 of the ZDOD- Switch 730 = 152 switched through, provided the word is in a

030028/0876

odd address is to be written in the cache memory 750, or to position 2 of the ZDOD switch, if the word is to be written into cache 750 at an even address.

The position O of the ZSMR switch leads to an expansion of the word containing 4-bit digits from 32 bits to 36 bits, whereupon the word has the position 3 of the ZDOD switch 730-152 is switched through to the RDOD register 730-154, in which the relevant word and in the next cycle to the cache memory 750 is sent out.

When the ZDOD switch 730-152 is in position 2, words expanded by operands to consist of 9-blt digits, by expanding the output signals ZID 4-19 in such a way that the 3b-bit word is generated. This is done by that the ACSII or EBCDIC zone characters are added. In position 1 of the ZDOD switch 730-152, the Output signals ZID 20-35 to 36 bits on the signal bus line ZDOD 0-35 extended. The output signals ZDOD 0-35 from position 2 of the ZDOD switch are in the RDOD register 730-154 and transferred to an even address of cache memory 750. The output signals in When the ZDOD switch is set to 1, the addresses of the cache memory 750 are sent to odd addresses.

In the event that the output of the comparator 730-90 indicates that the binary number or counter position RRWC 0-6 of the RRWC register 730-88 is smaller than the binary counter position RWPC 0-3 of the RWPC register 730-84 the data words are neither received by the execution unit 714 nor from the decimal unit to the cache memory 750 sent out, and the count of the RWPC register 730-88 is counted down or decreased until the output of the comparator 730-90 indicates that the

030028 / 087S

binary counter position RWPC 0-3 is equal to the binary counter position RRWC 0-6. This will make the license plates FMSEQ and FSWRT are set and the data words are clocked into RDOD register 730-154 and transferred to the cache memory 750.

Operands with 9-bit characters cause the transfer from two words to cache 750 to each of the words from execution unit 714 during normal Operation recorded words. The location recorded by the execution unit 714 has up to eight Decimal digits with four bits each; it gets on expanded two words, each of which has up to four decimal digits of nine bits each. The cyclical Setting and removing the FCPCO flag controls the transmission of words to odd addresses and even addresses in the cache memory 750 «

Cycle delay

The rate of processing of short operand is increased thereby, that at the beginning of the processing of the command or the instruction, the number of words is predetermined, which is emitted from the decimal unit 730 to the execution unit 714 ₅ and that the number of cycles is predetermined between the time at which the first read command is sent to the cache memory unit 750 and the time at which the first data word is sent to the execution unit 714. The number of words and the number of delay cycles are calculated in the decimal unit 730 and determined by the firmware in the execution control unit 701. The output signals PK-VCTR 0-3 of the decimal unit 730 according to FIG Branch circuits 701-1 issued; they cause

030028/0878

let the firmware branch to a specific address in execution control memory 701-4, which causes the firmware to execute a subroutine to process the operand. The particular selected Subroutine is designed to match the exact number of words in the operand with the exact number of delay cycles, whereby the operand is processed with the minimum number of microwords will.

The calculation of the number of delay cycles is a function of the data type, which means that the calculation in question depends on whether the incoming operand consists of 4-bit characters or 9-bit characters. In addition, the calculation in question depends on the location of the most significant character in the operand that comes from the cache memory 750, and also on the location of the most significant digit in the operand that is transferred to the execution unit 714. As an example, assume an 8-decimal digit operand consisting of 9-bit characters with a leading sign. It is also assumed that the sign is or was contained in the third character position of the first word of the operand. The second word from cache memory contains 4 decimal characters and the third word from cache 750 contains 4 decimal characters. The decimal unit 730 would invite no decimal digits to the inclusion of the first word out since the first W _O rt contains only the sign. Four decimal digits are taken from the second word, but this is not enough to fill the RDOD register 730-154. Four decimal digits are included from the third word and the RDOD register was loaded with 8 decimal digits.

These load operations take three cycles to complete

030028/0876

assemble the location and transfer it to execution unit 714. The signal lines PK-VCTR 0-3 would the firmware does a word transfer with a 2 cycle = Show delay. The firmware performs using the information indicating the number of transmitted Words and the number of delay cycles indicates the control regarding the transfer of Words of data from one register to another register in a special cycle, rather than stopping or in to pass a waiting loop for a data word,

The delays are a function of the data type, the 4-bit or 9-bit decimal symbols, as indicated by the state of the output of the ZTNSA switch 730-36 and. of the ZTNSB switch 730-34 is displayed ₀ These signals are the signals ZTNSAO or ZTNSBO ₅ . The ACPDF adder 730-52 provides the difference in setting between the first digit position for the high-order digit in the first word from the cache memory 750 and the digit position of the highest-order digit as it is transmitted to the execution unit 714. The output signal ZCPAO of the ZCPA switch 730-44 designates the word from the cache memory 750 which occurs under an odd or under an even word address.

The Boolean equations for number calculations of words and delay cycles can easily be converted into functional hardware; they are by following Equations given;

PK VCTR 9-0
PK-VCTR 1 = ■> TDBjJ
PK-VCTR 2 * = TDBl
PK-VCTR 3 = ARWC6

030028/0876

TDB0 * [(ZTNSA (J · FDUACT · FEÜPl + ZTNSB0 ■ FRDPl) (ACPDF0 · Z "CTA" 0 + ACPDF0 · ZCPAj? · ACPDFl)]

TDBl * KZTNSA0 FDUACT FRDPl + ZTNSB0 * FRDPl) (ACPDF0)

FDUACT FRDPl + ZTNSB0 FRDPl)

[(ACPDFZ · 'ΖΤηζ0) + (ACP.DF0 · (ÄCPTTb "0 * ACPNBl 'ACPNB2 * ACPNB3 +

- acpnbi) + acpdf0 · zcpa0 · acpdfi)]

The PK-VCTR1 signal is output as a binary signal 1 and indicates a 2-cycle delay. The signal PK-VCTR2 indicates a 1-cycle delay as binary signal 1. The signal PK-VCTR3 indicates a binary O, that a data word of the decimal unit to the execution unit 714 through wircU transmitted the signal are PK-VCTR3 shows a binary 1 to _s that two data words to the execution unit 714 transmitted.

For the calculation of the signal PK-VCTR1 the Boolean shows Expression ZTNSA0 · FDUACT · FRDP1 indicates that a 9-bit operand 1 word from the cache memory 750 is present «, the signal ZTNSB0.FRDP1 shows the presence of a 9-bit operand ~ 2-word from the cache memory 750. The expression AGFDF0 ACPA0 indicates that the shifter 730-156 left shift the word from an even Address of the cache memory 750 has been made or will «, The expression ACPDF0 · ZCPA0 · ZCPDFf shows a left shift of 1-3 decimal digits of a word from an odd Address of the cache memory 750.

For the calculation of the signal PK-VCTR2, the expression ZTNSAO · FDUACT.FRDP1 «ACPDF0 shows the presence of a 4-bit Qperand-1 word from the cache memory 750 Bn ₉ \ f which requires a left shift by the shifter 730-156. The expression ZTNSBO-FRDP 1 <> ACPDF0 indicates a 4-bit 0perand-2 word, which is a left

0300 2 8/0878

Shift required The expression ZTNSA0οFDUACT ° FRDP1 + ZTNSB0 «FRDP1 shows a 9 = bit operand = 1 word and a 9 bit 0 operand 2 word at ₀

The expression ACPDFZ ° ZÜFÄ0 + ZCPDF0 ° ZCPA0 indicates either a zero shift / a right shift of the word from the even cache memory address _o The expression ACPNB0 · ACPNB1 ° ACPNB2 ° 5ÜPHB3 indicates that the decimal number is in the 4 of the 4th digit -Bit character word or in position O of the 9-bit character word from an odd cache memory address. 3 is included and that the shift number is less than four digits _o The expression ACPDF0 ■ »ZCPA0 ° ACPDF1 shows a left shift ₉ that is greater than three digit positions from the odd cache memory address word _o It should be noted that the signal ACPDFZ as binary = signal 1 indicates that the adder 730-52 is set to a binary value O. To calculate the signal PK = VCTR3, the signal ARWC6 shows a 1-word transmission from de r decimal unit 730 and execution unit 714 when the signal in question occurs as binary signal 0 j while a 2-word transmission is displayed when the signal in question occurs as binary signal 1 ο

Decimal unit 730 - Fig _o 3 - * rewrite operation

The operand 3, in character positions within the word most significant and the word least significant start and end _o It may be necessary to hold three information stored the highest in the words and lowest value of the operand that is not part of the operand 3 ,, In in this case solves the

03OO28 / Q87S

Firmware issues a command DUCMD 306, which concerns the loading of rewrite data. This command is triggered in the decimal unit 730 in order to transfer the word of highest significance to the REWR2 register of the register bank 730-177 via the bus line ZDI 0-35 from the cache memory 75O _{9 to} the RDID register 730-158 and the RDID buffer 730- 176 to download. The firmware triggers a second DUCMD command to load the lowest significant word into the REWR3 register of the REWR O-3 register bank 730-177. If the firmware DUCMD a command outputs 303 (storing the operands on the decimal), the word occurs on most significant on the ^s ignalbusleitung ZID 0-35. Assume that there are 4-bit decimal points for the operand. In this case, the RCP2 register of register bank 730-42 stores the start character position of operand 3. Since this is a descriptor 3 operation, the position RCP2 of switch 730-44 is selected and the output signal ZCPA 0 -3 is sent to a ZRUMP switch 730-148. Position 1 of the ZRUMP switch is activated, and the output signal ZRUMP 0-2 is sent to a REWUM slide device 730 149. The REWUM 0-7 output signals are provided to the Control 1-ZSMR logic 730-142, and the Control-2-ZSJVIR-C-7 output signals select the digit position of the ZSMR switch that is selected. For example, for processing the most significant word of the 4-bit digit operand, the digit positions in position 0 of the ZSMR switch 730-180 would be selected for the operand digit data. The sign position in position 1 of ZSMR switch 730-180 would be selected if the operand had a leading sign and the digit positions to the left of the operand would be selected in position 3 of the ZSMR switch for rewrite data will. The output signal REWUM is 0-7 of the shifter 730-149

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ο -

request the write data for those digits O ₉ ,, The output bus ZSMR 0 = 35 is on the position O of the ZDOD switch 730-154 to the RDUD registers 730-154 hinjdurchge switched ₀

If the operand contains 9 = bits = decimal digits ₉ then the logic signals 1ZSMR O ₉ 2 _P 4 and 6 and the logic signals 2ZSM O _D 2 ₉ 4 and 6 are sent to the unpacking or spreading ZBOD = logic 730 = 184 The output signals 1ZD0D 0 = 3 and 2ZD0D 0 = 3 give the positions for rewriting or ₀ rewriting and for the leading sign digit of switch position 3 and the operand decimal digit positions of either position 1 or position 2 of the ZDOD switch 730-152 free.

During the load operation with regard to a 2-descriptor operation, the most significant word of the operand, which could contain rewrite information, is written into the REWRO register of register bank 730 = 177 and all subsequent words are entered into REWR1 register 0 hrieben _s whereby the previous word replaced wirdo this results in _D that the word most significant of the operand 2 in the REWRO register is stored and that the word of lowest value is the operand 2 is stored in the REWR1 register ₀ the loading of these registers in the RDQD ~ Register 730 = 154 takes place in the manner described above ₀

The REWR «= Reglsterbank 730 = 177 is determined by the control signal SRBWR released The Boolean expression is SREVJR = CFDID + FLDREWRH) o

The control signal WRREWR1 is output to terminal 1, and the status flag FLDREWRH is applied to terminal 2 of the register selection input terminals to one

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of the four registers REWR 0-3. The Boolean expression for the control signal WRREWR1 is: WRREWR1 = FR0P2LD F0P2F + FLDREWRH FREWR

The output signal of the register REWR 0-3 is transmitted via the ZEWR switch 730-178 selected. The signal 1ZEWR becomes to output selection terminal 1, and the status flag FREWR is applied to the output selection terminal 2 of the ZEWR switch 730-178. The Boolean expression for the control signal 1ZEWR is:

1ZEWR = (.FREWR FREWR2. FFOSD + F0P2S. FFOSD

FREWR ;.

Decimal unit 730 - Fig. 3 - rounding constant

Two commands or commands DUCMD 309, which bring about the introduction of the rounding constant in the device RDOD, are initiated by the firmware. For short operands, the rounding constant is sent to the execution unit in response to the first command DUCiO 309 if the relevant constant is to be inserted into the word with the lowest significance. The rounding constant is sent out to the execution unit upon the occurrence of the second command or second command DUCMD 309 in the event that the relevant constant is to be inserted into the word of highest significance. In any case, a word that contains a total of zeros is sent out to the execution unit in response to the further instruction DUCMD 309. The further or other rounding constant, a binary 5, is added to the digit to the right of the scale factor pointer { decimal point). The rounding constant is stored in bit positions 4-7 of switch position 3 of ZPK switch 730-160.

The ATMP adder 730-30 subtracts a 1 from the operand 3 scale factor stored in the RSF2 register of the

030028/0876

Register bank 730-4 is stored, with a signal output to the ATMP adder 730-20 via the ZASFB switch 730-28 takes place. If the output ATMP6 is a zero then the rounding constant is applied to the word lowest value issued in response to the DUCMD 309 command. If the output signal ATMP6 is a 1, then the rounding constant is transferred to the word with the highest value in response to the second DUCMD 309 command.

The output signals ATMP 7-9 are inverted by means of the inverter 730-147. The output signals ATMP 7-9 are selected by ZDSC switch 732; they represent the binary shift number for the shifting device 730 = 156 «,

The ZPKR switch 730-164 is on the first command DUCMD 309 released, provided the rounding symbol η is added to the word lowest value »The relevant switch is responded to the second command DUCMD released, provided the rounding character is added to the word of highest value »In any case, will a binary output signal 5 from position 3 of the ZPK = switch 730-160 to the execution unit 714 the ZPKR switch 730-164, the ZDS sliding device 730-156, the position 0 of the ZID = switch 730-150, the Position 0 of the ZDOD switch 730-152 and the RDOD = Re = register 730-154 transferred

For the long operand store operation, the decimal unit 730 speaks to the first Command DUCMD 309 with a pointer that points to the word in the notepad memory to which the Rounding constant is added. Furthermore, the relevant decimal unit speaks to the second command DUCMD 309 with the rounding constant at »The output signals ATMP 0 = 6, which indicate the word ^ to which the rounding constant is added, are about the position

030028/0876

3Q0OQO6

of the ZLZC switch 730-76, position 3 of the ZID switch 730-156, the position 0 of the ZDOD switch 730, the RDOD register 730-154 for the execution unit 714 ' selected. The rounding constant, a binary 5>, becomes the execution unit 714 during the second DUCMD-309 operation as explained above for the short operand.

Sign derivative

Since each operand is accepted by the decimal unit 730 during the load operation, the sign becomes checked, provided it is not an overlaid sign. The decimal unit 730 checks whether the character in question is a valid algebraic sign.

An RCPS O-2 register 730-126 stores the memory location within the word of the sign. A ZCPS switch 730-124 selects the position of the sign the end. The ZCPS switch position 0 sets the leading sign position fixed for 9-bit character operands. Switch position 1 sets the leading sign position for 4-bit character operands. Switch position 2 designates the final sign position for 9-bit character Uperands. Switch position 3 designates the final sign position for 4-bit operands.

The output signals RCPS 0-1 select the position of a ZCH switch 730-170 showing the sign could contain. No attempt is made to use the terminating or leading word of the operand in the ZCH switch 730-170. One from the cache 750 operand word received via the signal bus line ZDI 0-35 is stored in the RDID register 730-158 and delivered to the ZCH counter 730-170. The output signal ZCH 2-8 is connected to a ZCHL switch 730-172 and to the

030028/0876

Sign derivation logic 730-174 released »Position 1 of the ZCHL switch is used for 9-bit operands and selected for 4-bit operands with an odd character pointer.

The sign-lead logic 730-174 selects either the sign character from the final or ₀ following word or from the leading word. If the sign is coded as an invalid character, a link signal (SET ILLEGAL) causes the software to issue an error message. If the sign is coded as the correct sign, the link signal (SET SIGN) sets an indicator for the software. The output signals ZCH 1-8 for the sign · = sign derivation logic show ei-bit EBCDIC signs. The ZCH 1-8 output signals for the ZCHL switch indicate 4-bit signed characters in the lower half of the 9-bit character (bit position 4-8) for 9-bit character operands. With 4-bit operand words, even pointers indicate the left four bits (bit positions 1-4), while odd pointers indicate the right four bits (bit positions 5-8).

Control signals 1ZCPS and 2ZCPS are applied to select input terminals 1 and 2 of ZCPS switch 730-124. The Boolean expressions are ι

FRDPl)

[IZCPS = »(ZTNSAO • FDUACT • FRDPl + ZTNSBO [2 ZCPS " CSTNSAl · ZTNSA2 FDUACT • FRDPl ZTNSBl - ZTNSB2 FRDPl)

The RCPS register is controlled by an SRCPS control signal

released whose Boolean expression is given by: [$ RCPS - (FDUACT · FP.DPl) + SFOP2LD)

030028/0876

Over-hole digit correction - Fig. 3

Operands that have words with 9-bit characters can have separate signs, either in a leading character position or in a subsequent character position, or the operand can be a Have a sign which is contained in the decimal digit code in a single character position. this requires a correction to be made to the decimal digit to include the over-holed sign. It is assumed that operand 1 requires an over-holed sign correction. A link signal ROP1 is sent from the control store 704-2 to the decoding logic 730-38. When the output signal ZTNSA 0-2 is coded from the RTNS2 register of register bank 730-32 and the ZTNSA switch 730-36 so that it is a Binary signal represents 000 or 011, making 9-bit characters are denoted by a leading sign or a following sign, then a logic output signal D1EQOVP of decoding logic 730-38 is output high. The link signal D1EQ0VP selects position 1 of a ZSSC switch 730-108 for an operand with the following sign. the Position 0 of the ZSSC switch is selected for the leading sign. The signals RLMP 4-6 are like this encoded to point to the character position of the leading sign, and the RTMP 4-6 signals are like that coded that they point to the character position of the subsequent or attached sign.

The shift count signals ZSSC 0-2 are sent to a shift device 730-145 issued to shift a logic signal DBITT, the number of bits by the counting signal ZSSC 0-2 is fixed. The link signal DBITT is used as a pre-link signal 0 for the overlaid Sign operations issued during the cycle in which the most significant word or the

030028/0876

! // Location of lowest significance from cache memory 750 is read out for a leading sign correction or for a subsequent sign correction. the Output signals ZCRDGM. 0-7 of the sliding device 730-145 are sent to the ZID switch control logic 730-188, to position 2 of the ZID switch for the character position to select, which is indicated by one of the signals ZCRDGM 0-9, which as a zero signal occurs and points to the over-punched sign position.

The RSGN register 730-134 has the corrected overlaid sign for operand 1 under of the firmware control loaded «The REXP register 730-138 is loaded with the corrected overlaid sign for operand 2 under firmware control. A ZCRDG switch 730-136 selects the output signals RSgN 5-8 for the punched sign correction sign of operand 1. The signals ZCRDG 0-3 are activated using of an inverter 730-186 inverted and transferred to the position of the ZID switch 730-150 »If the word, close to which the corrected overpunched sign is added, picked up by the cache memory 750 and carried out the decimal unit 730 is switched through, it is stored in the RDOD register 730-154 »The character in the sign position is replaced by the corrected overpunched sign ZCRDG 0-3 »

The Boolean expression for the signal DBITT is »DBITT - (FOPlLD · DlEQOVP · (ZTNSAl · FFDÖ + ZTNSA (I) • DMPEQ) + FOP2LD · D2EQOVP · (ZTNSBl · FTEÖ "+ ZTNSA (I) · DMPEQ))

where DMPEQ is a logic signal 1 in the case that the content of the RLMP register 730-102 is equal to the content of the RTMP register 730 = 100 "

030028 / 087S

The above equation indicates that the signal DBITT is set as logic signal 0 in the case that operand 1 or operand 2 requires an over-punched sign correction during the load operation. The expression ZTNSA1 · FFDO shows a leading overpunched Sign, and the expression ZTNSA 1 · DMPEQ indicates a subsequent over-punched sign.

DlEQOVP - (DBlfX ROPl ZTNSAO) D2EQOVP - (BBITfc ROPl ZTNSBO)

During the store operation, the sign is inserted into RSGN register 730-134 and into the operand word inserted via position 1 of the ZSMR switch 730-180, as previously described.

Decimal Unit 730 - Figure 3 - Load the STC mask into the RDOD register

The firmware initiates a DUCMD-203 Load STC Mask command in the RDOD command during the occurrence of the commands (STCA and STCQ) that the Storing a character in the accumulator and in the quotient register concern. The decimal unit 730 receives the output signals RCHU 30-35 from the drawing unit 720; these signals are sent to position 1 of the ZID switch 730-150 via the buffer 730-168. Each of the output signals RCHU 30-35 leads as logic signal 1 to the fact that the corresponding six Bits of position 1 of the ZID switch 730-150 as 1-Signa-Ie appear. These groups of six bits are stored in RDOD register 730-154 via ZDOD switch 730-152.

030028/0876

4 shows the relationship between the hardware of the decimal unit 730 and the firmware in the execution control memory 701-2. The execution = addressing and branching circuits 701-1 send the control memory location addresses ZECSA 0-12 to the execution control memory 701-2 _o The microword at the "relevant address memory location is read out, and the bit positions RSCR 88, 89, 94-97 are fed to the input side of the decoding logic 730-204 belonging to the decimal unit 730, which has a conventional decoding logic circuit" Table 1 shows the bit configurations RSCR 88, 89, 94-97 for the corresponding commands or »commands DUCMD 200-206, 300-315.

The commands DUCMD 200-206, 300-315 are used to enter a status identifier in the Control logic 730-202. This unit consists of conventional flip-flops that are set in a conventional manner or to be reset »

The I cycle control state circuits 704-102 that are on the above-mentioned elsewhere (see U.S. Patent Application Serial No. 853,944} the signals FPOA ', POP HOLDM and HOLDE to the temporal Control of the decimal unit 730 for so-called assembly line or Effect pipeline operations of control unit 704. These signals are also fed to the input side of the status indicator control logic 730-202, whose Output signals of the input side of a decimal unit control logic 730-200 as well as the input side of the status indicator control logic 130-202 and the decimal unit control logic 730-200 of the decimal unit ~ control logic 730-200 the output signals DUCMD of the decimal unit decoding logic 730-204 and the descriptor information supplied by the

030028/0876

no

Control unit 704-1 via the signal lines RSIR 21-35 and ASFA 33-36 in the registers shown in FIG. 3 has been recorded.

The operands stored in cache 750 become operand processing unit 730-206 transmitted, whereby one word is transmitted over the signal lines ZDI 0-35. The operand processing unit 730-206 is indicated by the descriptor information, the status flag signals and the register and switch control signals cause the operand word off the cache memory 750 to accommodate non-operand and detach non-decimal digits characters from the word and convert the relevant word into 4-bit decimal digits and the four 4-bit decimal digits into up to align eight words with 4-bit decimal digits and pass the full word to execution unit 714 to transmit the signal lines RDOD 0-35. The output signals from the combination or logic unit 730-200 are the signals PK-VCTR 0-3 and the signals RRLTRD, RREQRD, ADSZ and condition branch signals ZAMO, the branch addresses in the execution addressing and Create branch circuits 701-1.

A clock signal controls the time relationships between the logic units according to FIG. 4.

4 illustrates the logic flow in the system. Those parts of the logic blocks according to FIG. 4 that relate to relating to the invention are illustrated in more detail in FIG.

Fig. 5 shows two typical instructions that processed by the decimal unit 730. The AD2D instruction - which concerns the addition using two decimal operands, results in the operand

030028/0876

η ή

from the address location designated by the descriptor 1 and with the address location indicated by the relevant descriptor 1 the specified format is added to the operand from the address memory location that occurs with the format, as specified by descriptor 2, with the resulting operand in the format and in the address storage parts is brought, as determined by the descriptor 2.

The AD3D instructions - the one addition using of three decimal operands affect - cause the operand to be taken from the address memory location and in the Format, as determined by descriptor 1, for the operand from the address memory location and in the Format is added as specified by descriptor 2 and that the resulting operand is in the Format and is accommodated in the address storage locations, as defined by the descriptor 3. That The instruction or command word consists of 36 bit positions 00-35.

The command format includes a P-bit which is zero-bit EBCDIC data and 1-bit ASCH data specifies.

The fields MF1, MF2 and MF3 describe the address modifications, which are to be carried out with regard to the descriptor 1, 2 and respectively.

The T bit enables the abort error ₀ The RD bit _{enables the rounding operation o} The OP code specifies the operation to be performed o Referring to Fig. 5, the operation code 202 = 1 denotes the AD2D instruction, and the operation code 222-1 denotes the instruction or the command AD3D _O The interrupt lock bit is denoted by I

030028/0876

For the descriptor formats, Y1, Y2, and Y3 are the Main memory word locations of the highest value character of the operand identified by descriptors 1, 2 and 3, respectively.

The O / E bit denotes the main memory word address as odd address or as an even address.

CN1, CN2 and CN3 denote codes that represent the Specify the position of the character with the highest value within the memory word of the operand, which is indicated by the Descriptors 1, 2 and 3, respectively. The codes depend on the data type, as illustrated below is.

Codes characters-numbers

O 1 2 3

O 1 2 3 4 5 6 7

TN1, TN2 and TN3 are codes that represent the numeric data type for descriptors 1, 2 and 3 respectively. A zero specifies a 9-bit data signal and a 1 specifies a 4-bit data signal.

The fields S1, S2 and S3 denote the sign and Decimal type of descriptor 1, 2 or 3.

030028/0878

9-bit characters 000 010 100 110 4-bit characters 000 001 010 011 100 101 110 111

00000

Unpacked data Packed data TN = 1

TN = O OVP allowed or OVP not allowed

00 LS, OVP, true to scale 00 Floating point, LS

01 LS, to scale 01 LS to scale

10 TS, to scale 10 TS to scale

11 TS, OVP, true to scale 11 no sign,

true to scale

LS = leading sign

TS = following sign

OVP = perforated sign

SF1, SF2 and SF3 denote the scale = or "scale factors of descriptors 1, 2 or" 3 "The decimal point is located after the lowest value digit _o A positive scale or scale factor shifts the decimal point by that many positions to the right. A negative scale or scale factor shifts the decimal point by that many positions to the left.

N1, N2 and N3 are the number of characters in the operand, which number is specified by the descriptors 1 _S 2 or ». 3 N1, N2 and N3 can be 4-bit codes designating the registers that contain the length of the operand concerned. However, to describe the invention, N1, N2 and N3 are the number of characters in the operand.

Decimal unit 750 - _{FJg 0} 3 ° vector branch data

Referring to FIG. 3, the decimal-control logic generates 730 = 20, the control signals 1PKVCTR ₅ 2PKVCTR and 4PKVCTR the occurrence of the DUCMD = command signals of the decimal unit 730 out, as has been described above ₀ The vector branching logic 730-15 signals have been supplied, which are characteristic of the properties of the operand. The outputs of decode logic 730-38 and

030028/0878

730-40, which will be described later, define the operand as a floating point or as an overlaid sign or as scaled operands, provided they consist of 4-bit or 9-bit decimal points. the Signals ZTNSA1 and ZTNSB1 indicate an operand with a subsequent sign if they are used as a logic signal 1 occur and they indicate an operand with a leading sign when used as a logic signal Zero occur. The signals ALNS 3-5 and the signals ALNDA 0-3 and ALNDB 0-3 designate the operand that has a set length of more than 63 decimal digits or a length of less than 63 decimal digits or has a length equal to 63 decimal digits. The detailed link arrangement is illustrated in fig.

The output signals PK-VCTR 0-3 of the vector branching logic 730-15 are sent to execution addressing and branching circuits 701-1 upon the occurrence of the control signals 1PKVCTR, 2PKVCTR and 4PKVCTR are output to the execution control memory 701-2 1 to display the next microword to be processed by the system.

According to FIG. 8, a PK-VCTR switch 15-72 generates ad vector branch signals PK-VCTR 0-3 in response to microword signals which are output to the decimal unit 730. The microword signals generate DUCMD command signals or command signals which, when linked or combined with the status identification signals, generate control signals 1PKVCTR, 2PKVCTR and 4PKVCTR. These control signals are output to the input selection terminals 1, and 4 of the switch 15-72? they lead to the selection of one of eight input signals from each of the four areas of the switch 15-72 ad.

030028/0876

While processing numeric commands that are not decimal — numeric commands, the Decimal unit 730 ineffective, whereby the input terminal O of the switch 15-72 a-d is activated.

The type-length vector signals are applied to the input terminal 1 of the switch 15-72 a-d. The signal DSHORT becomes input terminal 1 of switch 15-72a fed. If the ALNS adder 730-24 indicates that the set length of the operand is greater than one binary 16 or equal to binary 1b, then one or more of the input signals ALNS 3-5 for the AND / NAND elements 15-32, 15-34 or 15-36 as logic signals 1 emitted One or more of the output signals are connected as logic signals 0 to the inputs of a AND / NAND gate 15-38 supplied, the output signal ALNSGTE16 is fed to the input of an AND / NAND element 15-50 » It's not a decimal multiplication / Divisions command, then the output signal DLNSCLDGTE 16 issued as logic signal 0 «This Signal which is fed to the input of an AND / NAND gate 15-74, causes the output signal DLONG as Logic signal 0 is issued ,, the signals ALNDA1, ALNDA2, ALNDB1 and ALNDB2 are fed to the inputs of the UJMD / NAND elements 15-40, 15-42, 15-44 or »15-46» A logic signal 1 is sent to the other input terminals supplied »The output signals of the AND / NAwD elements 15-40 and 15-42 are fed to the inputs of an AND / NAND gate 15-52, and the output signals the AND / NAND gates 15-44 and 15-46 are fed to the inputs of an AND / NAND gate 15 = 54. The output signals ALNDAGTE 16 and ALNDBGTE 16 indicate as logic signals 1 that the length of operands 1 and 2 is shorter is as 16 decimal digits ο If the operands are not floating point operands are and if the set length

including the scale factor setting is less than 16 decimal digits, then the signal DLONG shows, the output signal of the AND / NAND gate 15-74, as a logic signal 1 indicates that both operands are or will be processed as short operands. The signal DLONG is fed to the input of an AND / NAND gate 15-56. The output signal DSHORT shows as a logic signal 1 indicates that the operand is processed as a long operand. The signal D12EQ0VP is the the other input of the AND / NAND gate 15-56 supplied; as logic signal 1 indicates the relevant signal, that neither operand 1 nor operand 2 has an interleaved sign, which is the requirement for is a short operand.

The DSHORT signal shows as a logic signal 1, that a short operand is fed to the input of an AND / NAND gate 15-58. The signal ZTNSAO shows as Logic signal 1 indicates that an operand with 9 bits per Character is delivered to the other input of the NAND gate 15-58. The output signal DHHORT 9 is used as a link signal O delivered to an input of an AND / NAND gate 15-62. The output signal DLNGORST 9 becomes as a logic signal 1 to the input terminal 1 of the Switch 15-72b, which is a short operand is displayed with nine bits per character. The logic signal 0 is the input terminal of the switches 15-72c and d supplied.

The signals TDBO and TDB1 are supplied to the input terminals and 3 of the switch 15-72b and the switch 15-72c, respectively. The Boolean expressions have already been described above; they give the number of delay cycles between the cycle in which the read request is made to the cache memory 750 and the Time at which a full word from the

030028/0878

Execution unit 714 received is “The signal ARWC 6 of the ARWC adder 730 = 60 becomes the input terminals and 3 of the switch 15 ~ 72d supplied; it shows you 1-word operands on if it is a logic signal O occurs and it indicates a 2 word operand if it occurs as link signal 1.

The input connections 4 and 6 of the switch 15-72 ad are selected for the descriptor 1 "vector or" for the storage vector operations. " over-punched sign operand is fed to an input of an AND / NAND gate 15-2. The signal ZTNSAO, which indicates an operand with nine bits per character, is fed as logic _{signal 1 to the other input of AND / NAND gate 15-2. Each input signal s} occurring as logic signal 0 causes the signal D1NEW 9, which is an input an AND / NAND element 15-14 is fed, as logic signal 1 occurs c The signals ZTJMSA1 and ZTNSA2 are fed as logic signals 1 to the other inputs of the AND / NAND element 15-14 «, the output signal D1EQFLP shows a logic signal 0 a Floating point operands on; it is fed to the input of an AND / NAND gate 15-64. The output signal D1FLPORTSO _S, which occurs as logic signal 1, indicates a floating point operand as such a logic signal.

If the signals ROP-1 and ZTNSÄÖ occur as logic signals 1, the output signal D1NEW9 of the AND / NAND element 15-2 occurs as logic _{signal 1 to 0} If the signal DBIT ^! occurs as logic signal 1, then the output signal D1EQOVP of an AND / NAND element 15 = 22 will appear as logic signal 0 »As a result, the output signal D1ZEQOVP of an AND / NAND element 15-30 will appear as logic signal 1» if the signal ZTNSA1 as

Ö30028 / 0876

Link signal 1 occurs, whereby an attached or subsequent sign is displayed, the Output signal DIEQTSO of a NAND gate 15-26 as a logic signal O lead to the output signal D1FLPORTSO of the AND / NAND gate 15-64 occurs as logic signal 1. The signal D1FLPORTSO becomes as logic signal 1 the input terminals 4 and of switch 15-72b, which creates a floating point operand or an operand with an interleaved subsequent Sign is displayed.

The output signal D1EQ0VP of the AND / NAND gate 15-22 is applied to the input terminals 4 and 6 of the switch 15-72a which means that an operand with an overlaid sign is displayed.

The signal DBITX then occurs as logic signal 1, when the signals ZTNSA1 and ZTNSA2 are fed as logic signals to an AND / NAND gate 15-4, whereby a Unsigned operand or an interleaved subsequent sign are displayed, or signals ZTNÖAO, ZTNSA1 and ZTNSA2 delivered to an AND / NÄND element 15-6, resulting in a 9-bit-per-character floating-point operand or an operand with an interleaved leading sign is displayed. The output signal D1EQFLP '9 of an AND / NAND gate 15-6 leads as logic signal 0 that Output signal DBITX of the AND / NAND gate 15-16 in a Link signal 1 over.

The logic signals 0 are selected by the connections 4 and 6 of the switches 15-72 c and d. The firmware produces a zero result and an overflow check during the memory vector operation. The descriptor 2 vector selects input terminal 5 of switch 15-72a-d. The signal D2EQ0VP is connected to the port 5 of the switch 15-72a supplied. If this

030028/0876

Signal occurs as logic signal 1 "it indicates an operand with an overlaid sign _o The signal D2EQOVP is generated in a corresponding manner as the signal DIEQOVP, which indicates an operand 1 with an overlaid sign ₀

The signal D2FLP0RTS0 is generated in a corresponding manner like the signal D1FLPORTSO, via the AND / i \! ÄWD = elements 15-28 and 15 = 66 “The relevant signal is applied to terminal 5 of switch 17 = 72b to set a floating point operand or an operand with a overlaid to display the following sign =

The input connections 5 of the switch 15-72 c, d carry a logic signal O ₀

The long input vector selects the input connection 7 of the switch 15-72 ad from ₀ The signals dTeqFEp and D2EQFLP are fed to the inputs of an AND / NAND element 15-48 o The output signal D12EQFLP is fed to the inputs of the AND / NAND elements 15-60 and 15-70 supplied »If the relevant output signal occurs as logic signal 0 j it shows a floating point = operand and converts the signals D12FLP0REL and D12FLP0R0VP into binary signals 1o Link signal 1 of the firmware indicates that the descriptor 1 and descriptor = * 2 vectors are to be executed, _etc.

When the signal D12ET3FLP as a logic signal 1 occurs _s iferden indicating to scale or scaled operands, the signal indicates ALNSLTE63 as Verknüpfungssi gna 1 0 a length of which is shorter than or equal to 63 decimal digits is "This signal is the input of the AND / NAND Elements 15-60 and 15-68 supplied "The output signals D12FLP0REL show as a logic

Ö30028 / 087S

signals 1 indicates that both operands have a length that is less than or equal to 63 decimal digits. That Signal D12EQ0VP becomes the other input of the AND / NAND gate 15-68 fed. The output signal D12OVPL63 is sent as a logic signal O to the input of the AND / MMD element 15-70 fed. The output signal D12FLP0R0VP indicates, as logic signal 1, that both operands with an overlaid sign and that the lengths are shorter than or equal to 63 decimal points.

The signal ALNSLTE63 is used as a logic signal O at the output an AND / NAND gate 15-8 generated. The input signal ALNS3 indicates a length as link signal 1, that is greater than 63 decimal digits. The FMYDV signal occurs as logic signal 1, since it is not is a multiplication / division operation. That Signal D12EQFLP occurs as logic signal 1, since no operand is a floating point operand.

The invention is therefore microprogrammed Data processing system created whose throughput or data rate is increased by an arrangement that counts the number of effective digits in an operand that is the result of a decimal-numeric instruction that is processed by the system. The arrangement takes digits of the least significant word of the relevant word Operands first, in response to a specific microword.

The arrangement has a first register which stores a number which is one less than the number of recorded words. An adder increments the output of the first register in the event that the recorded Word has a decimal JMuIl in the high value place of the word. A second register stores the output of the adder in a

03002 8/0076

0000ΠΘ

Word count area and the number of leading zeros in a digit count area o The second register is loaded in the same cycle in which the word is processed, provided that the word concerned not only contain decimal zeros

The arrangement also counts the number of leading zeros of an operand in the cycle _p in xtfelchem the operand word is processed by the decimal unitg the relevant arrangement sends the number or to counter = position to the execution unit on the occurrence of a certain microword from _o

The arrangement in question counts the number of leading zeros by first storing in a register the number of words which the decimal unit will not send out for processing, v / as determined by an instruction descriptor v / irdo if the operand is accepted by the decimal unit If _{9 is} the word of the highest order, the number of leading zeros in the operand is added to the register _s in the same cycle in which the operand word is processed by the decimal unit. This creates a count of the number of zeros in the operand, which the decimal unit will send out for processing. This counter position relating to the leading zeros is available for the firmware in response to a microword = command

3C028 / 0876

Empty soap

Claims (14)

Claims ( 1 .y decimal unit for the modification of decimal-numerical operands which are processed by a microprogrammed execution unit, characterized in that a first signal recording device is provided, which receives signals characterizing the length of the field of each operand, that a complement formation device is provided which selectively allowed to complement specific field length signals which are output to the first signal receiving device, the specific field length signals in question being indicative of the number of words to be added to the number of words contained in the length of the field of the operand, which are equal of a certain length is that a register for leading zeros is provided, which has at least a first part and a second part, that a first memory device is connected to the complement formation device and to the register for the leading zeros, which allows to store the complement signals in the first part that a second recording device is provided which allows to record a series of signals which are indicative of a most significant word and which are followed by subsequent words of the operands that with the second signal on acquisition = - device a detector device is effectively connected, which allows leading zeros within the operand words to determine that an incrementing device is connected to the detector device, which the content of the first part by a certain Q30028 / 087fi 6AD ORIGINAL Allows the number to be incremented in the event that the detector means generates an output signal, which provides an indication that the word of the delivered to the second storage means Operands contains a total of leading zeros, and that with the detector device a second memory device which allows to store encoded signals in the second part which characterize them are for the number of leading zeros that are highest within the word with the digit Significance of the operand are included, with the relevant signals for transmission to the execution unit can be used. 2. Decimal unit according to claim 1, characterized in that the length of the field signals is weighted in this way is that a binary number is displayed which is indicative of the number of decimal digits in the Field length that the three low-order signals are a binary representation of the number of decimal digits in the most significant word of the operand is that the remaining signals of the relevant length of the field signals are binary representations of the number of subsequent words in the operand, and that the complement generator for the remaining length of the field signals, the field length signals are generated which characterize are for the number of words to be added to the number of words included in the Length of the relevant field of the operand are included in such a way that the relevant length is equal to the certain length is. 3. decimal unit according to claim 2, characterized in that the specific length by the length of seven Words is given. 030028/0876 4. decimal unit according to claim 1, characterized in that the second signal receiving device is a memory device contains, which is used to store a variety of operand words that a switch and Sliding device for aligning the decimal part serves the plurality of operand words in the operand word and that transmission means are provided which allowed the operand word to be transferred to the execution unit 5. decimal unit according to claim 4, characterized in that the detector device contains an AND = logic device, the leading zeros within the line of signals that are characteristic of the word which is followed by the following words of the operand Operand words allow that the UJMD logic device is connected to a detector device which is responsive to leading zeros and which supplies an output signal in the event that the signals provide an indication that the word contains only leading zeros is connected to the most significant digit responsive detector device, which generates coded signals in the event that the signals checked by them provide an indication that the word contains the highest significant digit, and that the detector means concerned, the output signal or the coded signals in d Create a source cycle in which the operand word is aligned by the decimal unit, _etc. 6. Decimal unit according to claim 5, characterized in that the incrementing device contains a status device which makes a determination in the event that the digit of the highest value has been recorded by the detector device « 030028/0876 7. Decimal unit according to claim 6, characterized in that that the certain number is 1. 8. decimal unit, in particular according to one of claims to 7 for modifying decimal-numeric result operands, which have been processed by a microprogrammed execution unit and which are for storage are used in a memory, characterized in that a signal recording device for recording of signals is provided which are characteristic of each word of the output from the execution unit resulting operands, where the least significant word occurs as the first word and where each Word is recorded on a microword that a detector device is connected to the signal recording device which generates signals in response to the word signals in question, which decimal digits of the word lowest significant and subsequent words of the resulting operand denote that with the Detector device connected to a decoder is referring to the relevant decimal digit signals a first signal is generated, which is indicative of a decimal digit in a position of high significance of the least significant word, which has a value that is greater than the decimal value O, that the relevant Decoder generates binary signals that characterize are for the position of the decimal digit of the highest value of the word in question in the event that the decimal digit in the high-order digit has a decimal value of zero, that a word counter device is provided which, in response to a control signal, generates a counting signal which is 1 lower than the number of words of the resulting operand that are received by the first storage device, that an adder device is connected to the word counter device and the decoder device, which signals in response to the counting signal and the first signal 030028/0876 which are indicative of the number of effective words that are stored by the first storage device are included that a counting register for counting the effective digits with at least one first part and a second part is provided that the first part of the relevant counting register with the Adder device for storing signals is connected, which are indicative of the number of effective words that the second part of the relevant counting register with the detector device for Storage of the binary signals is connected, which are indicative of the number of decimal digits in the resulting word containing the most significant decimal digit in the event that each Word of the first memory device has an effective digit, and that the register in question has the Stores the number of effective digits recorded in the cycle in which the Word is transmitted from the execution unit » 9. decimal unit according to claim 8, characterized in that the receiving device includes a buffer which for receiving the word signals of the resulting operand and for generating negated output signals and confirmation output signals, which designate the decimal digits in the relevant word. 10. Decimal unit according to claim 9 _f, characterized in that the detector device generates signals on the negated signal © that are indicative of the decimal digit positions which have the decimal value zero or a value which is greater than the decimal value zero. 11. Decimal unit according to claim 1O _9, characterized in that the decoding device selectively generates signals on the decimal zero signals which 030 0 28/087 6 Bathroom original It is characteristic of decimal zero signals that contain leading zero signals that the relevant Decoding device for signals which have a value greater than the decimal value zero, Binary signals generated, which are characteristic for the position of the decimal digit of the highest significance, and that the decoding device also generates a signal which is indicative of the effective Word containing digit. 12. Decimal unit according to claim 11, characterized in that the word counter device is an AND logic device for generating the control signal contains that the AND logic device receives a first status signal supplied, which by the microword is generated in a first cycle and in each subsequent cycle that the AND logic device a second status signal is supplied, which is determined by the first status signal in a second cycle and in each of these subsequent cycles Cycles is generated, and that the control signal in the second cycle and in subsequent Cycles is generated. 13. Decimal unit according to claim 12, characterized in that the adding means by the word counter means is controlled in the second cycle and in the subsequent cycles and on the first Signal responds in each of the relevant cycles when the received from the execution unit Word contains the decimal digit in the high-order digit with a value greater than the decimal WnIl. 14. decimal unit according to claim 13, characterized in that the counting register for counting the effective 030028/0876 kO ORIGINAL Digit is enabled in each cycle, the signal being generated which is indicative of the word _{e containing the effective digit} 030028 / 087G