GB2104276A

GB2104276A - Digital information signal reproducing apparatus for disc records

Info

Publication number: GB2104276A
Application number: GB08218728A
Authority: GB
Inventors: Shigeaki Wachi
Original assignee: Sony Corp
Current assignee: Sony Corp
Priority date: 1981-06-30
Filing date: 1982-06-29
Publication date: 1983-03-02
Also published as: CA1185011A; JPS583118A; NL8202642A; JPH0223945B2; DE3224478A1; FR2508686B1; FR2508686A1; GB2104276B; US4466089A; DE3224478C2

Description

1 GB 2 104 276 A 1

SPECIFICATION

Digital information signal reproducing apparatus for disc records This invention relates to a digital information signal reproducing apparatus for disc records.

Discs are known on which a digitized audio signal or other digital information signal is recorded. By way of example, for an audio signal, an optical disc is known on which the audio signal is recorded in pulse code modulated (PCM) form. The PCM signal can be recorded at a constant angular velocity or at a constant linear velocity. In view of the higher recording density obtainable, recording at constant linear velocity is preferable.

Of course, a disc on which a PCM signal is recorded at constant linearvelocity has to be reproduced at the same constant linear velocity. In one previously proposed method of controlling the disc rotation at the constant linear velocity upon playback, the position of a pick-up is detected by a potentiometer and since the necessary rotational speed is inversely proportional to the radial position, the detected output is supplied to a divider so as to obtain a control signal. However, this arrangement is complex and expensive.

To overcome these defects it has been proposed to use the reproduced signal from the disc as the source of the control information.

A digital audio disc for use with an optical signal detection system is usually manufactured as follows. A mastering process is used to form an original disc on which pits (recesses) corresponding to 1" or "0" of a recorded signal are formed by a laser beam optically modulated by the recorded signal, and the digital audio discs are then duplicated from this original disc by the same method as that used for normal analog discs. However, depending upon the quantity of this manufacturing process, the sizes of the pits may be displaced or shifted uniformly by a predetermined amount, so even when the actual ON/OFF ratio of the recorded signal is 50%, the ON/OFF ratio of the reproduced signal is not 50%.

This is known as asymmetry. In other words, when in a waveform converting circuit of a reproducing system, the reproduced signal is converted to a pulse signal, the pulse width thereof differs from that of the recorded signal. In a previously proposed reproducing apparatus, when the signal read out from the disc is supplied to a comparator used as a waveform converting circuit so as to be waveformconverted, a reference threshold level is adjusted manually for the purpose of overcoming this prob- lem, but the adjusting operation is inconvenient.

Moreover, when the audio signal is digitized, for example, converted to a PCM signal to be recorded, the audio signal is recorded using a base band system, and not a carrier modulation system such as amplitude or frequency modulation. A modulation method such as a run length limite code is normally used. In the run length limited code, a minimum transition interval Tnin between two different data "0" and 1" is extended to enhance the recording effi- ciency and a maximum transition interval Tmax therebetween is shortened to facilitate self-clocking on playback.

The deviation of the maximum or minimum transition interval from a reference value, where the linear velocity is taken as a reference, can then be detected and used to correct velocity errors and the asymmetry.

The required correcting or compensating means includes a peak value holding circuit for deriving the maximum transition interval Tmax when it appears twice successively in the signal reproduced from the disc and peak-holding the interval, another peak value holding circuit for inverting the above maximum transition interval Tmax and peak-holding therein the inverted signal, and a circuit for deriving a difference between the outputs of the two peak value holding circuits, the differential output being used to compensate for the asymmetry. Also, a clock component contained in the signal reproduced from the disc drives a phase locked loop (PLL) circuit. The output of this PLL circuit and clock signal from a reference clock oscillator are compared with one another to control the disc drive motor.

This method uses an analog control signal system and in consequence accurate correction or compensation of the asymmetry and accurate control of the motor velocity and phase are not possible.

According to the present invention there is provided an information signal reproducing apparatus for use with a disc having recorded thereon an information signal which is modulated by a run length limited code, the apparatus comprising:

means for reproducing said information signal from said disc; a motor for rotating said disc; a comparator for comparing the level of said reproduced information signal with a threshold voltage to produce a continuous rectangular waveform signal; a first detecting means for detecting the duration of a positive polarity part of a maximum or minimum transition interval in said rectangular waveform signal and the duration of a negative polarity part of the maximum or minimum transition interval in said rectangular waveform signal; an up-down counterfor counting a clock pulse signal in such a manner that the content of the counter is increased (or reduced) when the duration of said positive polarity part is greater than a predetermined duration and that the content of the counter is reduced (or increased) when the duration of said negative polarity part is greater than said predetermined interval; a digital-to-analog converter for converting a digital signal supplied from said up-down counter to an analog signal; and means for supplying said analog signal to said comparator as said threshold voltage, thereby to produce a signal having equal intervals of positive and negative polarity parts of said maximum or minimum transition interval.

The invention will now be described by way of example with reference to the accompanying drawings, throughout which like references designate like elements, and in which:

2 GB 2 104 276 A 2 Figure 1 is a block diagram of an embodiment of information signal reproducing apparatus according to the invention; Figures 2A to 2K, 3A to 3C and 4 are signal waveform diagrams used to explain the operation of 70 the embodiment of Figure 1; and Figure 5 is a circuit diagram showing in more detail part of the block diagram of Figure 1.

Referring to Figure 1, the embodiment to be described is for use with an optical disc on which, for example, a PCM audio signal is recorded using a run length limited code modulation method. To increase the recording density, the PCM audio signal is recorded on the disc D at a constant velocity. In the run length limited code modulation method, a 80 minimum transition interval T between two diffe rent data M" and M" is extended to enhance the recording efficiency and a maximum transition inter val T,.x therebetween is shortened to make self clocking on playback easier.

Taking advantage of the fact that a modulated output wherein the maximum transition interval Tmax appears successively does not normally occur, a bit pattern in which the maximum transition interval Tmax occurs twice successively (with positive and negative polarity respectively) is used as a frame synchronizing (sync) signal. Therefore, as the frame sync signal always appears during each frame period, the disc rotation is controlled so as to make the maximum transition interval T equal to a 95 reference value.

By way of example, the maximum transition value Tma. may be 5.5 T (where T represents a bit cell period of input data to be recorded).

An optical or photo detector 1 irradiates a light beam on the disc D, detects the light beam reflected from the disc D which is modulated by the recorded signals, and converts the reflected beam to an electrical signal. The optical detector 1 provides a reproduced PCM signal SP whose waveform is blunted so as to be substantially a sine wave. The PCM signal SP is supplied through an amplifier 2 to a comparator 3, in which it is compared with a threshold voltage VT, which will be described later.

Thus a continuous rectangular output signal S. corresponding to the "V or "0" of the recorded signal is supplied by the comparator 3.

Whether or not the length of the maximum transition interval Tm,, in the reproduced signal is equal to the reference value, for example, 5.5 T is detected as follows. A clock pulse signal with a constant frequency sufficiently higher than the bit frequency of the reproduced signal is generated, the number of the clock pulses contained within the maximum transition interval T,.x of the signal SO is counted, and the resulting count is compared with the count corresponding to the reference value 5.5 T.

A counter 21 detects whether or not the maximum transition interval TmaxOf the reproduced signal is 5.5 T, and a clock generator 22 generates the clock signal with the frequency higher than the bit frequency of the reproduced signal. An output clock CP of the clock generator 22 is supplied to a clock terminal CK of the counter 21. The counter 21 is cleared when a clear terminal CL thereof is supplied with the signal M".

A clear signal generator 25 generates and supplies a clear signal to the counter 21. One input terminal of a switching circuit 23 is directly supplied with the output signal S,, (Figure 2A) derived from the comparator 3 and the other input terminal is supplied with a signal g.(Figure 213), which is the output signal S. inverted in polarity by an inverter 24. The switching circuit 23 is alternately switched to engage one or the other input terminal by a signal S,,, which will be described later, at every one frame sync period, that is, at each accurate one frame period. Therefore, the signal S,, and 9. are derived one after another from the switching circuit 23 and supplied to the clear signal generator 25.

The signal S. is also supplied to a frame sync signal detector 26 which includes a I'LL circuit. Once the disc D is pulled into the constant linear velocity, the PLL circuit is synchronized with the clock component contained in the reproduced signal SP, Based upon the clock signal derived from the PLL circuit, the frame sync signal where the maximum transition interval Tmax of 5.5 T occurs twice successively is detected. The f rame sync signal detector 26 gener- ates a detecting output signal SF which becomes M" when the frame sync signal is not detected and which becomes M" when it is detected.

Since the frame sync signal is sometimes lost due to drop-out or the like, it is arranged that the frame sync signal detector 26 supplies a signal SFG (Figure 2C) which is synchronized with the detecting signal SF and which free-wheels overthe lost signal portion of the signal SF when there is a drop-out. In this case, in the state afterthe disc D has been pulled into the constant linearvelocity, the signal SFG contains information indicating the position where the frame sync signal exists, and as shown in Figure 2C, the signal SFG is 'V' during an interval TFS comprising the frame sync signal and a small interval before and after.

The signal SM from the frame sync signal detector 26 is supplied to one input terminal of a switching ci rcu it 30.

The output signal of a quartz oscillator 28 is supplied to a frequency divider 29, from which a signal SFX (Figure 2K) with a constant period equal to the period of the frame sync signal when the linear velocity is a predetermined value, is derived and supplied to the other input terminal of the switching circuit 30. As will be apparent from Figure 2H, the signal SFX is a positive pulse signal of small pulse width.

The switching circuit 30 is switched to the side of the frequency divider 29 until the disc D has been pulled into the constant linear velocity, and its switching signal is obtained as follows. The output signal of the switching circuit 30 is supplied to and halved in frequency by a frequency divider 31A and the frequency-divided out therefrom is further sup- plied to a frequency divider 31 B, in which it is further frequency- divided by eight, that is, the output signal of the switching circuit 30 is frequency-divided by sixteen, and then supplied to a frame sync signal existence detector 32. The frame sync signal exist- ence detector 32 is also supplied with the detecting 3 GB 2 104 276 A 3 signal SF from the frame sync signal detector 26, so as to produce an output signal DFs which becomes "0" when the frame sync signal is not detected over, for example, sixteen successive frame periods, that is, when the disc D has not yet been pulled into the constant linear velocity, and which becomes 1" when the frame sync signal is detected, that is, when the disc D has been pulled into the constant linear velocity. The output signal DFS is supplied as the switching ciontrol signal to the switching circuit 30 so that when the output signal DFS is "0", the switching circuit 30 is switched to the state opposite to the state shown in the figure, and when the output signal DFS is 1", it is in the state shown in the figure.

Accordingly, when the disc D has not yet been pulled into the constant linear velocity, the switching circuit 30 produces the output SFX supplied from the frequency divider 29, while when the disc D has been pulled into the constant linear velocity, and the frame sync signal is being detected stably, the 85 switching circuit 30 supplies the signal SFG.

The signal derived from the switching circuit 30 is supplied to the clear signal generator 25 and to the frequency divider 31A. Thus, the frequency divider 31A produces a signal S, which repeats 1" and "0" alternately at each one frame period or at every one frame sync period. The signal S, is supplied to the switching circuit 23 as its switching control signal, whereby during the period when the signal S,, is, for example, 1", the switching circuit 23 is switched to the state shown in the figure, while during the period when the signal S,, is "0", it is switched to the state opposite to the state shown in the figure. Therefore, the signal S. and E.- are alternately derived from the switching circuit 23 at every one frame period or at each one frame sync period. The output signal of the switching circuit 23 is supplied to the clear signal generator 25.

The clear signal generator 25 produces the output signal of the switching circuit 23 during the period when the output signal of the switching circuit 30 is "0", and also produces the clear signal "0" during the period when the output of the switching circuit 30 is 1". This clear signal is supplied to the clear terminal CL of the counter 21.

As stated before, the counter 21 is in the clear state when the clear terminal CL thereof is supplied with the signal "0", while the counter 21 counts the input clock CP when the clearterminal CL thereof is supplied with the signal 1". Thus, when the output signal of the switching circuit 30 is "0" and the signal S. or S. is supplied to the clear terminal CL of the counter 21, during the interval of the signal S., the input clock CP is counted by the counter 21 during the transition interval of positive polarity, while during the interval of the signal S., the input clock CP is counted by the counter 21 during the transition interval of negative polarity. In short, the number of the clocks CP contained within the transition inter vais of the positive and negative polarities is counted bythe counter 21.

When the output signal of the switching circuit 30 is M", the signal supplied to the clear terminal CL of the counter 21 is "0" so that the counter 21 is put into the clear state. The time at which the output signal of the switching circuit 30 is changed over from 1 " to "0" appears in each one frame period or one frame sync period so that the counter 21 is also cleared in every one frame period or one frame sync period.

In this case, since the switching circuit 23 supplies the signals S. and Q alternately at each one frame period or one frame sync period, the detections of the lengths of the transition intervals of the positive and negative polarities are both performed at every one frame period or one frame sync period in time sharing manner.

Within one frame period or one frame sync period, the counter 21 produces an output N. which becomes "0" if there exists any longer transition interval in the signal S, or the signal 9.-where the number of clocks CP counted is more even by one clock than the number of clocks CP contained within the maximum transition interval of 5.5 T when the linear velocity of the disc D is the predetermined velocity, and which becomes M" if not. When the output N. becomes "0", the counter 21 is disabled because the output NO is supplied an enable terminal of the counter 21, and since this output N. is supplied to the clear signal generator 25, the counter 21 is no longer cleared by the signal S. or the signal-.-. This state is continued until the counter 21 is cleared by the signal SFX of the next frame period or the signal SFG of the frame sync period.

In other words, the output N,, of the counter 21 is updated at every one frame period or one frame sync period.

The output N. of the counter 21 is supplied to a D terminal of a D flipflop circuit 40. Also. by the rising edge of the signal SFX or SFG derived from the switching circuit 30 which is supplied to a terminal CK of the flip-flop 40, the output N,, of the counter 21 is latched to the D flip-flop 40. In this case, the output signal of the switching circuit 30 is delayed by the clear signal generator 25 in such manner that the counter 21 is cleared by the signal SFX or S17G after the latch of the output N. to the D flip-f lop circuit 40 is completed.

In response to the output of the D flip-flop circuit 40, the pull-in operation for the linear velocity, the velocity servo and the asymmetry correction are carried out.

A system 60 effects the pull-in operation of the constant linear velocity and the velocity servo, and a system 70 effects the asymmetry correction. The systems 60 and 70 include up-down counters 61 and 71 and output processing circuits (digital-to-analog converters) 62 and 72 for converting the counted value outputs from the counters 61 and 71 in digital-to-analog fashion, respectively. The clock signal from a clock pulse generator 50 is supplied to up-count terminals U or down-count terminals D of the up-down counters 61 and 71 in accordance with the output of the D flip-flop circuit 40.

More specifically, the clock pulse generator 50 is supplied with the output signal S, of the frequency divider 31A, from which a pulse Pu is derived at each period when this signal S, is "V and a pulse PD is derived during each period when the signal S, is "0".

The pulse Pu is supplied to the up-count terminal U of the up-down counter71 byway of agate circuit 4 GB 2 104 276 A 4 73,while the pulse PD is supplied to the down-count terminal D of the up- down counter 71 by way of a gate circuit 74. Moreover, the pulse PD is supplied through a gate circuit 63 and a change-over circuit 64 to the up-count terminal U of the up-down counter 61, and is further supplied through the gate circuit 74 and the change-over circuit 64 to the down-count terminal D of the up-down counter 61. Then, if a Q output VS of the D flip-flop circuit 40 is "1", the gate circuits 73 and 74 are opened, and if adoutput-TSthereof is 1", the gate circuit 63 is opened.

The voltage from the output processing circuit 62 is supplied to a level comparator 7 so as to develop an output signal at an output terminal 8, thereby driving a disc driving motor M, while from the output processing circuit 72 is developed a threshold voltage VTto be supplied to the comparator 3 for use in waveform conversion.

The change-over circuit 64 serves to switch the velocity servo system 60 to the phase servo system after the disc D has been pulled into the constant linear velocity, which is supplied with a pulse signal 3f,, (Figure 3A) with a frequency three times the frame frequency provided by frequency-dividing the output of the quartz oscillator 28 at a frequency divider 65 and a pulse signal 3fp (Figure 313) with a frequency three times the frequency of the frame sync signal provided by frequency-dividing the output of, for example, the PLL circuit at the frame sync signal detector 26. This change-over circuit 64 is switched so as to select either of the outputs of the gate circuits 63 and 74 by the output DFS of the frame sync signal existence detector 32 until the disc rotation has been pulled into the constant linear velocity. After the disc rotation has been pulled into the constant linear velocity, the change-over circuit 64 is switched so as to select either of the signal 3fx and 3fP, In the state in which the signals 3fx and 3fP are selected by the change-over circuit 64, the counter 61 is supplied at its up-count terminal U with the signal 3fx and is also supplied at the clowncounter terminal D thereof with the signal 3fP. Then, an Output SL of the least significant bit derived from the counter 61 is a signal that changes to "1" at each supply of the signal 3fx and changes to"O" at each supply of the signal 3fP. In other words, the signal SL is equal in period to the signal 3fx and the duty ratio thereof corresponds to the phase difference between the signals 3fx and 3fP. Since the more significant bits do not change, the motor M is supplied with a voltage changing in response to a pulse width of the least significant bit thereby controlled. That is, the phase servo becomes operable for the motor M.

The process of pulling the disc D into the constant linear velocity will now be discussed.

Until the disc D has been pulled into the constant linear velocity, the output DFS of the frame sync signal existence detector 32 is "0" so that the switching circuit 30 provides the output signal SFX (Figure 21-1) of the frequency divider 29. Therefore, the output S, of the frequency divider 31A becomes a signal Svl which repeats M" and "0" alternately at every one frame period as shown in Figure 21. Whereas, the switching circuit 23 produces the signal SO during one frame period FA when this signal S,, is "1" and the signal-g during one frame period F13 when this signal S,, is "0".

In this case, the signal SFX is the positive pulse signal with the fairly narrow pulse width, so that the clear signal generator 25 supplies the signal S,, during the period FA and the signai7. during the period FB. Thus, during the period FA, the length of the transition interval of positive polarity in the reproduced signal, and during the period FB, the length of the transition interval of negative polarity are detected over successive one frame periods.

During each of the frame periods FA and FB, the counter 21 produces the output NO which becomes M" if there exists any longer transition interval than the maximum transition interval 5.5 T where the linear velocity of the disc D is the predetermined one, namely, if the linear velocity of the disc D is slow. Therefore, while the velocity of the disc rotation is slow and until the disc D has been pulled into the constant linear velocity, the Q output VS of the D flip-flop circuit 40 is "0" and the doutput VS thereof is '1 " thus forcing only the gate circuit 63 to be opened. At this time, the change-over circuit 64 is put into such a state by the output DFS of the frame sync signal existence detector 32 as to select the output signals of the gate circuits 63 and 74. Accordingly, although the clock generator 50 generates a pulse Pu (Figure 2J) at the beginning of the period FA and a pulse PD (Figure 2K) at the beginning of the period FB, the pulse PD is supplied to the up-count terminal U of the up-down counter 61 by way of the gate circuit 63 and the change-over circuit 64, so as to increase its count value. Consequently, a gradually increasing voltage is derived from the output processing circuit 62 and is then supplied to the level comparator 7 so that the voltage applied to the motor M is increased to allow the rotational velocity of the motor M to be increased.

Since in this state, the gate circuits 73 and 74 are closed, the counter 71 of the asymmetry correction system 70 is not supplied with an up or down clock and a voltage corresponding to a previously set count value is derived from the output processing circuit 72 and is employed as the threshold voltage VT.

When the rotational velocity of the motor M is increased substantially to reach the predetermined linear velocity, the maximum transition interval T,,,. of the signal S. or S-o becomes nearly 5.5 T so that in association with the detection accuracy of the counter 21, the maximum transition intervals which are longer and shorter than 5.5 T appear, so the output N,, of the counter 21 becomes M" as well as "0". In other words, when the maximum transition interval T,x is shorter than 5.5 T, that is, the velocity is somewhat faster than the predetermined value, the output N. becomes M" so that the Q output VS of the D flip-flop circuit 40 becomes "Y, while the doutput VS thereof becomes "0". At this time, the gate circit 74 is opened to allow the clock pulse PD derived from the clock generator 50 to be supplied through it and the change-over switch 64 to the down- count terminal D of the up-down counter 61 resulting in the decrease of its count value. Therefore, the output voltage of the output processing circuit 62 is lowered GB 2 104 276 A 5 so as to decrease the rotational velocity of the motor M.

When the lengths of the intervals where the Q output VS of the D flipflop circuit 40 is 1 " an M" are equal to each other in view of the time constant of the output processing circuit 62, the count value of the up-down counter 61 becomes substantially constant, so that the output processing circuit 62 produces the voltage corresponding to this count value thereby to rotate the disc D at the constant linearvelocity.

At this time, if the clock pulse PD or Pu is derived from the clock generator 50 during the period where the Q output VS of the D flip-flop circuit 40 is 1", either the clock pulse PD or Pu is supplied to the up or 80 down counter terminal U or D of the up-down counter 71 since the gate circuits 73 and 74 are opened, whereby the asymmetry phenomenon will be corrected as will be described later.

Afterthe disc rotation has been pulled into the constant linearvelocity as set forth above, the detecting signal SF from the frame sync signal detector 26 becomes "0" so as to change the output DFS of the frame sync signal existence detector 32 to 1" so that the switching circuit 30 is switched to the position shown in the Figure, from which the signal SM is derived. Also, the change-over circuit 64 is switched by this output DFS so as to select either of the signals 3fx and 3fp, whereby the phase servo mentioned before is applied to the motor M.

Since in this state, the change-over circuit 64 is changed over to select either the signals 3fx and 3fp, the counter 21 acts as a transition interval detection circuit or detector of the asymmetry correction system 70. The signal SM derived at this time from 100 the switching circuit 30 contains information as to the interval throughout which the frame sync signal exists. Accordingly, this example so utilizes the above signal SFG that the counter 21 detects the transition interval only near the frame sync signal, that is, the portion near where the positive and negative polarities of the maximum transition inter vals T,,2x occur successively. Therefore, in this case, the correction of the asymmetry is performed so as to make the ON/OFF ratio of the maximum transition 110 interval Tnax of the frame sync signal portion in the reproduced signal equal to 50%.

If the reproduced signal happens to have the maximum transition interval Tme,,, at some time in the frame in addition to the frame sync signal portion, the asymmetry is corrected only in the portion of the frame sync signal as stated above. The reason for this is as follows.

The maximum transition interval Tm. will occur other than in the frame sync signal interval only at 120 random times. In a reproducing apparatus for a PCM audio disc, the correction of the asymmetry is generallyper-formed together with the velocity servo of the disc, in which the rotational velocity of the disc is varied throughoutthe frame period. Accordingly, any maximum transition interval Tr,,,x occurring at a random time fluctuates, so that unless the ON/OFF ratio of the signal at the specified position is compared with one another, accurate judgement of the ON/OFF ratio is impossible.

Furthermore, if the ON/OFF ratio of the signal is compared in an interval other than that of the frame sync signal, for example, when the long transition interval is caused by a scratch on the disc, the influence of the long transition interval makes the accurate correction of the asymmetry impossible. This is also considered in this embodiment.

The correction of the asymmetry will now be described.

The signal SM (Figure 2C) derived from the switching circuit 30 is supplied to the clear signal generator 25 and the frequency divider 31A. Since the signal SM is coincident in period with the frame sync signal in the reproduced signal, the output signal S, derived from the frequency divider 31 A becomes a signal S,,2 which as shown in Figure 2D repeats 1" and M" alternately at every one frame sync period and which is supplied to the switching circuit 23, so that the switching circuit 23 produces the signal S,, during one frame sync period TA where the signal S,,2 becomes 1" and the signal 9 during one frame sync period TB where the signal S,2 becomes M". Also, the output clocks Pu and PD of the clock generator 50 are respectively derived as shown in Figures 2E and 2F at the beginning of each one of the frame sync periods TA and TB.

Whereas, within each one frame sync period, the clear signal generator 25 directly produces the signal S. or S. supplied through the switching circuit 23 during the period TFS including the frame sync signal portion where the signal SM is M", and during other periods where the signal S17G is 1", the clear signal generator 25 provides a clear signal which always becomes M". This clear signal is supplied to the clear terminal CL of the counter 21, so that the counter 21 detects whether the maximum transition interval Trna. of the frame sync signal developed during this period TFs is shorter or longer than 5.5 T. During the period TA where the signal S. is derived from the switching circuit 23, the counter 21 detects the maximum transition interval T a. of positive polarity, while during the period TB where the signal S, is derived from the switching circuit 23, the counter 21 detects the maximum transition interval Tme,. of negative polarity.

The detected output N. of the counter 321 is latched in the D flip-flop circuit 40 by the rising edge of the signal SM, so thatthe Q output VS andU output V-S of the D flip-flop circuit 40 are respectively updated at each end of the periods TFs as shown in Figure 2G.

For example, during the period TA where the maximum transition interval T, jx of positive polarity is detected, if the length of the maximum transition interval Tm,,x of positive polarity in the signal S. is shorter than 5.5 T, the output N. of the counter 21 is 1" so that as shown in Figure 2G, the Q output VS of the D flip-flop circuit 40 remains 1" from the end of the period TFS within the period TA to the end of the period TFS within the following period TB. Then, while during this period, the gate circuits 73 and 74 are opened, only the pulse PD is derived from the clock pulse generator 50 during this period, and is then supplied to the down-count terminal D of the counter 71 via the gate circuit 74 thus resulting in the 6 GB 2 104 276 A 6 decrease of the count value of the counter 71 and the value of the comparing threshold voltage VT.

Since the length of the maximum transition inter val T,jx of positive polarity is shortened when as shown in Figure 4, the comparing threshold voltage VT changes to a voltage VTu which is higher than a voltage VTO in the absence of the asymmetry, the value of the comparing threshold voltage VT is decreased and corrected so as to change the voltage VTu to the correct voltage VTO as described above.

On the other hand, during the period TB where the length of the maximum transition interval T,ax Of negative polarity is detected, if the length of the maximum transition interval Tnx of negative polar ity in the signal S,, is shorter than 5.5 T, the output N, of the counter 21 also becomes 'I". But, at this time, the Q output VS of the D flip-flop circuit 40 remains I" from the end of the period TFS within the period TB to the end of the period TFS within the following period TA (the polarity of which becomes of oppo site polarity to that of Figure 2G). Then, since during this period, only the pulse Pu is derived from the clock pulse generator 50, the pulse Pu is supplied to the up-count terminal U of the up-down counter 71 through the gate circuit 73, whereby its count value is increased to allow the value of the comparing threshold voltage VTto be increased.

The length of the maximum transition interval T,ax of negative polarity is shortened when the threshold voltage VT changes to a voltage VTD which 95 is lower than the correct voltage VTO as is clear from Figure 4. Therefore, as described above, the value of the voltage VT is increased so as to correct the voltage VTD to be the correct voltage VTO.

When the disc is rotated stably at substantially constant linear velocity, if asymmetry occurs at the output of the waveform converting circuit, in response to the detected outputs of the parts of the positive and negative polarities of the maximum transition intervals T in the output of the waveform converting circuit, in response to the detected outputs of the parts of the positive and negative polarities of the maximum transition intervals Tm,, in the output of the waveform converting circuit, the up-down counter 71 is counted up or counted down to permit the asymmetry phenomenon to be corrected.

Moreover, when the phase servo is being supplied by the signals 3fx and YP to the motor M and the rotational velocity of the motor M is appreciably fluctuated by drop-out or other reasons, so that in the frame sync signal detector 26, the frame sync signal is not detected over more than sixteen successive frame sync periods, the output DFS of the frame sync signal existence detector 32 becomes M" to permit the change- over circuit 64 to be switched to the state to select either of the output signals of the gate circuits 63 and 74. By the Q output VS and the Q output VS of the D flip-flop circuit 40 which are the latch outputs of the detecting output N,, from the counter 21 to detect the maximum transition interval T,ax, the up-clock or down-clock is properly supplied to the up-down counter 61 to apply the velocity servo rapidly so as to make the linear velocity the predetermined velocity.

As the frame sync signal is detected, the output DF:s of the frame sync signal existence detector 32 gets back to 'I" so that the change-over circuit 64 is changed over into the state to make the phase servo operable.

An example of part of the apparatus of Figure 1 is illustrated in Figure 5 to which reference is now made.

The detecting output N,, of the counter 21 is derived through a NAND gate 321 N, in which when the number of the clock pulses CP contained within the period where the maximum transition interval T,,x is 5.5 T is counted, all of the counted outputs of the predetermined bits become 'I" so that the output N. of the NAND gate 21 N becomes "0".

The clock generator 22 for generating the clock CP comprises a quartz oscillator 22A and a counter 22B to frequency-divide the output from the quartz oscillator 22A. At the rising edge of the signal derived from the clear signal generator 25, the counter 22B is loaded with a predetermined value so that the beginning of the transition interval to be detected and the generation phase of the clocks CP derived from this counter 22B may always keep the constant relation therebetween.

The clear signal generator 25 comprises a NAND gate 25A and three inverters 25B, 25C and 25D. Each of the inverters 25B, 25C and 25D is used to delay the output signal derived from the switching circuit 30.

The switching circuit 23 comprises NAND gates 23A, 23B and an inverter 23C, in which the signal S. is supplied to the NAND gate 23A and the signal 9._ is supplied to the NAND gate 23B, respectively. The signal S, derived from the frequency divider 31A is supplied directly to the NAND gate 23B, and is also supplied to the NAND gate 23A via the inverter 23C, whereby the NAND gates 23a and 23B are opened alternately. The output NO of the NAND gate 21 N is supplied to the NAND gates 23A and 23B, whereby when the output N. becomes M", the NAND gates 23A and 23B are closed so as not to pass the signals S. and-gtherethrough.

The switching circuit 30 comprises three NAND gates 30A, 30B and 30C, in which the NAND gate 30A is supplied with the signal SFX of the frame period and is controlled to open/close its gate by the output DFS of the frame sync signal existence detector 32, and the NAND gate 30B is supplied when the signal SFG of the frame sync frequency and is controlled to open/close its gate by the output signal DFS inverted by an inverter 32C.

The frequency dividers 31A and 31 B are formed, in this case, by one counter.

The frame sync signal existence detector 32 comprises a counter 32A and a NAND gate 32B. The signal SF is supplied to its rest terminal R of this counter 32A and to the NAND gate 32B, while a 1/16 frequency-divided outputfrom thefrequencydividing counter31 is supplied to the clockterminal CK of the counter 32A. When the frame sync signal detector 26 detects the frame sync signal, the signal SF is "0", so that the counter 32A is in the reset state and the output DFS of the NAND gate 32B changes to 'I". Whereas, when the frame sync signal detector 26 does not detect the frame sync signal, the signal SF 7 GB 2 104 276 A 7 becomes "V so that the counter 32A is enabled to count. So, as sixteen frame sync periods have passed with the frame sync signal not detected, the 1116 frequency-divided output of the counter 31A rises to "V, so that the output of the counter 32A becomes 1" and the output DFS of the NAND gate 32B becomes "0".

The circuit portion of the clock signal generator 50 for generating the clock pulse PD comprises three inverters 50A, 50B and 50C, each of which acts as a delay circuit, a NAND gate 50D and an inverter 50E. The signal S, and the signal, which is the signal S, delayed by the inverters 50A, 50B and 50C, are supplied together to the NAND gate 50D, so that the inverter 50E produces the pulse PD with the pulse width having delay times of three inverters 50A, 50B and 50C at the beginning of the period TA or FA. Also, the clock pulse Pu generating circuit portion of the clock signal generator 50 comprises three inver- ters 50F, 5OG and 50H, each of which functions similarly as a delay circuit, a NAND gate 501 and an inverter 50J. The output of the inverter 50C and an output, which is the output of the inverter 50C delayed by the inverters 50F, 50G and 50H, are supplied to the NAND gate 501 so that the inverter 50J provides a pulse Pu with a pulse width having delay times of three inverters 50F, 50G and 50H at the beginning of the period TB or FB.

The gate circuits 63,73 and 74 are all formed of NAND gates.

The change-over circuit 64 comprises NAND gates 64A, 6413, 64C, 6413, 64E and 64F, in which the NAND gate 64A is supplied with the signal 3f,, and the NAND gate 64B is supplied with the signal YP, respectively, while the output DFS of the frame sync signal existence detector 32 is supplied to the NAND gates 64A and 64B so as to open them when the frame sync signal is stably detected. Moreover, the output of the NAND gate 63 is supplied to the NAND gate 64C and the output of the NAND gate 74 is supplied to the NAND gate 6413, respectively, while the output DFS inverted by inverter 32C is supplied to the NAND gates 64C and 64D, whereby the NAND gates 64C and 64D are opened when the frame sync signal is not detected over sixteen successive frame periods or more.

The outputs from the NAND gates 64A and 64C are supplied to the NAND gate 64E whose output is supplied to the up-count terminal U of the up-down counter 61, while the outputs of the NAND gates 64B and 64D are supplied to the NAND gate 64F whose output is supplied to the down-count terminal D of the up-down counter 61, respectively.

In this example, the counter 61 is a 4-bit counter, and in the output processing circuit 62 the counted outputs of the more significant three bits of the counted outputs of four bits derived from the counter 61 are digital-to-analog converted by resistors 62A, 62B and 62C, one end of each of which is connected in common. The counted output of the least significant bit of the counter 61 is added through a NAND gate 62F, an inverter 62G and a resistor 62H to the above D/A converted output and is employed for the phase servo.

In this case, when the full count state is brought 130 about by the up-count in the up-down counter 61 or the zero count state is brought about by the downcount therein, if the up-count and down-count operations are not stopped, this leads to misopera- tion of the servo circuit. Therefore, the outputs of the NAND gates 62D and 62E, each being supplied with the counted outputs of the more significant three bits are respectively supplied to the NAND gates 64E and 64F so as to close them when full-count and zero-count states take place in the counter 61.

The up-down counter 71 is similarly a 4-bit counter, in which its counted outputs of the more significant three bits are digital-to-analog converted by resistors 72A, 72B and 72C of the output proces- sing circuit 72 and become the threshold voltage VT.

When the lock of the phase servo is made inoperable due to any other reason, especially after the disc rotation has been pulled into the constant linear velocity, the phase servo is made OFF and the velocity servo is readily made operable so as to recover the stable state rapidly.

More specifically, in Figure 5, a constant linear velocity pull-in lock circuit 80 comprises a D flip-flop circuit 80A, NAND gates 80B and 80C and inverters 80D and 80E, in which the output DFS of the frame sync signal existence detector 32 is supplied to the NAND gate 80B and a G output of the D flip- flop circuit 80A is also supplied thereto. A D terminal of this flip-flop circuit 80A is made of high level, while a clock terminal CK thereof is supplied with the 1/16 frequency-divided output from the frequencydividing counter 31. The outputs of the NAND gates 62D and 62E are supplied to the NAND gate 80C whose output is supplied to a clearterminal CL of this D flip-flop circuit 80A via the inverter 80D.

The output of the NAND gate 80B is supplied to the phase servo NAND gate 62F, and is also supplied to the inverting input terminal of the level comparator 7 byway of the inverter 80E.

Accordingly, when the frame sync signal is supplied and the output DFS is "1", if the up-down counter 61 is at neither the full count state nor the zero count state, the output of the inverter 80D is M". Thus, the D flipflop circuit 80A is cleared to make its Q output M" so that the output of the NAND gate 80B becomes '1 " and the NAND gate 62F is opened to permit the phase servo circuit to become effective and the output of the inverter 80E whose level is equal to the comparing reference voltage of the level comparator 7 to become of low level.

On the other hand, in the state under which the output DFS is M", when the up-down counter 61 is put into the full count or zero count state, that is, a state in which the servo lock is invalid, the output of the NAND gate 80C becomes M" and the output of the inverter 80D becomes M" so that the 1116 frequencydivided output of the counter 31 supplies the clock to the D flip-flop circuit 80A so as to change its Q output to M". Then, the output of the NAND gate 80B becomes "0" so that the NAND gate 62F is closed and the signal to be supplied to the inverting input terminal of the level comparator 7 becomes of high level to allowthe velocity servo to become operable rapidly.

In addition, the reason why the counter 21 is reset 8 GB 2 104 276 A 8 by the signal SFX of the frame period derived from the quartz oscillator, so as to detect the length of the transition interval by the frame period until the disc rotation has been pulled into the constant linear velocity is described below. If the frame sync period SIFG is employed until the disc rotation has been pulled into the constant linear velocity, when the frame sync signal is not detected, this signal S17G has a frequency much higher than the frame period. This is because it becomes the frequency-divided signal with the free-running frequency of the PLL circuit, so that, with respect to a reproduced signal with a longer frame period, this signal SIFG sometimes does not contain in each period the maximum transition interval Tmax, resulting in a risk that the disc rotation will not be pulled into the constant linear velocity.

As described above, the up-down counter is used, the transition intervals of positive and negative polarities are detected in time sharing manner and the up-count operation of the counter is controlled by one detected output and the down-count operation thereof is controlled by the other detected output, thus enabling the asymmetry to br corrected.

Because the asymmetry is digitally corrected, the accuracy of the correction can be increased.

Moreover, the maximum transition interval T,a>, is detected only in the part of the data frame sync signal including the maximum transition interval Tmax so that the previously mentioned defect where the maximum transition interval Tmax is detected overthe entire interval will not occur. Moreover, during the period in which the frame sync signal is not supplied until the rotational velocity is pulled into the stable state, the maximum transition interval 100 Tmax is detected by the unit of the frame period. Therefore, even if the velocity servo is effected by the use of the detected output of the maximum transition interval T,ax, the problem of the velocity servo not being made effective will not occur.

If a signal repeating the minimum transition interval Tmir, is employed as the data frame sync signal, then as an alternative to the maximum transition interval Tmax, the minimum transition interval T is detected by the counter 21 so as to correct the asymmetry thereof.

Claims

1. An information signal reproducing apparatus for use with a disc having recorded thereon an information signal which is modulated by a run length limited code, the apparatus comprising:

means for reproducing said information signal from said disc; a motor for rotating said disc; a comparatorfor comparing the level of said reproduced information signal with a threshold voltage to produce a continuous rectangular wave- form signal; a first detecting means for detecting the duration of a positive polarity part of a maximum or minimum transition interval in said rectangular waveform signal and the duration of a negative polarity part of the maximum or minimum transition interval in said 130 rectangular waveform signal; an up-down counter for counting a clock pulse signal in such a mannerthatthe contentof the counter is increased (or reduced) when the duration of said positive polarity part is greater than a predetermined duration and that the content of the counter is reduced (or increased) when the duration of said negative polarity part is greater than said predetermined interval; a digital-to-analog converter for converting a digital signal supplied from said up-down counter to an analog signal; and means for supplying said analog signal to said comparator as said threshold voltage, thereby to produce a signal having equal intervals os positive and negative polarity parts of said maximum or minimum transition interval.

2. Apparatus according to claim 1 wherein said disc has recorded thereon a frame synchronizing signal and there are provided means for deriving said frame synchronizing signal from said reproduced information signal, means for deriving a reference signal from a reference signal source when said frame synchronizing signal is not repro- duced, and a switching means for selectively switching said means for deriving said frame synchronizing signal and said means for deriving said reference signal from one to the other, said first detecting means detecting the maximum and minimum transi- tion interval of said reproduced information signal using an output of said switching means.

3. Apparatus according to claim 1 wherein said first detecting means comprises a counter to count a clock pulse signal from a clock generating source only during the period of the maximum or minimum transition interval of said reproduced information signal.

4. Apparatus according to claim 3 further comprising:

a second up-down counter for reducing a content of said first-mentioned counter when the content is greater than a predetermined value and increasing said content when said content is less than the predetermined value; a second analog-to-digital converter for converting an output of said second up-down counter to an analog signal; and a loop for controlling said disc rotation bythe output of said digital-to- analog converter.

5. Apparatus according to claim 4 further comprising:

means for supplying a clock pulse signal to said second up-down counter; means for generating a first pulse with a frequency higher than that said frame synchronizing signal and a second pulse with a frequency higher than a frame frequency of said reproduced information signal; and a selecting circuit for selectively supplying either of the signals derived from said clock signal supplying means and said pulse generating means to said second up-down counter.

6. Apparatus according to claim 5 wherein said selecting circuit is connected to a circuit for deriving said frame synchronizing signal.

9 GB 2 104 276 A 9 7. Apparatus according to claim 5 wherein the output of said second up- down counter includes more and less significant bits, said second up-down counter is respectively supplied at its up (or down) count terminal with said clock signal and at its down (or up) count terminal with a clock signal to be compared with said clock signal so as to provide a velocity servo signal by the more significant bit or bits of the counted output of said second up-down counter and a phase servo signal by the less or least significant bits or bit thereof.

8. An information signal reproducing apparatus for use with a disc having recorded thereon an information signal which is modulated by a run length limited code, the apparatus being substantially as hereinbefore described with reference to Figure 1 of the accompanying drawings.

9. An information signal reproducing apparatus for use with a disc having recorded thereon an information signal which is modulated by a run length limited code, the apparatus being substantially as hereinbefore described with reference to Figures 1 a nd 5 of the accompanying drawings.

Printed for Her Majesty's Stationery Office, by Croydon Printing Company Limited, Croydon, Surrey, 1983. Published by The Patent Office, 25 Southampton Buildings, London, WC2A IlAY, from which copies may be obtained.