JPH01182973A - Slicing circuit - Google Patents

Abstract

PURPOSE:To equalize the time interval of the signal of a high and a low by controlling the comparison value of a comparator by the output of a phase comparator when the time interval of the binarized digital signal of a high and a low is different. CONSTITUTION:An input analog signal from a record medium is inputted from a signal input terminal 101 to a comparison circuit 102, this signal is compared by the value of a comparison level terminal 112 and converted into a binary digital signal. The output of the comparator 102 obtains a repeating pulse equivalent to the duty ratio of the frequency of double the output of a toggle flip flop 103, namely the ratio of the time interval of a high and the time interval of a low, by the toggle flip flop 103, a delay circuit 104 and an exclusive 'or' circuit 105. The output of the pulse and the comparator 102 of the equal duty ratio thus prepared is inputted into a phase comparator 106 and phase-compared. The deviation of the duty ratio is compensated by controlling the value of the comparison level terminal 112.

Description

Detailed Description of the Invention Field of the Invention The present invention relates to a slicing circuit for converting an analog signal into a binary digital signal of high and low values, and in particular, it relates to a slice circuit for converting an analog signal into a binary digital signal of high and low values. The present invention relates to a slicing circuit for converting into equal binary digital signals.

2. Description of the Related Art Optical discs, which can record conventional technical information at high density using laser light, are being actively developed in various places.

For example, the signal on this optical disk is pulse width modulated (
(hereinafter referred to as PWM). In this PWM recording, signals are recorded using pulse widths, so how to accurately detect pulse widths becomes a major issue in signal reproduction.

Generally, a slice circuit is used to detect the pulse width, but if the comparison level of this slice circuit is fixed, the pulse width cannot be detected accurately due to fluctuations in the recording laser power or recording fluctuations due to changes in the sensitivity of the medium. , there is a problem that the signal cannot be reproduced.

A conventional slice circuit for solving this problem is disclosed in, for example, Japanese Unexamined Patent Publication No. 85513/1983. FIG. 5 is a block diagram of this conventional slice circuit. 501 is an input analog signal, 502 is a slice circuit, 503 is a rising edge detection circuit, 504 is a falling edge detection circuit, 505 is a clock recovery circuit, 50
7 is a DC voltage generation circuit, 508 is data, 509 is a clock output, and 510 is a comparison level input.

The operation of the conventional slice circuit configured as described above will be explained below.

The input analog signal 501 is converted to 510 by the comparison circuit 502.
It is compared with the comparison level of , and output as a binary digital signal. A rising edge of the output signal of the slice circuit 502 is detected by a rising edge detection circuit 503. A clock regeneration circuit 505 takes in the rising edge and generates data 508 and a clock 50 synchronized therewith.
Outputs 9. On the other hand, the falling edge of the output of the comparison circuit 502 is detected by the falling edge detection circuit 504, and this falling edge and the recovered clock output 5
09 Which phase comparison is performed in the phase comparison circuit 506. The output of the phase comparator circuit is converted into a DC voltage by a DC voltage generation circuit 507, and becomes a comparison level 510 of the slice circuit 502.

With this configuration, by changing the comparison level 510 of the slice circuit 502 according to the input analog signal 501, it is possible to correctly reproduce the pulse width of a signal obtained by PWM (pulse width modulation) on the input analog signal 501. A comparison level of 51O is obtained.

Problems to be Solved by the Invention However, in the above configuration, in order to recover the clock from the rising edge of the slice circuit, a PLL (PHL) using a loop filter, VCO (voltage control excavator), etc.
ASE LOCK LOOP) must be configured, the comparison level cannot be determined unless clock recovery is performed, and the configuration for determining the comparison level becomes complicated.

In view of this, an object of the present invention is to provide a slice circuit that can obtain a comparison level for correctly reproducing the pulse width of a pulse width modulated signal with a simple configuration.

Means for Solving the Problems The present invention provides a comparison circuit for converting an input analog signal into a binary digital signal by comparing whether the input analog signal is larger or smaller than a certain comparison value. a flip-flop that inverts at the rising or falling edge of the output of the flip-flop; means for delaying the output of the flip-flop by half the inversion interval of the output of the flip-flop; a circuit for taking an exclusive OR with the output; a means for comparing the phase of the output of the comparison circuit with the output of the exclusive OR; and controlling a comparison value of the comparator by the output of the phase comparison means. 1 is a slicing circuit characterized in that it has means.

According to the above-described configuration, the present invention controls the comparison value of the comparator using the output of the phase comparator when the time intervals between the high and low levels of the binarized digital signal differ. The spacing will be equal.

Embodiment FIG. 1 shows a block diagram of a slice circuit in an embodiment of the present invention. In FIG. 1, 101 is a signal input terminal, 102 is a comparator, 103 is a toggle flip-flop that inverts at the rising edge, and 104 is a delay circuit, which has an inversion interval of 0. It has 5 times the amount of delay. 105 is an exclusive OR circuit which uses a toggle flip-flop 103, a delay circuit 104, and an exclusive OR circuit 105 to obtain twice the frequency of the toggle flip-flop. 106 is a phase comparator, 107 is a charge pump circuit,
108 is a differential circuit, 109 is an arithmetic circuit, and 110 is a sample and hold circuit control signal 111 for the output of the arithmetic circuit 109.
a sample-and-hold circuit for sampling or holding; 111 is a sample-and-hold circuit control signal;
12 is a comparison level terminal of the comparison circuit 102, and 113 is an output terminal.

The operation of the slice circuit of this embodiment configured as described above will be described below.

Consider the case where the input analog signal has a single frequency.

An input analog signal from a recording medium such as an optical disk is input to a comparison circuit 102 from a signal input terminal 101.

This signal is compared with the value of the comparison level terminal 112 and converted into a binary digital signal. The output of comparator 102 is input to toggle flip-flop 103, and its output is further input to delay line 104 and delayed. The delay circuit 104 has a delay time of 0.00000000000000 though the inversion time interval of the output of the toggle flip-flop. It has 5 times the amount of delay. The output of the delay circuit 104 is input to an exclusive OR circuit 105 and exclusive ORed with the output of the toggle flip-flop. A toggle flip-flop 103, a delay circuit 104, and an exclusive OR circuit 105 obtain repetitive pulses with an equal duty ratio (ratio of high time interval to low time interval) and a frequency twice that of the output of the toggle flip-flop. The repetition frequency of this pulse is equal to the frequency of the input analog signal.

The thus produced pulses having the same duty ratio and the output of the comparator 102 are input to a phase comparator 106 and their phases are compared.

FIG. 2 shows how the duty of the output of the comparator 102 changes depending on the value of the comparison level terminal 112 of the comparator 102. In FIG. 2, 201 indicates an input analog signal. When the value of the comparison level terminal 112 is LO, the duty ratio is reproduced equally as shown in FIG. This is compensated by controlling the

This will be explained with reference to FIG.

3(a) and (bL(c)) show the output of the comparator 102 when the values of the comparison level terminal 112 are Ll, LO, and L2 shown in FIG. 2. FIG. 3(d) 3(a) to 3(c) are input to the toggle flip-flop 103. In this way, the output of the toggle flip-flop 103 is output to the comparison circuit as shown in FIG. 3(d). Regardless of the duty of the output of the comparator 102, the pulse has an equal duty ratio and has an inversion interval twice that of the output of the comparator 102.
The output of No. 3 is input to the delay circuit 104 and delayed as shown in FIG. 3(e). The amount of delay of this delay circuit 104 (
By making DL) in FIG. 3(d) half the repetition time of the input analog signal (indicated by T in FIG. 3), the output of the exclusive OR 105 has a duty ratio as shown in FIG. 3(f). Obtain repeating pulses with equal ratio. The output of the exclusive OR circuit 105 and the output of the comparator 102 are inputted to a phase comparison circuit 106 and their phases are compared. This phase comparator 1
06 outputs are shown in FIGS. 3(g) to (1). The phase comparator 106 has two outputs, U and D, as shown in FIG.
The output of the exclusive OR circuit 105 and the comparison circuit 1 are respectively
It changes as shown in (g) to (1) depending on the phase relationship of the output of 02.

In other words, the fall of the output of the comparator circuit 102 is as shown in FIG.
As shown in a), when the falling edge of the output of the exclusive OR circuit 105 is delayed, an output is generated on U as shown in FIG. 3(g), but D remains high.

On the other hand, the fall of the output of the comparator circuit 102 is shown in FIG. 3(b).
When the falling edges of the outputs of the exclusive OR circuit 105 are equal as shown in FIG. 3(h), both D and U remain high as shown in FIG. 3(h).

Furthermore, the fall of the output of the comparator circuit 102 is shown in FIG.
), the output (f) of the exclusive OR circuit 105
When the falling edge is faster than the falling edge of , an output is generated at D as shown in FIG. 3(i), but U remains high.

The outputs U and D of the phase comparator 106 are input to the charge pump circuit 107 in FIG. 1 for converting the phase difference into a voltage value. This charge pump circuit 107 has phase difference voltage conversion characteristics as shown in FIG. That is, when the phase difference is O, the output of the charge pump circuit 107 is vO.
However, as the phase difference increases, the output increases or decreases linearly. -For example, when the high section is long as shown in FIG. 3(a), the charge pump circuit 107
The output of the charge pump circuit 107 becomes V3, and conversely, when the high period is short as shown in FIG. 3(b), the output of the charge pump circuit 107 changes to V4.

The operations of the phase comparator 106 and charge pump circuit 107 described above can be realized, for example, by Motorola's ICMC4044 (MOTOROLA MECL DATA).
BOOK).

Therefore, the output of this charge pump circuit 107 and the output VO of the charge pump circuit 107 when the phase difference is O are compared by the differential circuit 108, and the value of the comparison level terminal 112 of the comparator 102 is determined based on the error voltage value. Arithmetic circuit 109
By controlling this, the value of the comparison level terminal 112 of the comparison circuit 102 can be set and controlled so that the output duty ratios are equal.

In the above description, an analog signal with a constant frequency has been considered as an input analog signal, but in reality, signals with various time intervals are input to the comparator circuit 102. However, even in such a case, a synchronization pull-in signal called a preamble of a constant period is usually input prior to data at various time intervals. Therefore, during the period when this preamble is being input, the comparison level terminal l of the comparison circuit 102
When the value of 12 is determined and the original data is input, this predetermined value of the comparison level terminal can be used.

A sample and hold circuit "1IiIIO is provided at the output of the arithmetic circuit 109 to control the value of the comparison level terminal of the comparison circuit 102 as described above at the time of inputting the preamble,
When the original data is being input, the value of the comparison level terminal 112 held by the sample and hold circuit 110 is used. This sample and hold circuit is controlled by an external sample and hold control signal 111. Such a sample and hold circuit 110 is not necessarily required when a single frequency is input.

As described above, the toggle flip-flop 103, the delay circuit 104, and the exclusive OR circuit 105 create a reference pulse width with an equal duty ratio, and the duty ratio of the output of the comparison circuit 102 is compared with the reference pulse width using the phase comparator 106 and the charge pump 107. By detecting, the comparison circuit 102
By controlling the value of the comparison level terminal 112, it is possible to reproduce pulse widths with the same duty ratio even when the amplitude of the input analog signal changes.

As described in detail, according to the present invention, the comparison level terminal of the comparison circuit can be controlled without using a complicated configuration such as a PLL, and the practical value thereof is great.

[Brief explanation of the drawing]

FIG. 1 is a block configuration diagram of a slice circuit according to an embodiment of the present invention, FIG. 2 is a waveform diagram for explaining the influence of the value of a comparison level terminal of a comparison circuit that is a component of the slice circuit, and FIG. 4 is an explanatory diagram of the operation of the same slice circuit, FIG. 4 is an explanatory diagram of the operation of the charge pump circuit, and FIG. 5 is a block diagram showing the configuration of the conventional slice circuit. lot...signal input terminal, 102...comparison circuit, 1
03... Toggle flip-flop, 104... Delay circuit, 105... Exclusive OR circuit, 106... Phase comparator, 107... Charge pump circuit, 108...
... Differential circuit, 109 ... Arithmetic circuit, 110 ... Sample and hold circuit, 111 ... Sample and hold circuit control signal, 112 ... Comparison level terminal of comparison circuit 102, 113 ... Output terminal, 501... Regenerated analog signal, 502... Comparison circuit, 503... Rise detection circuit, 504... Fall detection circuit, 505
... Clock regeneration circuit, 606 ... Phase comparator, 5
07... DC voltage regeneration circuit, 508... Data, 5
09...Clock, 510...Comparison level. 101--4IC5 people 7j16moto102-m-biil: circuit 103-1 rise inversion toggle flip flop l0A-
-1 delay circuit tOS-m-exclusive tIy OR circuit 106-Imari comparator 107-=+7-jihonpuli]g JO&--Differential circuit 113--Idekata Wakiko Figure 1 207-- Human Analogy LO, Ll, L'l - Comparison Level Figure 2 Figure 3 1"I ---L 1 Figure 4 Value Difference

Claims (2)

[Claims] (1) A comparison circuit for converting the analog signal into a binary digital signal by comparing whether the input analog signal is larger or smaller than a certain comparison value; an inverting flip-flop, means for delaying the output of the flip-flop by half the inversion interval of the output of the flip-flop, and an exclusive OR of the output of the delaying means and the output of the flip-flop. a circuit for determining the phase of the comparator, means for comparing the phase of the output of the comparison circuit and the output of the exclusive OR, and means for controlling the comparison value of the comparator by the output of the phase comparison means. slice circuit. (2) The slice circuit according to claim 1, further comprising means for sampling or holding the comparison value of the comparator circuit.