JPH02151289A - Pll lock detection circuit for motor - Google Patents

Abstract

PURPOSE:To judge whether a recording can be executed or not by providing second latch means for latching the latch signal of first latch means, and detecting the look state of a PLL servo circuit according to the latch state of the second latch means. CONSTITUTION:A 'H' level is latched in a first D flip-flop circuit 3 at the falling edge of the output signal of a second multivibrator circuit 4. Thus, the 'H' level is latched in a second D flip-flop circuit 5 after the several pulses of the output signals of a phase comparator, i.e., when a PLL servo is effectively locked. The first flip-flop 3 might be frequently set and reset when the PLL servo does not become the lock state. In this case, since the second multivibrator circuit 4 is cleared by a 'L' level clear signal input to a bar RD terminal, no erroneous operation occurs.

Description

[Detailed description of the invention] [Industrial application field] The present invention is applicable to controlling the rotation of an optical disc.

PLL (Phas) to keep the linear velocity of rotation constant
eLocked Loop) This relates to a PLL lock detection circuit for a motor that detects a locked state in a servo.

[Conventional Example] Recently, there are signs that write-once optical discs and rewritable optical discs are becoming popular in the consumer field. In line with this trend, various optical disc devices that are capable of not only reproduction but also recording have begun to be proposed. In such an optical disc device, the rotation of the motor (for optical disc) at the position of the optical head must be kept at a constant linear velocity. Therefore, PLL
For example, if the position data of the optical head is X and the linear velocity at that position is V, then the angular velocity ω・
Since x = v, this angular velocity ω is controlled by a PLL servo to achieve a constant linear velocity V.

[Problems to be Solved by the Invention] By the way, in the above-mentioned optical disk device capable of recording and reproducing, the rotation speed of the optical disk changes depending on the position of the optical head, regardless of whether it is during playback or recording, so the PLL servo is in a locked state. It is necessary to know whether it is or not. In other words, if information is added or rewritten using the optical head when the PLL servo is not in the locked state, the addition or rewriting will not be performed correctly and the information will be read out during playback. I become unable to do so.

This invention was made in view of the above problems.

The purpose is to provide a PLL lock detection circuit for a motor that can detect the locked state of the PLL servo and determine whether or not recording is possible.

[Means for Solving the Problems] In order to achieve the above object, the present invention detects the number of rotations of an optical disk by a motor, and generates a pulse signal corresponding to this number of rotations and an optical system for recording and reproducing information from the optical disk. The phase is compared with the signal corresponding to the target position information of the head, and the linear velocity of the optical head position is kept constant.
In the PLL servo circuit that controls the motor, a first pulse generating means generates a pulse signal of a predetermined width τ based on a signal obtained during phase comparison; A first latch means that latches the state of the signal obtained by phase comparison, a second pulse generation means that generates a pulse signal of a predetermined width τ2 based on this latch signal, and a pulse signal generated by the second pulse generation means. and a second latch means for latching the latch signal of the first latch means using a pulse signal, and the locked state of the PLL servo circuit is detected based on the latched state of the second latch means. This is the summary.

[Operation] With the above configuration, in the first pulse generating means, a pulse signal having a predetermined width τ1 is generated at the timing of the phase comparison result signal obtained by the PLL servo circuit.

Then, the phase result signal is latched in the first latch means with the pulse width and at the timing of the pulse signal. Here, the pulse width τ□ is set narrower than the pulse interval of the phase result signal output when the PLL servo circuit is in the locked state. In other words, since the phase result signal expresses the phase locked state by a pulse width, the phase locked state can be detected depending on whether this pulse width is larger or smaller than 1 in the above-mentioned predetermined width. .

By the way, in the first latch means, even if the rotation speed of the motor is an integral multiple of the reference and the lock state is not established, the locked state is detected. Therefore, when pulses in a phase-locked state are continuously output from the PLL servo circuit.

In other words, it is necessary to detect the locked state only when the locked state is reliably achieved. Therefore, the phase locked state latched by the first latch means is inputted as a trigger signal of the second pulse generation signal and as a signal of the second latch means. Furthermore, the pulse width of 2 of the signal generated by the second pulse generating means is larger than the predetermined width of 1. Then, the second pulse generating means generates a pulse signal having a pulse width τ2 at the timing of the signal latched by the first latch means, and the second latch means receives the phase result signal. It is latched at the timing of a pulse signal with a pulse width τ2. As a result, this second latch means has P
The PLL servo lock state in the LL servo circuit is latched, and is latched when the lock state is reliably achieved.

[Example] Embodiments of the present invention will be described below based on the drawings.

In FIG. 1, the output signal (comparison result) from the phase comparator of the PLL servo circuit is passed through an inverter circuit 1 to a first multivibrator circuit (first pulse generating means:
For example, trigger B of LS123 (retriggerable type) 2
A first D flip-flop circuit (first latch means; for example, LS74) is input to the terminal, and the third D
Input to the terminal as latch information. The pulse signal obtained by the first multivibrator circuit 2 is output from the Q terminal and input to the clock T terminal of the first D flip-flop circuit 3. Note that the trigger A terminal of the first multivibrator circuit 2 is connected to ground, and CI! Terminal and Rε/CI! A capacitor C1 and a resistor R□ are connected to the terminal, and the time constant τ, (=
C4.R1) is set narrower than the output signal (comparison result) interval of the phase comparator at the time of maximum rotation of the motor.

The signal latched by the first D flip-flop circuit 3 is output from the Q terminal, and is sent to the second multivibrator circuit (second pulse generating means; for example, LS 123 (
The signal is input to the trigger B terminal and RD terminal of the retrigger (pull type) 4, and is input as latch information to the D terminal of the second D flip-flop circuit (second latch means; for example, LS74) 5. The pulse signal obtained by the second multivibrator circuit 4 is outputted from the Q terminal and inputted to the clock T terminal of the second D flip-flop circuit 5. The trigger A terminal of the second multivibrator circuit 4 is connected to ground, and a capacitor C2 and a resistor R are connected to the C6 terminal and the RE/Ct: terminal, and the time constant τ2 (=C
2.RZ) is set to a value larger than the above-mentioned time constant τ□. The signal latched by the second D flip-flop circuit 5 is output to the recording control system as an output signal of the motor PLL lock detection circuit.

Next, the operation of the PLL lock detection circuit of the motor configured as described above will be explained based on the second @ time chart. In addition,
A signal input manually to the PLL lock detection circuit of the motor (
The output signal of the phase comparator) is a negative pulse signal, and the PLL
It is assumed that the more the phases in the servo match, the narrower the pulse width of the negative pulse signal becomes.

First, the output signal of the phase comparator shown in FIG. 2(2) is inverted by the inverter circuit 1 and input to the first multivibrator circuit 2. Then, a negative pulse signal with a time constant τ1 is generated from the first multivibrator circuit 2 at the rising edge of the inverted output signal (as shown in FIG. 3(b)).

At this time, the input signal (output signal of the phase comparator) is latched into the first D flip-flop circuit 3 at the rising edge of the pulse signal generated by the first multivibrator circuit 2 (see (c) in the same figure). ).

In other words, when the PLL servo is not in the locked state,
Since the pulse width of the output signal of the phase comparator becomes wider, the first
The D flip-flop circuit 3 receives its output signal “1”.
L'' level is latched. However, when the PLL servo enters the lock state, the pulse width of the output signal of the phase comparator becomes narrower, so the first D flip-flop circuit 3 receives its output signal # L $ The 7th level is not latched and the 'H' level remains latched.

On the other hand, due to the latch signal output from the Q terminal of the first D flip-flop circuit 3, the second multivibrator circuit 4 generates a negative pulse signal with a time constant of 2 at the rising edge of the latch signal. At this time, the second D flip-flop circuit 5 receives the signal from the first D flip-flop circuit 3 at the rising edge of the pulse signal generated by the second multivibrator circuit 4. The output signal of the second multivibrator circuit 4 is latched (shown at (θ) in the figure). Here, when the PLL servo is not in the locked state, the rising edge of the output signal of the second multivibrator circuit 4 is the first D flip.・Since this is the latch timing of the “L” level in the flop circuit 3, the second
The D flip-flop circuit 5 is not set, and its Q
The output remains at L” level. However, the PLL
When the servo is in the locked state, the same figure (e)
However, as shown in point 2, at the falling edge of the output signal of the second multivibrator circuit 4, the first D flip-flop circuit 3 latches the 'H' level. 1 for D flip-flop circuit 5
After a few pulses, the output signal of the phase comparator becomes P
When the LL servo is in the locked state, the "H" level is latched.

Also, when the PLL servo is not in the locked state, the first flip-flop circuit 3 is frequently set,
It may be reset. In this case, as shown in □ in the same figure (e), the second multivibrator circuit 4
Since this is cleared by the "L" level signal input to the R terminal, there is no possibility of malfunction.

Here, the reason why the second multivibrator circuit 4 and the second D flip-flop circuit 5 are provided in addition to the first multivibrator circuit 2 and the first D flip-flop circuit 3 is because the rotation of the motor This is to prevent misidentification when the PLL servo is not in the locked state, and to reliably detect the locked state of the PLL servo. In the invention, the lock detection signal is output after the output signal of the phase comparator has several pulses.

Therefore, depending on the latched state of the second D flip-flop circuit 5, it is possible to detect whether or not the PLL servo of the motor that rotationally drives the optical disk is in the locked state. Therefore, if the output of the second D flip-flop circuit 5, for example, the output of the output Q terminal, is outputted as a lock state signal to the recording control system of the optical disk device, a control signal indicating whether or not recording is possible in a write-once type or rewritable type CD can be obtained. It can be used as a , and accurate rewriting can be performed.

[Effects of the Invention] As explained above, according to the PLL lock detection circuit for a motor of the present invention, when controlling a motor that rotationally drives an optical disc, the PLL servo circuit for keeping the linear velocity of the optical disc constant. a first multivibrator circuit that generates a pulse signal of a predetermined width τ at the timing of the phase comparison result signal, and a first multivibrator circuit that latches the signal state of the phase comparison using the pulse signal generated by the first multivibrator circuit. 1 D flip-flop circuit, a second multivibrator circuit that generates a pulse signal of a predetermined width τ2 at the edge of this latch signal, and a pulse signal generated by the second multivibrator circuit to generate the first D flip-flop circuit. a second D flip-flop circuit for latching the latched signal of the flip-flop circuit;
Due to the latch state of the D flip-flop circuit, the P
Since the lock state of the LL servo is detected, P
The locked state of the LL servo can be detected reliably,
It has the advantage that it can be used as a recording control signal for write-once type, rewritable type CDs, etc. in optical disk devices capable of recording and reproducing.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram of a PLL servo lock detection circuit for a motor showing an embodiment of the present invention, and FIG. 2 is an operation time chart diagram for explaining the operation of the PLL servo lock detection circuit for the motor. . In the figure, 2 is the first multivibrator circuit (retriggerable type, first pulse generation means), 3 is the first D flip-flop circuit (first latch means), and 4 is the first multivibrator circuit ( 5 is a second D flip-flop circuit (retriggerable type, second pulse generating means).
second latching means).

Claims (3)

[Claims] (1) Detect the number of rotations of the optical disk by the motor, compare the phase of the pulse signal corresponding to this number of rotations with the signal corresponding to the target position information of the optical head that records and reproduces information from the optical disk, and a first pulse generating means for generating a pulse signal of a predetermined width τ_1 based on a signal obtained during phase comparison in a PLL servo circuit that controls the motor so as to keep the linear velocity of the head position constant; a first latch means for latching the state of the signal obtained by the phase comparison with a pulse signal generated by the pulse generating means; and a second pulse generating means for generating a pulse signal of a predetermined width τ_2 using this latch signal. and a second latch means for latching the latch signal of the first latch means with the pulse signal generated by the second pulse generating means, and the PLL servo circuit according to the latched state of the second latch means. A PLL lock detection circuit for a motor that detects the locked state of the motor. (2) The first pulse generating means has a time constant τ_1 (=C
_1・R_1), and the second pulse generating means has a time constant τ_2(=C_2・R_1).
__2) in the second multivibrator circuit, the first and second latching means are D flip-flop circuits;
The signal obtained by the phase comparison is inverted and then converted to the first signal.
is input to the trigger B terminal of the multivibrator circuit, and is also input to the D terminal of the first D flip-flop circuit, and the @Q@ output of the first multivibrator circuit is input to the trigger B terminal of the first D flip-flop circuit. This first D flip-flop circuit is connected to the clock T terminal of the flip-flop circuit.
The Q output of the flop circuit is connected to the second trigger B terminal and also to the D terminal of the second D flip-flop circuit, and the @Q output of the second multivibrator circuit is connected to its second trigger B terminal. Claim 1: the second D flip-flop circuit is connected to the clock T terminal of the second D flip-flop circuit, and the @Q@ output signal of the second D flip-flop circuit is a signal for detecting the locked state of the PLL servo circuit. )
A PLL clock detection circuit for the motor described above. (3) The time constant τ_1 is narrower than the phase comparison interval obtained at the maximum rotation of the motor, and the time constant τ_2
A PLL clock detection circuit for a motor according to claim 1 or 2, wherein τ_1 is larger than τ_1.