JPS62114166A - Data separate circuit - Google Patents

Abstract

PURPOSE:To surely demodulate a read modulation signal with a comparatively simple circuit by adding a function inserting a signal compensating dropout to a phase comparison circuit of a phase locked loop. CONSTITUTION:The leading of a VCO output signal 202 of a voltage controlled oscillator and a read modulation signal 201 is detected by change point detection circuits 204, 205 and when any dropout exists, the transmission of set signals 1, 2 is stopped. Thus, a dropout detection circuit 209 inputs a set signal 3 to a dropout compensation signal Ff circuit 210. Then a dropout compensation signal insertion circuit 211 outputs the OR between the output of the circuit 210 and an UP signal 1 as an UP signal 2 to form a VOC control signal 203 via a pulse width DC converting circuit 212. The signal 203 controls the frequency of the voltage controlled oscillator to ensure the demodulation of data except the dropout period.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a data separation circuit, and more specifically,
Data separation is applied to optical disk memory devices, etc., and when reading information written on the disk, extracts the tarock component included in the read signal to synchronize the bits, and demodulates the read modulation signal. It is related to circuits.

(Prior Art) The configuration of a data separation circuit in a conventional disk drive device is described, for example, in the magazine "Interface J, May 1983 issue, P, 173-174.P, 18B-191, P.
, 196. This data separation circuit inputs a read modulation signal from the disk and outputs a demodulated signal, and mainly uses a phase-locked loop (hereinafter referred to as PLL) for extracting a self-clotter included in the read modulation signal, It consists of a synchronization section for locking in synchronization with a synchronization signal included in a modulation signal, and a demodulation section for demodulating based on the extracted self-clock.

However, according to the above-mentioned conventional data separation circuit, if the read modulation signal includes a dropout, feedback exceeding the actual frequency deviation is applied to the voltage controlled oscillator provided in the PLL, resulting in synchronization of the PLL. This has the disadvantage that the data in areas other than the dropout section is incorrectly demodulated.

In order to solve these drawbacks of the prior art, the applicant proposed a new data separation circuit in Japanese Patent Application No. 60-93371. The configuration of this data separation circuit is shown in FIG.

The data separation circuit shown in FIG. 4 receives a read modulation signal (digital signal) 101 from the disk and outputs a demodulation signal 102, and can be divided into four main parts. That is, a PLL for extracting a self-clock included in the read modulation signal 101, a synchronization section for locking the PLL in synchronization with a synchronization signal included in the read modulation signal 101, and demodulation based on the extracted self clock. They are a demodulator and a dropout compensator that detects dropout and inserts a signal to compensate for dropout.

In FIG. 4, the PLL includes a time delay circuit 1031, a phase comparison circuit 104. Loop filter 105. It consists of a voltage controlled oscillator +06 and a frequency dividing circuit 107, and the synchronization section includes a synchronization signal detection circuit 108. The main component is a gain switching circuit 109. The demodulation section consists of a demodulation circuit 110.

The dropout compensation section is a shift register 111. Change point count circuit 112. Reference clock generation circuit 113. Dropout determination circuit 114. It consists of a dropout compensation circuit 115.

Before explaining the operation, FIG. 5 shows the basic format of the signal read from the disk.

The format is "GAP", with the period being the "INDEX" signal detected every rotation of the disk.

“5YNC”, “I[) DATA”, “tlsER'
s DATA" etc. are included as basic components. "GAP" is a rotational fluctuation absorption area for rewriting data, "5YNC" is a reference signal area for locking the PLL, and "TD DATA'' is an area for recording data such as track numbers and sector numbers,
"USER"S DATA" is an area for storing user data.

Next, the operation of the data separation circuit shown in FIG. 4 will be explained. If dropout is not included, the read modulation signal 101 is directly transmitted to the synchronization signal detection circuit 108, the time delay circuit 103 . It is input to demodulation circuit +10. Read modulation signal 1
When 01 is input, the synchronization signal detection circuit 108
5YNC” of the signal format shown in Figure 5 is detected, and P
The LL gain switching circuit 109 brings the PLL gain into a "large" state. In this state, the PLL loop is instantaneously synchronized and locked to the "5YNC" signal. That is, the signal obtained by dividing the read modulation signal 101 and the output of the voltage controlled oscillator 106 by the frequency dividing circuit 107 is sent to the phase comparator circuit 1.
04, and its output passes through the loop filter 105 to form a feedback loop that is input to the voltage controlled oscillator 10B. The output signal 107 is synchronized with "5YNG" included in the read modulation signal 101.

"5YNC" (When the input of the @ number is finished, the gain switching circuit 109 is
sets the loop gain of the PLL to a "small" state. Therefore, in this state, the loop gain is "small", so
The voltage controlled oscillator +06 continues to oscillate in synchronization with "5YNC" and follows only gradual phase changes caused by fluctuations in the rotational speed of the disk.

As shown in 1- below, the signal format shown in Figure 5 is
When the PLL synchronizes with ``5YNG'', extraction of the self-clock begins, and at that timing, the following ``TD''
The modulated signal of "I]SER'S DATA" to D8T is demodulated by the demodulation circuit 110, and a demodulated signal 102 indicating the track number, sector number, or data recorded by the user is finally obtained. Here, read modulation signal 1
The time delay circuit 103 at the first stage of 01 optimizes the phase relationship between the read modulation signal lot input to the demodulation circuit 110 and the output signal of the frequency divider circuit 107, which becomes the demodulation timing signal (signal for synchronizing bits). As shown, phase comparator circuit 1
This is to provide an offset to the phase difference between the input signals of 04.

Next, the operation of the phase comparison circuit 104 will be explained with reference to FIG. As shown in FIG. 6, the inputs of the phase comparison circuit 104 are digital signals of a read modulation signal and a voltage controlled oscillator (VCO) frequency division signal, and the phase comparison circuit 104 is mainly composed of digital circuits.

Normally, the phase relationship between input signals is shown in Figure 6 (A) (B) (
There are three types of C). That is, in (A), when the phase of the read modulation signal leads the phase of the VCO frequency division signal, (
B) is a case where there is a delay, and (C) is a case where there is no lead or lag. The phase comparator circuit 104 uses a signal to "UP" (advance the phase) the oscillation frequency of the voltage controlled oscillator 106 and "DOWN" the oscillation frequency, depending on the temporal relationship between the change points of the two input signals. (to change the phase)
Set/reset the signal for

In the case of (A) in FIG. 6, the read modulation signal rises =
Since the rise of the read modulation signal is earlier than the fall of the VCO frequency division signal, the "UP" signal is set at the rise of the read modulation signal, and the "UP" signal is set at the fall of the VCO frequency division signal.

As a result of the "DOWN" signal being reset, a "l]P" signal with a pulse width proportional to the phase delay is generated.

Next, in the case of (B) in FIG. 6, the fall of the VCO frequency division signal is earlier than the rise of the read modulation signal, so the "DOWN" signal is set at the fall of the VCO frequency division signal, and the read modulation signal At the rising edge, the “P” signal and “DOWN” signal are reset, and the “DOWN” signal with a pulse width proportional to the phase advance is generated.
“A signal is generated.

In the case of (tE) in FIG. 6, the read modulation signal is located in the center of the "old G11" level section of the VCO frequency division signal, so there is no phase delay or lead, and the "UP" signal and " D
OWN” signal is only reset.

The pulse widths of these "UP" and "DOWN" signals are converted into voltage values and output from the phase comparator circuit 104, so feedback is applied to the voltage controlled oscillator 106 in the subsequent stage, and the PLL locks in synchronization with the input signal. .

Next, the operation when dropout occurs will be explained. Note that a dropout compensation unit (111 to 11) detects dropout and inserts a signal to compensate for dropout.
Since the operations other than 5) are the same as those described above, the operation of the dropout compensator will be explained here. FIG. 7 is a time chart showing the operation of the dropout compensator.

In FIG. 7, the dropout determination section (a) is the fourth
A signal with a constant period generated by the reference clock generation circuit 113 shown in the figure, which is the read modulation signal +
Dropout is determined based on the number of change points of 01.

In this case, the dropout determination section (
If the number of change points of the read modulation signal 101 in each section from (1) to (2) in a) is less than three, it is determined that dropout has occurred. The length of this determination interval and the number of change points for determining dropout can be determined by checking in advance the period of the modulation signal and the sensitivity of the PLL to the dropout signal (how long dropout must occur before synchronization is lost). decide.

For example, in (a) of the dropout determination section in Figure 7,
Hereinafter, this will be referred to as the judgment interval ■. ), at the start of the judgment interval (2), the change point (b) of the read modulation signal I is counted by the change point count circuit 112 by the trigger of the output (a) from the reference clock generation circuit 113, and the judgment At the end of section ■, " is the change point count (c)
has a value of "3°". Similarly, by triggering the reference clock generation circuit 113, the dropout determination circuit 114 detects whether the count value is less than "3". In this example, Since the count value is "3", it is not determined that it is a dropout and the process moves to the determination section ■, where the change point count circuit 112 is also connected to the reference clock generation circuit 11.
3 and starts a new dropout determination. Similarly, in the case of the determination period (3), since the count value of the change point count circuit 112 is "1" at the end, it is determined that there is a dropout, and the dropout determination circuit (d) is set. This signal is held until the end of the next non-dropout determination interval. In this example, the process continues until the end of the determination interval (■).

As described above, when a dropout is detected in the read modulation signal 101, the dropout compensation circuit 115 causes the insertion signal (g
) is inserted, resulting in a dropout compensation output (f),
It is input at the later stage. For the frequency of the insertion signal (g), select a value determined to have the least effect on data from among the standard frequencies of modulation signals (for example, the frequency of data "0"), and use the read modulation signal 101 as the reference clock. Generation circuit 11
3, a constant relationship is always maintained between the phase of the insertion signal (g) and the phase of the readout modulation signal 101. At the time of insertion, the dropout determination signal (d) is delayed by one period of the determination interval from the actual dropout interval, so the read modulation signal 10 is output by the shift register II+.
A signal (e) obtained by delaying 1 by one cycle of the determination interval is used.

The sample clock of the shift register I11 is set to be sufficiently higher than the frequency of the read modulation signal 101 to avoid any influence due to the sample.

(Problem to be Solved by the Invention) However, according to the data separation circuit previously proposed by the present applicant, even if a dropout occurs in the read modulation signal, data other than the dropout section where the PLL is out of synchronization can be Although the demodulation error no longer occurs and the reliability of demodulation can be expected to improve, the following three problems remain to be solved.

The first is that many circuits are required to detect and compensate for dropouts. The second problem is that the read modulation signal is delayed by the time required to determine dropout. The third problem is that the read modulation signal changes due to the insertion of the dropout compensation signal, making it impossible to accurately measure, for example, the error rate on the disk medium.

The present invention solves the three problems mentioned above, requires a relatively small amount of circuitry, does not cause delay or change to the read modulation signal,
One objective is to provide a data separation circuit that is not affected by dropout.

(Means for Solving the Problems) The present invention provides a phase-locked loop that extracts a self-clock in a modulated signal read from a recording medium, and a phase-locked loop that is locked in synchronization with a synchronization signal included in the modulated signal. The target is a data separation circuit that has a synchronizing section for adjusting the phase-locked loop, and a modulating section for performing modulation based on the self-clotter extracted by the phase-locked loop. The lock loop is provided with a phase comparator circuit equipped with compensation means for detecting dropout in the modulated signal and inserting a signal to compensate for the dropout.

(Function) The compensation means provided in the PLL phase comparator circuit detects the presence or absence of dropout in the read modulation signal, and when dropout is detected, inserts a predetermined signal to compensate for the dropout. work.

With this compensation, P
This prevents the LL from becoming out of synchronization, and demodulation can be performed correctly. Furthermore, the compensation means is not provided independently like the dropout compensation section shown in FIG.
Since it is included in the LL phase comparator circuit, dropout compensation can be achieved with a relatively small amount of circuitry.

(Embodiment) FIG. 1 is a block diagram showing the configuration of a data separation circuit according to an embodiment of the present invention. In addition, in Figure 1, the fourth
Elements similar to those in the figures are given the same reference numerals. The data separation circuit of this embodiment receives the read modulation signal 101 (digital signal) from the disk, and receives the demodulation signal 101 (digital signal).
2 is the output. This data separation circuit can be mainly divided into three parts. The conventional data separation circuit shown in Fig. 4 consists of four parts: a PLL, a synchronization section, a demodulation section, and a dropout compensation section. The first example is a phase comparison circuit with a dropout compensation circuit 200 as a new phase comparison circuit in the PLL, excluding the dropout compensation section to be inserted.
This is the data separation circuit shown in the figure.

FIG. 2 is a block diagram showing a detailed configuration of the phase comparator circuit 200 with dropout compensation circuit shown in FIG. The phase comparator circuit 200 with a dropout compensation circuit receives the readout modulation signal 201 and the VCO output signal 202 as input, and
A VCO with a DC level proportional to the phase difference between two signals
A control signal 203 is output. Note that each signal in FIG. 2 is a digital signal except for the VCO control signal 203. As shown in the figure, the phase comparator circuit 210 with dropout compensation circuit includes change point detection circuits 204 and 205.
, 7-piece 917091 for UP signal 7-piece 917091 for signal Signal reset circuit 208, dropout detection circuit 20
9. Flip-flop circuit 2 for dropout compensation signal
10, it is composed of a dropout compensation signal insertion circuit 211 and a pulse width DC conversion circuit 212. Among these, the dropout detection circuit 209, the dropout compensation signal flip-flop circuit 210, and the dropout compensation signal insertion circuit 211 are parts that compensate for dropouts. Note that the dropout compensation signal insertion circuit 211
is turned on and off by the PLL gain switching signal 213.

FIG. 3 is a time chart illustrating the operation of the phase comparator circuit 200 with dropout compensation circuit shown in FIG.

Next, the operation of the data separation circuit of this embodiment having the above configuration will be explained.

First, in FIG. 1, when the readout modulation signal 101 does not include dropout, the phase comparison circuit with dropout compensation circuit 200 is different from the phase comparison circuit 104 in the conventional data separation circuit shown in FIG. Perform the same action as the action. This operation is as explained using FIG. 6. Therefore, as already explained, the operation of the data separation circuit shown in FIG. 1 as a whole is exactly the same as the case in which the dropout compensator does not operate in the conventional data separation circuit shown in FIG.

Next, the operation when dropout is included in the read modulation signal +01 will be explained with reference to FIGS. 2 and 3.

In FIG. 2, when a read modulation signal 201 and a vCO output signal 202 are input, a change point detection circuit 204,
205 detects the rising edge, and outputs set signals 1 and 2 as shown in FIG. 3, respectively. Next, the set signal 1 is set to 7 solenoids 91709 for the UP signal. Similarly, the set signal 2 sets the signal number 7 917091 for the DOWN signal. The above is as shown in Figure 3. These UPP No. 1 and DOWN signals are input to the UP and DOWN signal reset circuit 20B, and the UPP No. 1 and DO
Reset signal 1 is set at the same time as both WN signals are set.
Output. This reset signal 1 is input to the UP signal signal 7 circuit 917091 circuit 20B and the DOWN signal flip-flop circuit 207, and the UPP signal 1 and the DOWN signal are reset. UPP No. 1 is then input to the dropout compensation signal insertion circuit 211, and in this case (when the read modulation signal 201 is like ■), since there is no dropout compensation signal, it becomes UPP No. 2 and pulses are generated. It is input to the width DC conversion circuit 212. The same <DOWN signal is also input to the pulse width DC conversion circuit 212. The pulse width DC conversion circuit 212 increases the DC level of the output signal, that is, the vCO control signal 203, in proportion to the pulse width of UPP No. 2, and decreases the DC level in proportion to the pulse width of the DOWN signal. In this case, UPP No. 2゜DO
Since both WN signals have the same narrow pulse width, vCO
The DC level of the control signal 203 does not change as shown in the part (■) in FIG. This is the operation of the part 0 in FIG. 3.

Next, the operation when there is no readout modulation signal, that is, when dropout occurs, as shown in the part @ in FIG. 3, will be described. When a dropout occurs as shown in the @ part, the set signal 1 is not output from the change point detection circuit 204, and therefore the UP and DOWN signal reset circuits 208
Therefore, the reset signal 1 will not be output. Therefore, the DOWN signal output from the i-minute flip-flop circuit 207 continues until the dropout ends and the reset signal 1 is output.

This state can be determined by whether or not the DOWN signal is set at the time when the set signal 2 is output from the change point detection circuit 205. Therefore, in the dropout detection circuit 209, this determination is made based on the DOWN signal and the set signal 2, and if dropout has occurred, that is, if the DOWN signal remains set at the time when the set signal 2 is output, the dropout will be detected. A set signal 3 indicating the start of out is output.

Similarly, the DOWN signal is reset when the set signal 2 is output when dropout is completed, so
The dropout detection circuit 2091 determines this and outputs a reset signal 2 indicating the end of dropout.

Flip-flop circuit 210 for dropout compensation signal
is the set signal 3 from the dropout detection circuit 209
outputs a dropout compensation signal that is set by the reset signal 2 and reset by the reset signal 2. Therefore, in this case, a dropout compensation signal as shown by ■ in FIG. 3 is output. Next, the dropout compensation signal insertion circuit 211 outputs the logical sum of the above-mentioned UPP number 1 and this dropout compensation signal as UPP number 2. Therefore U
PP No. 2 becomes as shown by [phase] in Fig. 3.

In this way, in Figure 3, when a dropout like the part marked ■ occurs, the DOWN signal becomes like the part marked ■.
Adding the dropout compensation signal [phase] to UPP No. 1,
By inputting it to the pulse width DC conversion circuit 212, V
Even if the CO control signal 203 changes temporarily like the 0 portion, it returns immediately. If you do not insert the ■ signal, it will look like the dotted line in the Q section, and the vCO control signal 203
The effect is obvious, as it shifts.

Also, even if there is only one dropout like the @ part in Figure 3, the dropout compensation signal becomes the [Yes] part for the [phase] part of the DOWN signal, and the up signal 2 becomes the ■ part. Therefore, the VCO control signal 203 also becomes like the part (■) and does not cause any deviation.

Here, dropout is compensated only when the PLL follows gradual fluctuations after synchronizing and locking to the synchronization signal, as described in the explanation of the conventional data separation circuit (Figure 4). So, in Figure 2, PL
When controlling the L gain switching signal 213 by inputting it to the dropout compensation signal insertion circuit 211, that is, when increasing the PLL gain, the dropout compensation signal is not inserted, and UPP number 1 is directly inserted into UPP number 2. use.

Therefore, as can be seen from the above explanation, if the data separation circuit with the configuration shown in FIG. , demodulated signal 102
can be obtained.

(Effects of the Invention) As described above in detail, according to the present invention, dropout compensation can be performed without requiring a large number of circuits. Also, since there is no need to insert a special signal into the input signal,
For example, signals recorded on an optical disc can be demodulated as they are without any delay. therefore,
This is effective when measuring the error rate of data, or when performing error correction and sending additional information of data to an error correction circuit. A further advantage is that there is no need to define in advance when dropout is being detected.

From the above points, the present invention can be used as an effective data separation circuit for optical disk memory devices with relatively high dropouts.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a data separation circuit according to an embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of a phase comparison circuit with a dropout compensation circuit, and FIG. 3 is a block diagram showing the configuration of a phase comparison circuit with a dropout compensation circuit. FIG. 4 is a block diagram showing the configuration of a conventional data separation circuit. FIG. 5 is a diagram showing an example of the format configuration of an input signal. FIG. 6 is a diagram showing the operation of the phase comparison circuit. FIG. 7 is a time chart for explaining the operation of the circuit shown in FIG. 4. 103--Time delay circuit 105--Loop filter 106--Voltage controlled oscillator 107--Divider circuit 108--Synchronizing signal detection circuit 109--Gain switching circuit 110-Demodulation circuit 200--Dropout Phase comparator circuit 2 with compensation circuit
04-... Change point detection circuit 205-... Change point detection circuit 206-UP Flip-flop circuit for P signal 207-D
OWN signal flip-flop circuit 208-UP, DO
WN signal reset circuit 209--Dropout detection circuit 210--Flip-flop circuit for dropout compensation signal

Claims (2)

[Claims] (1) A phase-locked loop that extracts a self-clock in a modulated signal read from a recording medium; a synchronization section that locks the phase-locked loop in synchronization with a synchronization signal included in the modulated signal; and the phase-locked loop. and a modulation unit that performs modulation based on the self-clock extracted by the data separation circuit, wherein the phase-locked loop detects a dropout in the modulation signal, and a compensation unit that inserts a signal to compensate for the dropout. A data separation circuit characterized by having a phase comparator circuit. (2) The phase comparison circuit in the phase-locked loop inputs the modulation signal and the frequency-divided signal of the output of the voltage-controlled oscillator included in the phase-locked loop, and calculates the frequency based on the change point of these input signals and their phase relationship. a first means for creating a set signal and a reset signal from the first means; and a second means for creating a frequency up pulse signal and a frequency down pulse signal of the voltage controlled oscillator using the set signal and reset signal from the first means. and third means for converting the magnitude of the pulse width of the pulse signal outputted by the second means into a DC level and outputting the same, and the compensating means converts one of the input signals from the voltage controlled oscillator into a DC level. The method further includes a circuit that adds a signal having the same pulse width as the frequency-down pulse signal to the frequency-up pulse signal as a dropout compensation signal if the frequency-down pulse signal is not reset after a period of time or more has elapsed. A data separation circuit according to claim 1 characterized by: