JP2823397B2 - Phase locked loop - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase locked loop for synchronizing an oscillation clock with a reference clock, and more particularly to stabilization of an oscillation frequency.

[0002]

2. Description of the Related Art When data transmission according to a predetermined format is performed between digital audio devices such as a compact disk player and a digital audio tape recorder, a receiving side of a transmission signal synchronizes each device with the transmission signal and receives the data. The transmission signal is configured to be demodulated into a format corresponding to each device. With this configuration, even when the formats of the signals used in the respective devices are different, it is possible to exchange data with each other.

FIG. 4 is a block diagram showing a configuration of an interface circuit that receives a transmission signal at a receiving device.
A transmission signal D _IN transmitted from a device on the transmission side is taken into the receiving circuit 1 and is input from the receiving circuit 1 to the demodulation circuit 2. The transmission signal D _IN is composed of, for example, a 4-bit fixed signal portion and a 28-bit data portion according to the format of the EIAJ (Electronic Manufacturers Association of Japan), and these 32-bit signals are continuous. In the receiving circuit 1, bit switching of the data portion of the transmission signal D _IN modulated to the biphase code is detected, and a clock DCK that matches the switching timing is extracted. This clock DCK is input to the phase lock loop 3 and configured to generate a clock BCK synchronized with the clock DCK. Demodulation circuit 2, based on the clock BCK synchronized with the transmission signal D _IN, applies processing such as demodulation to the format corresponding to the parity check and audio equipment of each bit to the transmission signal D _IN, a transmission signal D
Audio signal D of desired format synchronized with _IN
OUT is output to the next circuit.

On the other hand, a device on the transmitting side is configured to modulate a format corresponding to the audio device into a predetermined format common to each audio device, and then transmit the modulated signal to a transmission line. Therefore, according to such an interface circuit, the receiving device can obtain an audio signal D _OUT in a format corresponding to each audio device in synchronization with the transmission signal D _IN. Can be transmitted even if the formats of the files are different.

FIG. 5 is a block diagram showing a configuration of the phase lock loop 3 employed in the interface circuit.
The phase comparator 10 for comparing the phases of the clock DCK and the clock BCK includes a phase detector 11 and a charge pump 1
When the clock BCK is advanced with respect to the reference clock DCK, the ground-side MOS transistor is turned on to generate the ground potential. Conversely, when the clock BCK is delayed, the power-side MOS transistor is generated. Is turned on to generate a power supply potential. This phase comparator 10
The output PD of, passed through a low pass filter (LPF) 13, a voltage controlled oscillator as a control voltage V _C (VCO) 14
Supplied to Therefore, the clock BCK becomes the clock DC
The oscillation of the VCO 14 is controlled so as to cancel out the advance or delay of K, and the oscillation of the VCO 14
That is, the clock BCK is synchronized with the clock DCK.

[0006]

However, in the phase locked loop 3 as described above, the phase comparator 10
, The time constant of the LPF 13 which receives the output PD of the phase comparator 10 and provides it to the VCO 14 is set relatively small. This is because the rise of the phase lock loop 3 is made faster so that the interface circuit can easily follow the fluctuation of the frequency of the transmission signal D _IN , and accordingly, the switching of the frequency of the transmission signal D _IN can be handled. ing.

However, in the phase-locked loop 3 having a small time constant of the feedback path, since the minute jitter included in the output PD of the phase comparator 10 is not sufficiently absorbed in the feedback path, V
The oscillation of the CO 14 also includes jitter. Therefore, the frequency of the clock BCK is not stabilized, and as a result, an error may occur in the demodulation processing of the transmission signal D _IN in the demodulation circuit 2.

Accordingly, the present invention provides a method of
An object of the present invention is to stabilize the oscillation of the CO 14 and obtain a clock BCK with a small frequency fluctuation.

[0009]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and is characterized by a first clock having a constant period and a second clock in which a voltage-controlled oscillation circuit oscillates. A phase-locked loop that varies an oscillation frequency of the voltage-controlled oscillation circuit based on a phase difference from the first clock and synchronizes the second clock with the first clock. A phase detector for detecting a phase difference between the second clock and the second clock, and an output unit for extracting any one of two potentials having a predetermined potential difference according to a detection output of the phase detector; Control means for setting the potential difference between the two potentials to be applied to the output unit to be small when the phase difference detected by the phase detection unit is within a predetermined period.

[0010]

According to the present invention, after the second clock oscillated by the voltage-controlled oscillator of the phase locked loop is synchronized with the first reference clock, the potential difference applied to the output of the phase comparator is set to be small. Therefore, the peak value of the output of the phase comparator becomes small, and the high-frequency component is easily removed by the low-pass filter provided in the feedback path. Therefore, the control voltage supplied to the voltage controlled oscillator is stabilized, and the jitter component of the oscillation of the voltage controlled oscillator is suppressed.

[0011]

FIG. 1 is a block diagram showing the configuration of a phase locked loop according to the present invention. The phase comparator 20 outputs the clock D
A phase detector 21 for detecting a phase difference between CK and the clock BCK, and two outputs PDa and PDb of the phase detector 21
An output unit 22 that extracts and outputs a predetermined potential according to
And outputs PDa and PDb of the phase detector 21 to the output unit 22.
Of the MOS transistors T _a1 , T _a2 , T _b1 , and T ₂ . The phase detector 21 detects the phase of the clock BCK with respect to the clock DCK, and outputs a low level output PDa corresponding to the period during which the clock BCK is delayed and a high level corresponding to the period during which the clock BCK advances. Output PDb. These outputs PDa and PDb are supplied to selectors 23
The gates of the P-channel MOS transistors T _a1 and T _a2 and the N-channel MOS transistors T _b1 and T _b2 of the output unit 22 are selectively supplied from a and 23b. Also,
The source of the P-channel type MOS transistors T _a1, T _a2 and N-channel type MOS transistors T _b1, T _b2, the potential V _a1 obtained from the resistor R for dividing the power supply voltage,
_Va2 , _Vb1 , and _Vb2 ( _Va1 > _Va2 > _Vb1 > _Vb2 ) are provided, respectively. Therefore, in response to the selection pulse SLC given from the phase difference measurement unit 24 described later, the clock DC
When the phase difference between K and the clock BCK is large, that is, when the phase locked loop is not locked, the potentials V _a1 and V _b1 are extracted according to the outputs PDa and PDb, and the phase locked loop is locked. output voltage V _a2, V _b2 PDa, is taken out according to PDb output PD of the phase comparator 20 is created when in.

The output PD is L as in FIG.
The control voltage V _C is supplied to the VCO 14 through the PF 13, and the VCO 14 generates a clock BCK having a frequency corresponding to the control voltage V _C and outputs the clock BCK to the phase locked loop. FIG. 2 is a block diagram showing the configuration of the phase difference measuring unit 24, and FIG. 3 is a timing chart for explaining the operation thereof.

The phase difference measuring section 24 includes a phase detecting section 21
And an edge detection circuit 25 for detecting the rising and falling timings of the output signals PDa and PDb, a counter 26 for counting the clock HCK whose cycle is sufficiently shorter than the clock DCK, and a decoder 27 for decoding the count value of the counter 26. Is done. The edge detection circuit 25 is provided with a reset pulse RS for setting the timing at the fall of the output PDa and the rise of the output PDb.
And a stop pulse ST for setting timing at the rise of the output PDa and the fall of the output PDb. The counter 26 is reset at the timing of the reset pulse RS, counts the clock HCK, stops the counting operation at the timing of the stop pulse ST, and outputs the count value to the decoder 27. Thus, the clock D is calculated based on the number of clocks counted by the counter 26 during the period from the reset pulse RS to the stop pulse ST.
The phase difference between CK and clock BCK is represented. The decoder 27 determines the magnitude of the count value of the counter 26 with respect to a specific value, and detects whether or not the phase difference falls within a specific range. Therefore, when the phase difference between the clock DCK and the clock BCK is within a specific range, the selector 23a,
A selection pulse SL for setting the selection of 23b to the side of the MOS transistors _Ta2 and _Tb2 is generated to select the selectors 23a and 23b.
It is configured to supply to.

According to the above configuration, the phase difference between the clock DCK and the clock BCK is reduced, and when the phase lock loop is locked, the potential difference between the two potentials extracted from the output unit 22 of the phase comparator 20 is reduced. Therefore, the peak value of the output PD becomes small, and the high-frequency component of the output PD is easily absorbed by the LPF 13. In this embodiment, the output unit 22 of the phase comparator 20
Are configured in two stages, but the driving capability of the output unit 22 can be changed to three or more stages by connecting three or more pairs of MOS transistors to which different potentials are applied stepwise. it can.

[0015] Such a phase locked loop is not limited to an interface circuit, but can be used for generating a frequency synthesizer or various synchronization signals.

[0016]

According to the present invention, the frequency of the clock oscillated by the voltage-controlled oscillator after the phase locked loop is locked without impairing the operation of the phase locked loop that quickly follows the change of the basic clock frequency. Can be stabilized, the jitter of the oscillating clock is suppressed, and a clock with a stable frequency can always be supplied.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a phase locked loop according to the present invention.

FIG. 2 is a block diagram illustrating a configuration of a phase difference measurement unit.

FIG. 3 is a timing chart illustrating circuit operation.

FIG. 4 is a block diagram showing a configuration of a conventional interface circuit.

FIG. 5 is a diagram showing a configuration of a conventional phase locked loop.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Receiving circuit 2 Demodulation circuit 3 Phase lock loop 10 Phase comparator 11, 21 Phase detection part 12, 22 Output part 13 Low-pass filter 23a, 23b Selector 24 Phase difference measurement part 25 Edge detection circuit 26 Counter 27 Decoder

Claims (2)

(57) [Claims] An oscillation frequency is varied according to a control voltage.
Voltage-controlled oscillator, a first clock having a constant period,
Phase with second clock output from voltage controlled oscillator
And the output of this phase comparator are controlled.
A feedback path for feeding back the voltage-controlled oscillator as a voltage;
The first clock based on the comparison operation of the phase comparator
A measuring unit for measuring a phase difference between the first clock and the second clock;
Wherein the phase comparator includes the first clock and the first clock.
A phase detection unit for detecting a phase difference from the second clock;
Multiple resistors are connected in series between the source grounds, and
When the first and second potentials having the first potential difference are supplied
Both have a second potential difference smaller than the first potential difference.
A resistor string for supplying third and fourth potentials;
Phase difference between the second clock and the second clock is within a predetermined range.
Response to the detection output of the phase detector when
Take out the first potential or the second potential, and
The phase difference between the first clock and the second clock is
Responds to the detection output of the phase detector when it is within the specified range
To take out the third potential or the fourth potential
And a force part. 2. The detecting section according to claim 1, wherein said measuring section detects and detects a signal from said phase detecting section.
A period shorter than the period of the second clock in response to a force;
Counter that counts on
Selected according to whether or not the default value exceeds the specified value
And a decoder for providing instructions.
Item 2. A phase locked loop according to item 1.