JPH05110424A - Phase locked loop - Google Patents

Abstract

PURPOSE:To obtain a clock signal not including jitter by making an oscillation frequency of the phase locked loop stable. CONSTITUTION:An output section 22 of a phase comparator 20 comparing a phase of a clock DCK with a phase of a clock BCK consists of two stages of MOS transistors(TRs) Ta1, Ta2 and Tb1, Tb2 and potential setsVa1, Va2 and Vb1, Vb2 different stepwise from each other are given to the TRs. Outputs PDa, PDb of a phase detection section 21 are fed selectively to the MOS TRs Ta1, Tb1, or the MOS TRs Ta2, Tb2 of the output section 22 from selectors 23a, 23b. A peak level of an output PD is set lower by allowing the selectors 23a, 23b to switch the outputs PDa, PDb from the MOS TRs Ta1, Tb1 to the MOS TRs Ta2, Tb2 when the phase difference between the clocks DCK and BCK reaches a prescribed range.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase locked loop for synchronizing an oscillation clock with a reference clock, and more particularly to stabilizing the oscillation frequency.

[0002]

2. Description of the Related Art When data transmission according to a predetermined format is performed between digital audio devices such as a compact disc player and a digital audio tape recorder, the receiving side of the transmission signal synchronizes each device with the transmission signal and receives the data. It is configured to demodulate the transmission signal into a format corresponding to each device. With this configuration, it is possible to exchange data even if the formats of the signals used in the respective devices are different.

FIG. 4 is a block diagram showing the structure of an interface circuit that receives a transmission signal at a device on the receiving side.
The transmission signal D _IN transmitted from the device on the transmission side is captured by the receiving circuit 1 and input from the receiving circuit 1 to the demodulating circuit 2. The transmission signal D _IN is composed of a 4-bit fixed signal portion and a 28-bit data portion in accordance with, for example, the EIAJ (Japan Electronic Machinery Manufacturers Association) format, and these 32-bit signals are continuous. In the receiving circuit 1, switching of the bits of the data portion of the transmission signal D _IN modulated to the bi-phase code is detected, and the clock DCK that coincides with the switching timing is taken out. This clock DCK is configured to be input to the phase locked loop 3 to generate a clock BCK synchronized with the clock DCK. The demodulation circuit 2 performs processing such as parity check of each bit on the transmission signal D _IN and demodulation into a format corresponding to the audio device based on the clock BCK synchronized with the transmission signal D _IN to obtain the transmission signal D _IN .
Audio signal D of desired format synchronized with _IN
Output _OUT to the next stage circuit.

On the contrary, the device on the transmitting side is configured to modulate from a format corresponding to the audio device to a predetermined format common to each audio device and then send it out to the transmission line. Therefore, according to such an interface circuit, the receiving side device can obtain the audio signal D _OUT in a format that is synchronized with the transmission signal D _IN and is compatible with each audio device. It is possible to transmit signals even when the formats are different.

FIG. 5 is a block diagram showing the structure of the phase locked loop 3 employed in the interface circuit.
The phase comparator 10 that compares the phases of the clock DCK and the clock BCK includes a phase detector 11 and a charge pump 1.
2 and generates a ground potential by turning on the MOS transistor on the ground side when the clock BCK advances with respect to the reference clock DCK. On the contrary, when the clock BCK advances, the MOS transistor on the power source side Is turned on to generate a power supply potential. This phase comparator 10
Output PD is passed through a low-pass filter (LPF) 13, and a voltage-controlled oscillator (VCO) 14 is set as a control voltage V _C.
Is supplied to. Therefore, clock BCK is clock DC
When it advances or lags behind K, the oscillation of the VCO 14 is controlled so as to cancel it, and the oscillation of the VCO 14
That is, the clock BCK is synchronized with the clock DCK.

[0006]

However, in the phase locked loop 3 as described above, the phase comparator 10 is used.
The time constant of the feedback path for feeding back the output PD of the above to the VCO 14, that is, the time constant of the LPF 13 which receives the output PD of the phase comparator 10 and gives to the VCO 14 is set to be relatively small. This is because the fast to the interface circuit the rising of the phase-locked loop 3 is likely to follow the variation of the frequency of the transmission signal D _IN, thereby to be able to correspond to the switching of the frequency of the transmission signal D _IN ing.

However, in the phase-locked loop 3 having a small time constant in the feedback path, the minute jitter contained in the output PD of the phase comparator 10 is not sufficiently absorbed in the feedback path, so that V
The CO14 oscillation also includes jitter. Therefore, the frequency of the clock BCK is not stable, and as a result, an error may occur in the demodulation processing of the transmission signal D _IN in the demodulation circuit 2.

Therefore, according to the present invention, V of the phase locked loop 3 is
The purpose is to stabilize the oscillation of the CO 14 and obtain a clock BCK with little frequency fluctuation.

[0009]

The present invention has been made to solve the above-mentioned problems, and is characterized in that a first clock having a constant cycle and a second clock oscillated by a voltage-controlled oscillation circuit are used. In the phase-locked loop that varies the oscillation frequency of the voltage controlled oscillator circuit based on the phase difference from the clock and synchronizes the second clock with the first clock. A phase detecting section for detecting a phase difference between the clock and the second clock; and an output section for extracting one of two potentials having a predetermined potential difference according to the detection output of the phase detecting section, And a control means for setting the potential difference between the two potentials applied to the output unit small when the phase difference detected by the phase detection unit falls within a certain period.

[0010]

According to the present invention, after the second clock oscillated by the voltage-controlled oscillator of the phase-locked loop is synchronized with the reference first clock, the potential difference applied to the output section of the phase comparator is small and grounded. Therefore, the peak value of the output of the phase comparator becomes small, and the high-frequency component is easily removed by the low-pass filter provided in the feedback path. Therefore, the control voltage applied to the voltage controlled oscillator becomes stable, and the jitter component of the oscillation of the voltage controlled oscillator is suppressed.

[0011]

1 is a block diagram showing the structure of a phase locked loop according to the present invention. The phase comparator 20 uses the clock D
Phase detector 21 for detecting the phase difference between CK and clock BCK, and two outputs PDa, PDb of this phase detector 21.
An output unit 22 that extracts and outputs a predetermined potential according to
And outputs PDa and PDb of the phase detection unit 21 to the output unit 22.
Of the MOS transistors T _a1 , T _a2 , T _b1 , and T ₂ of the selectors 23a and 23b. The phase detection unit 21 detects the phase of the clock BCK with respect to the clock DCK, and outputs the output PDa that is at a low level corresponding to the period when the clock BCK is delayed and the high level corresponding to the period when the clock BCK is advanced. Output PDb is output. The outputs PDa and PDb are respectively supplied to the selector 23.
The gates of the P-channel type MOS transistors T _a1 and T _a2 and the N-channel type MOS transistors T _b1 and T _b2 of the output section 22 are selectively supplied from a and 23 _b . Also,
The sources of the P-channel type MOS transistors T _a1 and T _a2 and the N-channel type MOS transistors T _b1 and T _b2 have a potential V _a1 obtained from a resistor R for dividing the power supply voltage,
V _a2 , V _b1 , and V _b2 (V _a1 > V _a2 > V _b1 > V _b2 ) are provided, respectively. Therefore, in response to the selection pulse SLC given from the phase difference measuring unit 24 described later, the clock DC
When the phase difference between K and the clock BCK is large, that is, when the phase locked loop is not locked, the potentials V _a1 and V _b1 are taken out according to the outputs PDa and PDb, and the phase locked loop is locked. , The potentials V _a2 and V _b2 are taken out according to the outputs PDa and PDb, and the output PD of the phase comparator 20 is created.

The output PD is the same as in FIG.
The control voltage V _C is supplied to the VCO 14 through the PF 13, and the VCO 14 generates a clock BCK having a frequency corresponding to the control voltage V _C and outputs it to the phase locked loop. FIG. 2 is a block diagram showing the configuration of the phase difference measuring unit 24, and FIG. 3 is a timing diagram for explaining its operation.

The phase difference measuring section 24 includes a phase detecting section 21.
Edge detection circuit 25 for detecting the rising and falling timings of the outputs PDa and PDb, a counter 26 for counting a clock HCK having a cycle sufficiently shorter than the clock DCK, and a decoder 27 for decoding the count value of the counter 26. Composed. The edge detection circuit 25 detects the fall of the output PDa and the output PD.
A reset pulse RS that sets the timing at the rising edge of b and a stop pulse ST that sets the timing at the rising edge of the output PDa and the falling edge of the output PDb are generated. The counter 26 is reset at the timing of the reset pulse RS to count the clock HCK,
The count operation is stopped at the timing of the stop pulse ST and the count value is output to the decoder. As a result, the phase difference between the clock DCK and the clock BCK is represented by the number of clocks counted by the counter 26 during the period from the reset pulse RS to the stop pulse ST. The decoder 27 determines the magnitude of the count value of the counter 26 for a specific value, and detects whether the phase difference is within a specific range. Therefore, clock DCK and clock BCK
When the phase difference with
The selectors 23a and 2b are generated by creating a selection pulse SL for setting the selection of a and 23b to the MOS transistors T _a1 and T _a2 sides.
3b.

With the above arrangement, when the phase difference between the clock DCK and the clock BCK becomes small and the phase locked loop is locked, the potential difference between the two potentials extracted from the output section 22 of the phase comparator 20 is reduced. Therefore, the peak value of the output PD is reduced, and the high frequency component of the output PD is easily absorbed by the LPF 13. In this embodiment, the output unit 22 of the phase comparator 20
Although the MOS transistor of No. 2 has a two-stage configuration, the drive capability of the output unit 22 can be changed to three or more stages by connecting in parallel three or more pairs of MOS transistors to which different potentials are applied in stages. it can.

Further, such a phase locked loop can be used not only for the interface circuit but also for the frequency synthesizer and generation of various synchronizing signals.

[0016]

According to the present invention, the frequency of the clock oscillated by the voltage-controlled oscillator after the phase-locked loop is locked, without impairing the operation of the phase-locked loop that swiftly follows changes in the frequency of the basic clock. Can be stabilized, so that the jitter of the oscillating clock is suppressed, and a clock with a stable frequency can be always supplied.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a phase locked loop of the present invention.

FIG. 2 is a block diagram showing a configuration of a phase difference measuring unit.

FIG. 3 is a timing diagram illustrating a circuit operation.

FIG. 4 is a block diagram showing a configuration of a conventional interface circuit.

FIG. 5 is a diagram showing a configuration of a conventional phase locked loop.

[Explanation of symbols]

 1 Reception Circuit 2 Demodulation Circuit 3 Phase Lock Loop 10 Phase Comparator 11, 21 Phase Detection Unit 12, 22 Output Unit 13 Low Pass Filter 23a, 23b Selector 24 Phase Difference Measurement Unit 25 Edge Detection Circuit 26 Counter 27 Decoder

Claims (2)

[Claims] 1. An oscillation frequency of the voltage controlled oscillation circuit is changed based on a phase difference between a first clock having a constant cycle and a second clock oscillated by the voltage controlled oscillation circuit, and the oscillation frequency of the voltage controlled oscillation circuit is changed with respect to the first clock. In the phase-locked loop that synchronizes the second clock, the phase comparator responds to a phase detection unit that detects a phase difference between the first clock and the second clock, and a detection output of the phase detection unit. And an output unit for extracting one of the two potentials having a predetermined potential difference, and a potential difference between the two potentials given to the output unit when the phase difference detected by the phase detection unit falls within a certain period. A phase-locked loop comprising: a control unit for setting a small value. 2. The control means sets the potential difference between the two potentials to be given to the output section in a stepwise manner as the phase difference between the first clock and the second clock decreases. The phase-locked loop according to claim 1.