GB2091920A - Frequency changer - Google Patents

Abstract

In a PROM 5 the ratio of the number (x) of locations storing a binary "1" to the total locations (y) is arranged to equal the ratio of an output frequency at C to an input frequency applied to a cyclic counter 4 which also counts to y. On each count of the counter a respective location of the PROM 5 is addressed so that on one cycle of y input pulses x output pulses are obtained. The input pulses to the counter may be obtained after multiplication and/or division at unit 3 from a signal generator. The output at C may be divided by a divider 6. A plurality of similar units fed from a common generator may provide a number of different frequencies. <IMAGE>

Description

SPECIFICATION Signal generators The present invention relates to signal generators and in particular to such generators for deriving a square wave output from a signal source having a different frequency to the frequency required at the output.

In many applications, for example frequency divisions multiplexing, a range of signals having differing frequencies are required. Since the frequency of each of the signals is required to have a fixed relationship with the frequencies of the other signals it is preferable to derive all of the signals from a signal source having an accurately controlled frequency such as a crystal controlled oscillator.

However, when the relationship of the frequency of the source signal and the frequency of the output signal is not an integer (whole number) relationship the required circuit to effect the frequency division may be complicated and hence expensive.

One solution to the provision of non-integer related frequency outputs is disclosed in United Kingdom Patent No. 1,002,733. The apparatus disclosed in Patent No. 1,002,733 uses pulse suppression to provide an output signal having the correct frequency but the method results in an uneven output square wave. An uneven output square wave is a square wave in which the time elapsed between successive transitions of the output is not constant. Such a signal is sometimes referred to as having an unequal mark/space ratio.

It is an object of the present invention to provide a square wave generator which is capable of deriving a square wave which is substantially even and which has a non-integer frequency relationship with a source signal from which it is derived.

According to the present invention a signal generator for generating a square wave output comprises a cyclic multi-digit counter which is arranged to be regularly sequenced by an input signal, storage means arranged to store a single binary digit value at each of a plurality of locations which are addressed in turn by a plurality of signals supplied by said counter characterising the state of said counter at any time, and a frequency divider which is arranged to respond to signals supplied by the storage means in response to said addressing to provide a square wave output signal, the relationship between the dividing factor of the frequency divider and the ratio of the respective quantities of the alternate binary digit values in the series stored in said storage means to each other being such that the output signal has a non integer relationship with the input signal and is one in which inequalities in the time elapsed between each successive transition of the output signal are substantially eliminated.

Preferably frequency dividing or multiplying means are provided between the input of said multi-digit counter and a signal source providing the input signal.

The storage means may be of the kind shown as a read-only memory (R.O.M.) having a plurality of locations each storing a binary digit. A plurality of cyclic multi-digit counters may be provided each being arranged to be regularly sequenced by the same input signal and each supplying a plurality of signals to address a respective plurality of locations of a respective plurality of storage means, the respective storage means providing signals to respective frequency dividers each of which responds to the signals to provide a respective square wave output signal.

One example of a signal generator in accordance with the invention will now be described with reference to the accompanying drawings in which: Figure 1 shows the generator in block schematic form and Figure 2 shows waveforms at various points in the generator of Fig. 1.

Referring to Fig. 1 the apparatus which is supplied with signals having a sinusoidal waveform by a signal generator 1 comprises a squarer 2 to provide a square wave signal of frequency fe a divider/multiplier 3 the output of which is connected to a sequential address counter 4. The output of the address counter 4 is used to address a programmable read-only-memory (PROM) 5, the binary output of which is divided by a counter 6. The apparatus functions as follows the divider/multiplier 3, which is of known form, multiplies the output of the signal generator 1 by 2m-n. The sequential address counter 4 counts the output pulses of the divider/multiplier 3 sequentially from zero to Yand then resets to zero.

The PROM stores Ybits in binary form of a programmed sequence consisting of X binary 'one' bits and (Y-X) binary 'nought' bits. Each step of the address counter 4 causes a respective one of the bits stored in the PROM 5 to be output to the divider circuit 6 which is arranged to change its output state (between binary 'one' and binary 'nought' alternately) each time 2m transitions of the output of the PROM 5 have occurred.

Thus if the required output frequency is 'fo' Yis selected to be equal to the source frequency 'fc' divided by 2n which is greater than or equal to twice 'fo'.

To determine the required transitions of the output of the PROM 5 the programmed sequence X must have an average frequency of 'fo' and ignoring for the present the multiplying effect of the divider/multiplier 3 and the dividing effect of the divider 6 (the net result of which is selfcancelling) X fc fo = . (1) Y 2n X The fractionmay be reduced to its V simplest form by dividing the numerator and denominator successively by two so that x fc fo = . (2) y 2" and a sequence of x pulses is produced over an interval of y pulses, thus the address counter 4 must count from zero to y and the PROM 5 must store y bits having 'x' binary 'one' bits and (y-x) binary 'nought' bits.It will be appreciated that the sequence is not regular unless a direct numerical (whole number) relationship exists between 'fc' and 'fo'.

In order to produce a more even relationship between the output pulses the input to the address counter 4 is effectively multiplied by 2m by the divider/multiplier 3 so that the output of the PROM 5 is 2m times 'fo'. Subsequently division of the output by 2m by the divider circuit 6 substantially eliminates the irregularity present in the sequence of x pulses at the output of the square wave generating apparatus shown.

As a typical example if the source frequency 'fs' is 5280 kilohertz and the required output frequency 'fo' is 612 kilohertz fs then fS must be greater than or equal to fo.

2n 5280 Putting n equal to 2 gives ------ = 1320 4 which is greater than twice times 612 and satisfies the requirement.

By substitution in equation (1) above X 612 = 1320 V X 612 therefore - V 1320 This may be reduced to derive an equivalent equation (2).

x 153 y 330 Thus x = 153 and y = 330 and the addressed space of the PROM 5 is therefore 330 locations, the sequential counter 4 being arranged to count from zero to 330 each time a pulse is received from the divider/multiplier 3. 153 of the PROM 5 locations will be set to binary 'one' with a distribution such that a minimum of irregularity occurs.

A suitable arrangement of bits stored at successively addressed locations of the PROM 5 for the example given may be as follows (using '0' and '1' to indicate the respective states): 0101010100101010101001010101010010101010 1001010101010101010100101010101001010101 0100101010101001010101010101010100101010 1010010101010100101010101001010101010101 0101010101010100101010100101010101001010 1010100101010101001010101010101010100101 0101010010101010100101010101001010101010 101010100101010101 The value of m is determined in accordance with the required smoothing of the output. Thus if the irregularity of the output is acceptable m may be zero and the divider 6 may be dispensed with. If however m and n have the same value, the divider/multiplier 3 will not be required.

It will be appreciated that m may be larger than n particularly if an as near regular output signal as possible is required.

In the example above if m is three (giving a division of eight by the divider 6), the effect of the "double nought" sequences (as indicated by underlining) held in the PROM store 5 will be negligible.

Referring to Fig. 2 the signals which may be expected at the points marked alphabetically in Fig. 1 are similarly referenced. It will be appreciated that the signals shown are hypothetical and do not relate to a specific example.

It will also be appreciated that a plurality of divider/multipliers 3, address counters 4, PROMs 5 and dividers 6 may be connected in parallel to a single signal generator 1 and squarer 2 to provide a respective plurality of different frequency output square waves.

If an output signal having a sinusoidal waveform is required the output of the divider(s) 6 may be connected to suitable filter networks to provide a sinusoidal output signal of frequency fo.

Claims (7)

1. A signal generator for generating a square wave output signal comprising a cyclic multidigit counter which is arranged to be regularly sequenced by an input signal, storage means arranged to store a single binary digit value at each of a plurality of locations which are addressed in turn by a plurality of signals supplied by said counter characterising the state of said counters at any time, and a frequency divider which is arranged to respond to signals supplied by the storage means in response to being addressed as aforesaid to provide a square wave output signal, the relationship between the dividing factor of the frequency divider and the ratio of the respective quantities of the alternate binary digit values in the series stored in said storage means to each other being such that the output signal has a non integer relationship with the input signal and is one in which inequalities in the time elapsed between each successive transition of the output signal are substantially eliminated.

2. A signal generator as claimed in Claim 1 in which further frequency dividing or frequency multiplying means are provided between the input of said multi-digit counter and a signal source providing the input signal.

3. A signal generator for generating a plurality of square wave signals each having a different fundamental frequency comprising a plurality of cyclic multi-digit counters each arranged to be regularly cycled by a single input signal, a plurality of storage means each arranged to store a single binary digit value at each of a plurality of locations which are addressed in turn by a plurality of signals supplied by different counters of said plurality of counters characterising the state of the respective counter at any time, and a plurality of frequency dividers each arranged to respond to signals supplied by a different one of said plurality of storage means in response to being addressed as aforesaid to provide a square wave output signal, the relationship between the dividing factor of each frequency divider and the ratio of the respective quantities of the alternate binary digit values in the series stored in associated storage means to each other being such that the output signal may have a non integer relationship with the input signal and is one in which inequalities in the time elapsed between each successive transition of the output signal are substantially eliminated, the arrangement being such that the output signals supplied by said frequency dividers have different frequencies.

4. A signal generator as claimed in any preceding claim in which the storage means is/are of the kind known as read-only-memory (R.O.M.).

5. A signal generator as claimed in any preceding claim in which the input to the signal generator is by way of a squaring circuit such that an input signal sequencing the cyclic multidigit counter(s) is presented to the counter(s) as having instant transitions.

6. A signal generator as claimed in any preceding claim in which the square wave output(s) is/are supplied to a filtering network to provide a respective sine wave output/respective sine wave outputs.

7. A signal generator substantially as hereinbefore described with reference to the accompanying drawing.