SU809291A1 - Multichannel switching apparatus - Google Patents

Description

The device is related to telemechanics and automation and can be used in automated systems for monitoring and controlling multi-parameter objects. A multichannel coaxial switch containing a clock driver is known. impulses connected to a matrix distributor, each output of which is connected to an amplifier, compensated switches, half-wave and two-half-wave rectifiers, one of which is connected to the AC source and the supply circuit of the clock pulse former, amplifier and counting circuit of the countershaft distributor. also an adversionary switchboard of the 1hator, containing a block of sensors, the output of which is connected to the input of the block for determining the current required sampling frequency and the first input of the switching unit, sec The input of which is connected to the first output of the software control unit, the second output of which is connected to the first output of the switch, the output of the coagulation unit is connected to the output of the switch, the output of the detection unit in the required polling frequencies is connected to the corresponding inputs of the generation of admissible polling frequencies and frequency comparators, the output of one KOTOEWX short-circuit is connected to the input of the program control block and one input of the block for generating permissive polling frequencies, the other input of which is connected to the output of another -frequency comparator, and The output to another input of the program control unit 2. However, the known switches with boliyum kommutiruekyh channels including a complex and cumbersome, or ix provide opportunities operational mode change switch operation. The closest in technical essence to the present invention is a multi-channel switch containing a vf / l code generator, the output of which is connected to one input of the memory unit, another input of which is connected to the first output of the control unit, and the third output of the control unit is connected respectively to the generator of the stroke generator and the first input of the decoder, the input of which is connected to the output of the memory unit, and the output to the output of the switch 31. From the consideration of the block diagram and the process of functioning of the known multi-channel switch ra that the distribution of cheykgil memory block of channel numbers and discipline referring to them are organized in a tree structure. Such a structure requires the presence in the memory block of cells containing base addresses to form true addresses. The true address is used to access the memory location containing the channel number. The selection of base addresses from the cells is carried out at relative addresses supplied to the memory unit from the generator-codes. The code generator is a series of consecutive scaling schemes with a key mask that form a parallel binary code, the value of which is increased by one with each clock of the generator. The switching frequency of the channels F is defined as where r is the rank number of the tree structure (O "r" k); FQ is the switching frequency of the zero-rank channels (), i.e. upper channel switching frequency. The amount of memory V required for switching channels is determined by the number of cells for storing channel numbers n and the number of cells for storing base addresses m lf- -I g V w- "I and where n is the number of kvolutiruyushhie channels of rank g. In this case, the minimum memory capacity is Y, 4, and takes place for such a structure of the commutator, in which all channels correspond to the rank, i.e. commutates with the upper frequency f In this case, ω 0 and Y). the maximum amount of memory V Q - has a place in the case when all kangish correspond to the rank r «1. i. they are connected from the lower frequency f. At the same time, u-lti Obviously, to organize any possible tree-like switching structures for a given l and k, the device’s memory size must be. Less than that, the memory structure requires, when generating a true address (for a single channel), multiple access to cells containing base addresses. The number of such hits when sampling a single rank channel is r + 1. Accordingly, the channel sampling time is equal to t (r + l) tn, where the memory access time. The time t is minimal for a zero-rank channel (), since there is only one access for its selection (there are no base addresses for rank channels) t The time t is maximum for a rank channel (), and you need to make k memory accesses for reading basic information addresses needed to form the true channel address, and one call to the generated true address for the channel number () 1: and thus t, .tt ". A disadvantage of the known multi-channel switch is the limited speed due to multiple access to the memory cells when sampling channels of grades O. The purpose of the invention is to increase the speed of the switch. The goal is achieved by the fact that a multichannel switchboard containing a code generator and a memory block whose output is connected to the input of the decoder has been entered a block of registers of zone initial addresses, a block of registers of cycle constants and a true address generator, a code generator output, the output of the regd1rov block of initial addresses the zones and the output of the cycle constant register block are connected respectively to the first, second and third inputs of the true address generator, the output of which is connected to the memory block input. FIG. 1 shows a block diagram of a multi-channel switch; in fig. 2 shows an example of reading memory cells for four consecutive cycles of KONBwyTaTopa with r 2; in fig. 3 - timing diagram of the switch operation, where T c is the time of one cycle, T is the time of the frame during which all memory cells are accessed at least once; in fig. 4 - zone of memory block structure. Multichannel switch (figure 1) consists of a generator of 1 codes, block 2 registers of cycle constants, which contains registers 3c, block 4 registers of initial addresses of zones, which contains registers .5d-5c, the former b of the true address, which contains elements And 7p- 7c, triggers 8o 8 to keys Er-9c, counters 100-10, elements AND HQ-11c, element OR 12, block 13 of memory, decoder 14. Block 13 of memory is divided into adjacent zones (zone O, zone 1 and t . e.) (FIG. 4), the number of which is equal to the number of grades r of the tree structure of the known switch. The number of cells in each zone is Pr. Each memory cell stores only the channel number. There are no base addresses in the memory cells. The sampling rate of an individual cell (channel switching frequency F ,,) is determined by the same expression as for a known colviator, i.e. Fh- - The rules for reading zone cells are listed in the table. All cells The first half of the cell A quarter of the cells 1 / g part of the cells All the cells The second half of the cell The quarter of the cells 1 / g part of the cells All the cells The first half of the cell The third quarter of the cell / t of the cells and so on. more often than to the zone 1 and 4 times more often than to whose zone 2, ie the frequency of access to the cells of zones O, 1, 2 relate to each other, respectively, 4: 2: 1 (Fig. 2 and 3). A change in the frequency of a channel's mutation is achieved by moving its number to another zone. For organizing the zone reading of cells from the memory block, it is necessary to set the initial addresses of the AH zones and the cycle constants BP, which determine the moments of the current address from zone to zone (Br – I). True, the address of the cell with the channel number is formed from the starting address of the zone and the relative magnitude of the code generation. Such a switchboard organization both makes only one call to the memory for sampling any channel. The sampling time of the channel is constant and equal to t - tttin. Meanwhile, the maximum speed of the switch is reached. The switch works as follows. Before the switch starts operation, cycle constants Вр (г 0-k) are recorded in registers 3, block 2 of cycle constant registers, and initial registers of zones A are recorded in registers BO-5, block 4 of registers of initial zones of addresses. Initial addresses of loop and cycle constants B g are stored on registers for the duration of the switch. Before starting the work of An, they are also recorded on the corresponding meters Yud-10ts of the former B instinctive address. The 1-code generator, which is a series of scaling schemes with a key mask, is adjusted to the corresponding cyclic mode of operation with a given cycle time TC (at the end of the cycle, the scaling schemes are nullified). After switching the switch into operation from the generator generator 1, the pair code the value of which increases by one with each clock cycle of the switch, together with the accompanying clocking pulse, is fed to the input of the true address shaper 6. A parallel code in the form of a true address b is simultaneously received at the first inputs of the AND TO - 7 elements, the second inputs of which receive the code of the corresponding constant Bf from the registers 3c of the block 2 registers of cycle constants. With the equality of the code values at the output of the corresponding element 0 k, a single pulse appears, which advances the corresponding trigger SQ-8 and sets it to the closed state. At the same time, at the output of the corresponding trigger BQ-8, a control signal appears that turns off the corresponding key 9c-ec and sets the next (in an increasing sequence of indices) the trigger to the open state. All triggers for mutual control are collected in a ring. BQ-8ts open triggers: enable the corresponding keys 9c-9, thus allowing the passage of clock pulses from the code generator 1 to the output of the keys 9 (, -9ts. At the initial moment, only the trigger VdI is opened. The clock pulses go to the key 9 output. they are determined by the value of the constant BO o key 9 o is turned off by trigger 8 (3 at the moment of equality of the current code value received from the code generator 1 and the cycle constant BQ on the AND 7 ° element. At the next moment the trigger DB through the trigger 8-f turns on the key 9 Clocking pulses are received t Now the output of the key 9:,. The number of px is determined by the difference in the values of B0, since the switch off of the key E by the trigger 8 occurs at the time of the comparison of the current

generator code 1 code with a constant B on the element And 7, and the value B is determined by the quality Bpi-4. Thus, during the cycle TC), the keys S are turned on / off sequentially (Q-9k according to the rule specified by the BQ-B cycle constants. At the outputs of the keys 90-9, B1fatyvac ms pulses, the number of which in each is equal to the number of cells read from the corresponding zone of the memory block 13 during one cycle, i.e. -.

Packs of consecutive pulses from the outputs of the keys 9c are fed to the inputs of the corresponding heading of the loggers lOg10ц. When receiving pulses, each of the 100-U counters generates consecutive true addresses of the memory cells within its zone, which (cell addresses) are transmitted to the memory block 13 through the wired element OR 12. At each moment of time only one of the counters 10v- 10k. Each element AND HQ-11c compares the current state of its corresponding lOg-10ts counter with the starting address of the next AH zone. When comparing the codes on the corresponding meter U, its initial address AH | is restored. those. the one that was fixed on it by the operation of the kc of the tutor; the restoration of the counter U ,, is made in each cycle, the counter in each second cycle, the counter iO} in every fourth cycle, etc. Consequently, the values of the counter codes 10-Yun are sequentially changed from the value of AH | .to the value of Ay 11

The addresses of the channels coming from the decoder of the true addresses to the memory block 13 read the numbers of the channels that go to the decoder 14, and to the sensors of the object. Thus, the performance of the proposed switch is improved. An additional advantage of the on-demand multi-channel switch as compared with the known switch is the reduction of the memory size V for the given n and k to V "|" n, since there are no base addresses in the memory cells and m O.

Ease of calculating the values of AN |. H. p

and b |. The i- and simplicity of changes in the switching frequency of a channel by moving its number from ZO1Sh to a zone allows nporpciMN & ampi ai switching more quickly during the switch operation, adapting it to the operation modes of a multi-parameter object.

Claims (3)

1. Copyright certificate SS.SRB 390550, cl. G 08 C 19/16, 1969. 2. Authors certificate of the USSR 433525, cl. G 08 C 19/16, 1972. 3. Author's certificate tCCP 299864, cl. G 08 C 19/16, 1969 (Prototype). cycle g CyclP Well cycle "G lt ; P. LN 2 l4 a 53 fpUi.Z But not Hf AHg r Lnk