GB2059157A - Resin encapsulated field-effect transistor - Google Patents
Resin encapsulated field-effect transistor Download PDFInfo
- Publication number
- GB2059157A GB2059157A GB8029170A GB8029170A GB2059157A GB 2059157 A GB2059157 A GB 2059157A GB 8029170 A GB8029170 A GB 8029170A GB 8029170 A GB8029170 A GB 8029170A GB 2059157 A GB2059157 A GB 2059157A
- Authority
- GB
- United Kingdom
- Prior art keywords
- conductor plate
- leads
- resin
- lead
- effect transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
A resin encapsulated semiconductor device comprises a field effect transistor element 1 having source, drain and gate electrodes, leads S, G2 connected to the electrodes of the element 1 and a resin encapsulated body 2. One of the leads, e.g. the lead S connected to the source electrode of the element 1, is either connected to a conductor plate 3 on which the element 1 is mounted, or is integral therewith. The lower surface of the conductor plate 3 is exposed outside the resin body so that the conductor plate is easily grounded to provide excellent stability and maximum gain reduction at high frequency operation. <IMAGE>
Description
SPECIFICATION
Resin encapsulated semiconductor device
This invention relates to a resin-encapsulated type semiconductor device and specifically to a resin encapsulated field effect transistor.
When a field effect transistor for high frequency use, such as an insulated gate type field effect transistor (hereinafter called a "MOSFET"), is employed in a high frequency circuit, it is necessary to ground the source electrode for a.c. signals via a capacitor or the like. If this grounding is not complete, operation in the high frequency circuit becomes unstable. Incomplete grounding also results in the drawback in a dual gate type MOSFET that sufficient gain reduction cannot be obtained by a gain control voltage applied to one gate electrode. When the control voltage of one gate electrode is changed to a predetermined voltage in orderto reduce the power gain, the reduction in level of the power gain with respect to a signal applied to the other gate electrode (hereinafter called "maximum gain reduction") is deficient.
Referring now to Figures 1A and 1 B of the accompanying drawings, which for explanatory purposes show a MOSFET of a flat package type, it can be seen that a MOSFET element 1 is fitted to one lead S of the leads S, D, G1, G2, which extend horizontally thereby forming a source terminal. The electrodes of the element and the leads are wirebonded together and the element as a whole is encapsulated in a moulded resin body 2. Grounding of the case is not possible unlike a metallic case.
Grounding must therefore be made solely by use of the source terminal (lead) S. It has been found, however, that the effect of lead inductance is not negligible when grounding is made in such a way.
For this reason, in comparison with a MOSFET having a metallic case, the resin-encapsulated flat package type MOSFET has inferior maximum gain reduction and stability in a high frequency band, especially in or above the UHF band.
It is therefore an object of the present invention to improve the stability of a resin-encapsulated FET.
It is a further object of the present invention to improve the maximum gain reduction of a resin encapsulated FET.
According to the invention there is provided a resin-encapsulated semiconductor device comprising a field effect transistor having source, drain and gate electrodes, a plurality of leads connected to said electrodes, a conductor plate and a resin body integrally encapsulating said field effect transistor and said leads, wherein one of said leads is electrically connected to said conductor plate, and at least a part of a surface of said conductor plate to which said one lead is not connected is exposed outside said resin body.
Preferred embodiments of the present invention will now be described with reference to the accompanying drawings in which:
Figure 1A is a plan view of the resin encapsulated flat package type MOSFET described above;
Figure 1B is a sectional view of the MOSFET of
Figure 1Ataken along line A-A' of Figure 1A;
Figure 2 is a sectional view of a first resin
encapsulated flat package type MOSFET embodying the present invention;
Figure 3 is a sectional view of a second resin
encapsulated flat package type MOSFET embodying the present invention;
Figures 4 to 11 show the fabrication steps of the MOSFETshown in Figure 2, wherein: ;Figure 4 is a sectional view of the pellet;
Figure 5 is a plan view of the lead frame;
Figure 6 is a perspective view of the substrate;
Figures 7to 10 are sectional views of the lead frame during assembly; and
Figure 11 is a perspective view of the MOSFET after assembly;
Figure 12 is a plan view of the lead frame at one stage in the process of fabricating the MOSFET shown in Figure 3;
Figure 13 is a sectional view of the lead frame at one stage in the process of fabricating the MOSFET shown in Figure 3;
Figure 14 is a plan view of the MOSFET of Figure 2 connected to the wiring substrate; and
Figure 15 is a sectional view taken along line C - C' of Figure 14.
Figure 2 is a sectional view corresponding to the B - B' direction of Figure 1A. The MOSFET element 1 is fitted with a lead S serving as a source terminal. A lead G2 serves as the second gate terminal. The lead
S is connected to a conductor plate 3 via an intermediate plate 4. An encapsulating resin body 2 integrally seals the MOSFET, leads and intermediate plate. As shown in this drawing, the bottom surface of the conductor plate 3 is exposed outside the resin body 2.
Figures 4 to 11 show the fabrication steps of the
MOSFET of Figure 2. Figure 4 is a section of the two-gate type MOSFET element. nt-type diffusion layers 6 and 7 to serve as source and drain are formed on a p-type Si substrate 5 and gates G1 and
G2 are formed on the surface of the element between the n±type diffusion layers 6 and 7 and insulated from the substrate 5 by an insulation film (SiO2) 8.
Electrodes S and D are disposed on the source and drain, respectively.
Figure 5 shows the lead frame of the flat package type to which the MOSFET element is fitted. The lead frame consists of leads corresponding to the aforementioned source S, drain D and gates G, and
G2, and of a dam 9 for stopping the flow of the resin during molding. The inner end of the lead S functioning as the source terminal also serves as an element-fitting portion 10.
Figure 6 shows the shape of the conductor plate 3.
The intermediate plate 4 is either formed integrally with the conductor plate 3 or connected to the conductor plate by spot-welding or the like.
The lead frame and conductor plate are combined with each other as shown in Figure 7 and are connected to each other via the intermediate plate 4 as shown in Figure 8. This connection is carried out by welding, brazing or caulking. As shown in Figure 9, the MOSFET element 1 is then fitted onto the lead frame and the electrodes of the element are con nected to the corresponding leads by wire-bonding.
In carrying out this wire-bonding, it is necessary to interpose a jig 11 or the like between the conductor plate 3 and the other leads G1, G2, D that are floating above the conductor plate 3.
Figure 10 shows the moulding of the resin encapsulation by packing the lead frame into upper and lower molds 12, 13. Figure 11 shows the appearance of the MOSFET after molding.
Figure 3 shows a further preferred embodiment of the present invention in which the lead S to be connected to the source of the element is integral with the conductor plate. In this case, it is advisable to employ a lead frame having the shape shown in
Figure 12. In Figure 12, the lead S to be connected to the source has a conductor plate 14 which extends fully within the dam 9 with suitable gaps between it and the other leads G1, G2, D. This conductor plate 14 and the lead S are formed integrally. A part 15 of the other leads such as G, for example, is bent upwardly as depicted in Figure 13. After the MOSFET element 1 and the leads are wire-bonded as shown in this drawing, resin encapsulation is used to give the construction shown in Figure 3, in which the lower face of the plate 14 is exposed outside the resin.
In the embodiment of Figure 3, the distance from the main body of the pellet (MOSFET element) 1 to the source lead terminal is short and the grounding effect can be increased.
In actually fitting a resin-encapsulated flat package type MOSFET in accordance with the present invention to a printed circuit board or the like, a grounding effect virtually identical to that of the device with a metallic case can be obtained by directly grounding the lower case portion (conductor plate) as shown in
Figures 14 and 15.
Figures 14 and 15 show a MOSFET element of the present invention in its connected state which is resin molded onto the printed circuit board. The leads of the source, drain and gate are shown connected electrically via solder 21 to the metal wires 22 on the printed circuit board having a metal foil such as a copper foil arranged in a predetermined wiring pattern 22 on the surface of the insulation plate 20. The conductor plate 3 is directly connected to the metal wires 22.
The stability and maximum gain reduction of a resin-encapsulated flat package type MOSFET in a high frequency circuit can thus be improved markedly.
The maximum gain reduction possible in a resinencapsulated flat package type FET of the present invention is increased by about 5 to 7dB when compared with that of the maximum gain reduction of the resin-encapsulated flat package type FET shown in Figures 1A and 1 B. Thus, it is possible to obtain good reduction of the power gain.
The present invention is not restricted to the above-described embodiments. For example, the
MOSFET may be not of the two-gate type but of the one-gate type. In the latter case, the number of leads is three. The present invention can also be applied to a junction-type FET in the same way as in the above-described embodiments. In the MOSFET shown in Figure 2, the source lead S may be connected directly to the conductor plate 4 without using the intermediate plate 4.
The present invention provides a remarkable effect in a FETto be used in a high frequency circuit in or higher than the UHF band. Especially good effects can be obtained in a FET used in the tuner of a television receiver.
Claims (9)
1. A resin-encapsulated semiconductor device comprising a field effect transistor having source, drain and gate electrodes, a plurality of leads connected to said electrodes, a conductor plate and a a resin body integrally encapsulating said field effect transistor and said leads, wherein one of said leads is electrically connected to said conductor plate, and at least a part of a surface of said conductor plate to which said one lead is not connected is exposed outside said resin body.
2. A device according to claim 1 wherein said conductor plate is integral with said lead connected to said source electrode.
3. A device according to claim 2 wherein the ends closest to said field effect transistor of said leads other than the lead integral with said c9nduc- tor plate are located spaced from the conductor plates and on the same side of the conductor plate as the transistor.
4. A device according to any one of the preceding claims wherein said lead connected to the conductor plate is the lead connected to the source electrode.
5. A device according to any one of the preceding claims wherein the transistor is mounted directly or indirectly on the conductor plate.
6. A device according to any one of the preceding claims wherein said plurality of leads connected to said source, gate and drain electrodes, protrude outwardly from said resin body.
7. A device according to any one of the preceding claims wherein said resin body has a cylindrical shape.
8. A resin encapsulated semiconductor device according to any one of the preceding claims wherein a wiring substrate having a metallic wiring pattern on the surface thereof is connected to said leads by solder.
9. A resin encapsulated semiconductor device substantially as herein described with reference to and as shown in Figures 2 and 4 to 11 or Figures 3, 12 and 13 ofthe accompanying drawings.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12063179A JPS5645054A (en) | 1979-09-21 | 1979-09-21 | Resin sealing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB2059157A true GB2059157A (en) | 1981-04-15 |
| GB2059157B GB2059157B (en) | 1984-05-23 |
Family
ID=14790997
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB8029170A Expired GB2059157B (en) | 1979-09-21 | 1980-09-09 | Resin encapsulated field-effect transistor |
| GB8315596A Pending GB8315596D0 (en) | 1979-09-21 | 1983-06-07 | Resin encapsulated semiconductor device |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB8315596A Pending GB8315596D0 (en) | 1979-09-21 | 1983-06-07 | Resin encapsulated semiconductor device |
Country Status (6)
| Country | Link |
|---|---|
| JP (1) | JPS5645054A (en) |
| DE (1) | DE3033516A1 (en) |
| GB (2) | GB2059157B (en) |
| HK (1) | HK37585A (en) |
| MY (1) | MY8500835A (en) |
| SG (1) | SG62184G (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4984063A (en) * | 1989-03-30 | 1991-01-08 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
| EP0408904A2 (en) * | 1989-07-21 | 1991-01-23 | Motorola, Inc. | Surface mounting semiconductor device and method |
| US6372539B1 (en) | 2000-03-20 | 2002-04-16 | National Semiconductor Corporation | Leadless packaging process using a conductive substrate |
| US6399415B1 (en) | 2000-03-20 | 2002-06-04 | National Semiconductor Corporation | Electrical isolation in panels of leadless IC packages |
| US6452255B1 (en) | 2000-03-20 | 2002-09-17 | National Semiconductor, Corp. | Low inductance leadless package |
| US6686652B1 (en) * | 2000-03-20 | 2004-02-03 | National Semiconductor | Locking lead tips and die attach pad for a leadless package apparatus and method |
| CN110337194A (en) * | 2019-07-25 | 2019-10-15 | 苏州华之杰电讯股份有限公司 | The connection method and connection structure of double metal-oxide-semiconductors and PCBA board in parallel |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3421539A1 (en) * | 1984-06-08 | 1985-12-19 | Siemens AG, 1000 Berlin und 8000 München | Semiconductor component for SMD technology |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5116109B2 (en) * | 1971-09-16 | 1976-05-21 |
-
1979
- 1979-09-21 JP JP12063179A patent/JPS5645054A/en active Pending
-
1980
- 1980-09-05 DE DE19803033516 patent/DE3033516A1/en not_active Withdrawn
- 1980-09-09 GB GB8029170A patent/GB2059157B/en not_active Expired
-
1983
- 1983-06-07 GB GB8315596A patent/GB8315596D0/en active Pending
-
1984
- 1984-09-01 SG SG62184A patent/SG62184G/en unknown
-
1985
- 1985-05-16 HK HK37585A patent/HK37585A/en unknown
- 1985-12-30 MY MY8500835A patent/MY8500835A/en unknown
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4984063A (en) * | 1989-03-30 | 1991-01-08 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
| EP0408904A2 (en) * | 1989-07-21 | 1991-01-23 | Motorola, Inc. | Surface mounting semiconductor device and method |
| EP0408904A3 (en) * | 1989-07-21 | 1992-01-02 | Motorola Inc. | Surface mounting semiconductor device and method |
| US6372539B1 (en) | 2000-03-20 | 2002-04-16 | National Semiconductor Corporation | Leadless packaging process using a conductive substrate |
| US6399415B1 (en) | 2000-03-20 | 2002-06-04 | National Semiconductor Corporation | Electrical isolation in panels of leadless IC packages |
| US6452255B1 (en) | 2000-03-20 | 2002-09-17 | National Semiconductor, Corp. | Low inductance leadless package |
| US6686652B1 (en) * | 2000-03-20 | 2004-02-03 | National Semiconductor | Locking lead tips and die attach pad for a leadless package apparatus and method |
| CN110337194A (en) * | 2019-07-25 | 2019-10-15 | 苏州华之杰电讯股份有限公司 | The connection method and connection structure of double metal-oxide-semiconductors and PCBA board in parallel |
| CN110337194B (en) * | 2019-07-25 | 2024-02-13 | 苏州华之杰电讯股份有限公司 | Connecting structure of parallel double MOS (Metal oxide semiconductor) tubes and PCBA (printed circuit board assembly) |
Also Published As
| Publication number | Publication date |
|---|---|
| GB8315596D0 (en) | 1983-07-13 |
| MY8500835A (en) | 1985-12-31 |
| HK37585A (en) | 1985-05-24 |
| DE3033516A1 (en) | 1981-04-09 |
| JPS5645054A (en) | 1981-04-24 |
| SG62184G (en) | 1985-03-15 |
| GB2059157B (en) | 1984-05-23 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 19940909 |