GB2038577A - P.C.M. decoder - Google Patents

Abstract

A bipolar P.C.M. decoder in which a charge of the required polarity is built up on a storage capacitor 6 by charge sharing with another capacitor 1 which in accordance with the digit values to be decoded is periodically connected to a single-polarity voltage source V. In dependence upon the value of polarity bit of the signal to be decoded the other capacitor 1 may be connected to the voltage source either when it is interconnected with the storage capacitor or when it is not interconnected with the storage capacitor. <IMAGE>

Description

SPECIFICATION Digital' to analogue converter arrangements The present invention relates to digital to analogue convertor arrangements.

According to one aspect of the present invention in a digital to analogue convertor arrangement in which charge is added to or taken from a storage capacitor to derive an analogue value from a binary coded input signal, by periodically interconnecting said storage capacitor with and disconnecting it from another capacitor, a charge of either polarity, in dependence upon the value of a polarity-indicating digit forming part of said binary coded input signal, is arranged to be built up on said storage capacitor by operation of switch means selectively connecting said other capacitor to a voltage source of a predetermined single polarity in dependence upon digit values of a binary coded input signal supplied to said convertor arrangement.

According to another aspect of the present invention in a digital to analogue convertor arrangement in which a value of charge is built up on a storage capacitor, in dependence upon digit values of binary-coded input signal, by periodically interconnecting said storage capacitor with another capacitor such that any charge on said capacitors is shared, there are provided means to connect said other capacitor to a source having a predetermined polarity selectively either when said other capacitor is interconnected with said storage capacitor or when it is not interconnected with said storage capacitor, in dependence upon the value of a polarity-determining digit forming part of said input signal, such as to build up a charge of a required polarity on said storage capacitor.

A digital to analogue convertor arrangement in accordance with the present invention will now be described with reference to the accompanying drawings, of which: Figures 1 to 4 show respective forms of convertor arrangement diagrammatically.

Referring first to Fig. 1 the digital to analogue convertor arrangement or decoder comprises a first capacitor 1 and switches 2 to 5 by means of which the capacitor 1 may be held discharged or may be charged in either sense from a single-polarity voltage reference source designated V. Thus by closing the switches 3 and 4 the capacitor 1 may be charged in one sense whereas by closing the switches 2 and 5 the capacitor 1 may be charged in the opposite sense. The arrangement also comprises a capacitor 6, of substantially the same value as the capacitor 1, and a switch 7 by means of which any charge on the capacitors 1 and 6 individually may be shared between the two.

The switches 2 to 5 and 7 are arranged to operate in dependence upon the digit values of a binary coded signal, these digit values being held during a decoding cycle in a storage register (not shown). A decoding cycle is timed by clockpulses at a repitition rate of, say, 128 KHz.

The arrangement may be used for decoding a compression-law binary coded signal com prising, say, a polarity digit, three digits indi cating in which of eight contiguous voltage ranges or segments of progressively greater width the original signal fell and four "linear code" digits indicating in which of sixteen equal intervals covering its respective segment the original signal fell. In decoding such a signal the sense in which the capacitor 1 is charged is determined by the value of the polarity digit, and in a first clock pulse period the capacitor 1 is charged to the reference voltage or held discharged in dependence upon the value of the least significant of the four 'linear' digits.During a second clock pulse period the capacitor 1 is disconnected from its charging source, if required, and connected by way of the switch 7 in parallel witch the capacitor 6, whereupon any charge on the capacitor 1 is shared between the two capacitors, and the voltage, if any, falls to half that of the reference source.

During a third clockpulse period the capaci tor 1 is disconnected from the capacitor 6 and is charged to the reference voltage or held discharged in dependence upon the value of the second least significant of the four linear digits. During a fourth clockpulse period the capacitor 1 is again disconnected from its charging source, if required, and is connected by way of the switch 7 in parallel with the capacitor 6. Any charges on the individual capacitors 1 and 6 are then shared, so that the capacitor 6 may be considered to hold half the charge that it received during the second clockpulse period together with the charge received during the fourth period, this latter quantity being half of that received by the the capacitor 1 during the third clockpulse period.

The alternate charging, as required, and charge-sharing proceeds for a further four clockpulse periods, in respect of the third and fourth of the linear digits, and during each of the two further charge-sharing periods the residual charge on the capacitor 6 is effec tively halved, and a further quantity of charge may be added in dependence upon the re respective linear digit value. The charge contrib utions to the total charge on the capacitor 6 at the end of the eighth clockpulse period in respect of the four linear digits are thus re lated by successive factors of two from the least to the most signficant.

The capacitor 1 is subsequently alternately discharged and connected in parallel with the capacitor 6, each time effectively removing half of the charge remaining on the capacitor 6 6 and thus dividing the voltage across it by two, a number of times determined by the value of the three segment code digits. Thus for signals from the highest segment, referred to as segment seven, which covers the upper half of the analogue voltage range the voltage on the capacitor 6 is not divided further, for signals from segment six, covering the next highest quarter of the analogue voltage range the voltage on capacitor 6 is divided once, and so on until for signals from the lowest analogue voltage range, segment zero, the voltage on capacitor 6 is divided seven times to obtain the final value.

When the division process in accordance with the segment code has terminated the final voltage value on the capacitor 6 is transferred by way of switches 8 and 9 and a buffer amplifier 10 to a "hold" capacitor 11, from which a continuous output voltage at that value is derived by an amplifier 1 2. The capacitors 1 and 6 are then released to decode the next coded value.

In a modification of the circuit shown in Fig. 1 the switch 3 and the second connection to the voltage source V are omitted. Decoding in respect of signals of one polarity, negative with respect to the source V, then proceed as above, with the capacitor 1 being charged effectively to minus V, as required by the respective linear digit value, by closure of switches 2 and 5 during the odd-number clockpulse periods referred to above. For signals of the opposite polarity, however, in respect of digit values where charge is to be added by way of the capacitor 1 the switch 5 is arranged to be closed during the respective even-number clockpulse periods,.when the charge-sharing also takes place.The reference voltage V is then applied across the two capacitors in series, whereupon the capacitor 6 is left with effectively an equal share of the added charge of the same value as described above but of the same polarity as the source V. The odd number clockpulse periods referred to above would in the modified arrangement be used to discharge the capacitor 1.

Referring now to Fig. 2 the capacitor 1 and the switches 2, 4, 5 and 7 may be duplicated, as shown, and used alternately, in respect of alternate digit values, to reduce the number of clockpulse periods taken up by the decoding cycle. Thus while one of the capacitors 1 is interconnected with the capacitor 6 for charge sharing to take place the other of the capacitors 1 may be connected for charging or discharging as required.

While the arrangement shown in Fig. 2, using a cycle of sixteen clockpulses at 1 28KHz, can decode compression-law coded values of the form referred to above at the standard sampling rate of 8KHz, the arrangement of Fig. 1 would generally require a higher frequency clock signal, say at 256 KHz, to complete decoding within the sampling interval of 1 25 micro seconds.

The use of a single voltage source for both signal polarities obviates the requirement for precisely matched voltage sources, while the capacitive division decoding process requires the capacitors to be matched to the order of one per cent to achieve acceptable results.

Referring now to Fig. 3 the buffer amplifier 10 and the switch 9 may be omitted, although a switch 1 3 may be required in parallel with the capacitor 11 to discharge that capacitor at the end of a decoding cycle.

As shown in Fig. 4 the amplifier 10, the switch 9 and the capacitor 11 may be omitted in an arrangement in which the capacitor 6 and the switches 7 and 8 are duplicated. The capacitors 6 are each used alternately as storage capacitor for decoding and hold capacitor for read-out of the decoded signal, these capacitors being discharged at the commencement of their respective decoding cycles by way of the switch 2.

Claims (5)

1. A digital to analogue convertor arrangement in which charge is added to or taken from a storage capacitor to derive an analogue value from a binary coded input signal, by periodically interconnecting said storage capacitor with and disconnecting it from another capacitor, wherein a charge of either polarity, in dependence upon the vale of a polarityindicating digit forming part of said binary coded input signal, is arranged to be built up on said storage capacitor by operation of switch means selectively connecting said other capacitor to a voltage source of a predetermined single polarity in dependence upon digit values of a binary coded input signal supplied to said convertor arrangement.

2. A digital to analogue convertor arrangement in which a value of charge is built up on a storage capacitor, in dependence upon digit values of a binary-coded input signal, by periodically interconnecting said storage capacitor with another capacitor such that any charge on said capacitors is shared, wherein there are provided means to connect said other capacitor to a source having a predetermined polarity selectively either when said other capacitor is interconnected with said storage capacitor or when it is not interconnected with said storage capacitor, in dependence upon the value of a polarity-determining digit forming part of said input signal, such as to build up a charge of a required polarity on said storage capacitor.

3. A digital to analogue converter arrangement in accordance with Claim 2 wherein there are provided two of said other capacitors arranged to be interconnected with said storage capacitor alternately.

4. A digital to analogue convertor arrangement in accordance with Claim 2 or Claim 3 wherein there are provided two storage capac itors arranged to be used alternately for decoding and as a hold capacitor for read-out of a decoded signal.

5. A digital to analogue convertor arrangement substantially as hereinbefore described with reference to any one of Figs. 1 to 4 of the accompanying drawings.