GB1565943A - Sequence control system having functions of automatic prevention and maintenance - Google Patents
Sequence control system having functions of automatic prevention and maintenance Download PDFInfo
- Publication number
- GB1565943A GB1565943A GB374778A GB374778A GB1565943A GB 1565943 A GB1565943 A GB 1565943A GB 374778 A GB374778 A GB 374778A GB 374778 A GB374778 A GB 374778A GB 1565943 A GB1565943 A GB 1565943A
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- Prior art keywords
- signal line
- information
- local
- sequencer
- pulse
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q9/00—Arrangements in telecontrol or telemetry systems for selectively calling a substation from a main station, in which substation desired apparatus is selected for applying a control signal thereto or for obtaining measured values therefrom
- H04Q9/14—Calling by using pulses
- H04Q9/16—Calling by using pulses by predetermined number of pulses
-
- G—PHYSICS
- G08—SIGNALLING
- G08C—TRANSMISSION SYSTEMS FOR MEASURED VALUES, CONTROL OR SIMILAR SIGNALS
- G08C15/00—Arrangements characterised by the use of multiplexing for the transmission of a plurality of signals over a common path
- G08C15/06—Arrangements characterised by the use of multiplexing for the transmission of a plurality of signals over a common path successively, i.e. using time division
- G08C15/12—Arrangements characterised by the use of multiplexing for the transmission of a plurality of signals over a common path successively, i.e. using time division the signals being represented by pulse characteristics in transmission link
Description
(54) SEQUENCE CONTROL SYSTEM HAVING FUNCTIONS
OF AUTOMATIC PREVENTION AND MAINTENANCE
(71) We, OSAKI ELECTRIC
COMPANY LIMITED, a Japanese
Company of 2-7 Higashigotanda, 2chome, Shinagawaku, Tokyo, Japan, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement:- The present invention relates to a sequence control system having functions of automatic prevention and maintenance, such a system being suitable for use in automatic meter reading of consumed quantities of electricity, gas, and water and so on; or in central monitoring control disaster prevention or another type of sequence control.
In conventional sequence control systems, the main unit of sequencer has based on the stored program logical operation to allow very small size of the main unit. As shown in Figure 1, however, the number of information input lines 1 connected with each sensor of SUNS" SNS2,
SNS3, . . . SNS,~,, SUNS, and control output lines 2 connected with each process equipment of POST, PCS2, PCS3,... PCSn~" PCSn has become extremely large since the sensors for detecting condition of controlled processes and the process equipments controlled by the sequencer have been distributed among many spots.In the case of that, for example, the number of sensors is 1000 and that of process equipments is 300, total number of 2600 of the input and output lines are required. Furthermore, the input interface unit and output interface unit 5 for connecting the input/output lines and the main unit 3 of sequencer have needed one unit for each network to have as much as 1300 interfaces, requiring large scale of the system. Therefore, in rather large sequence control system, the quantity of wire, the cost of interfaces and the amount of work of wiring and connection have become considerably large. If there occurs misconnection, a huge amount of work for searching correcting is unavoidable.Various sequence control systems having relatively small number of input/output lines and interfaces have been proposed in order to eliminate this weak point but the problems have still remained in the viewpoint of early finding of troubles of local unit having charge of controlling sensors or process equipments and troubles of disconnection and short circuit of input/output lines.
According to one aspect of the present invention there is provided a sequence control system having a sequencer and a plurality of local units each serving as a sensor; the sequencer and all the local units being connected by four lines including a synchronizing signal line, a selection signal line, an information signal line and a common line; and wherein: a reset pulse is transmitted to all the local units from the sequencer through the synchronizing signal line to reset all the local units to an initial state in a normal cycle for information collection; a selection signal pulse train consisting of a series of pulses whose number is the same as the number of local units is transmitted from the sequencer through the selection signal line; pulses of the selection signal pulse train are simultaneously counted in each local unit: a pulse is sent back or not to the sequencer from the local unit through the information signal line, depending upon the state of on or off of the local unit, within one bit time of the pulse as hereinafter defined, when the pulse of the same number as the address number of each local unit has been counted; at the time of switching to an information test cycle an information test cycle command signal consisting of a number of pulses is transmitted to all the local units from the sequencer through the selection signal line to simultaneously set all the local units to an information test state following the selection signal pulse train; information concerning whether or not the function of sending back information at each local unit is effective is sequentially sent back to the sequencer from each local unit through the information signal line, in synchronism with the selection signal pulse train in the information test cycle: and a reset command signal for resetting consisting of pulses is transmitted to all the local units from the sequencer following the selection signal pulse train through the selection signal line to reset all the local units simultaneously to the information test state.
According to another aspect of the present invention there is provided a sequence control system having a sequencer and a plurality of local units each serving as a sensor and as a control for process equipment; the sequencer and all the local units being connected with six lines including a synchronizing signal line, a selection signal line, an information signal line an on-control signal line, an off-control signal line and a common line; and wherein: a reset pulse is transmitted to all the local units from the sequencer through the synchronizing signal line to reset all the local units to initial state in a normal cycle for information collection and process equipment control; a selection signal pulse train consisting of a series of pulses whose number is the same as the number of local units, is transmitted from the sequencer through the selection signal line; pulses of the selection signal pulse train are simultaneously counted in each local unit; a pulse is sent back or not to the sequencer from the local unit through the information signal line depending upon the state of on or off of the local unit within one bit time of the pulse as hereinafter defined when the pulse of the same number as the address number of each local unit has been counted; at the same time an on-control signal or an off-control signal, is transmitted to the local unit from the sequencer within one bit time which is assigned for each local unit through the on-control signal line or the off-control signal line to control process equipment on or off; at the time of switching to an information test cycle an information test cycle command signal consisting of a number of pulses is transmitted to all the local units from the sequencer through the selection signal line to simultaneously set all the local unit to an information test state following the selection signal pulse train; information concerning whether the function of sending back information at each local unit is effective or not is sequentially sent back to the sequencer from each local unit through the information signal line in synchronism with the selection signal pulse trian at the information test cycle: at the time of switching to a control test cycle a control test cycle command signal consisting of a number of pulses is transmitted to all the local units from the sequencer through the selection signal line simultaneously to set all the local units to control test state following the selection signal pulse train; information concerning whether the function of controlling at each local unit is effective or not is sequentially sent back to the sequencer from each local unit through the information signal line in synchronism with the selection signal pulse train in the control test cycle; and art the time of returning to the normal cycle, a reset command signal for resetting consisting of pulses is transmitted to all the local units from the sequencer following the selection signal pulse train through the selection signal line simultaneously to reset all the local units to the test state.
The term "one bit time" is defined herein as the time from the leading edge of a pulse of the selection signal train to the leading edge of the next pulse in the train.
It will be appreciated therefore that the number of input/output lines connecting the sequencer with local units can be reduced as few as four lines due to time sharing method for selection of local unit and sending back information from the local unit, and consequently the number of interfaces can be considerably reduced. Furthermore, the function of information send back for all the local units is tested so as to find troubles at early stage by switching to information test cycle regularly.
In one embodiment according to the present invention, ON-OFF control of process equipment is attained by transmitting an on-control signal or an offcontrol signal through an on-control signal line or an off-control signal line simultaneously with information collection.
Moreover, it can test the control functions of all the local units.
In a further embodiment of this invention, one pulse from a sensor is recognized and counted up exactly as one pulse because a trailing edge of the pulse can be detected.
Reference is now made to the accompanying draiwngs, in which: Figure 1 is a block diagram showing a conventional sequence control system;
Figure 2 is a block diagram showing an embodiment of the sequence control system according to the present invention:
Figure 3 is a wiring diagram showing a local unit of the system of Figure 2;
Figure 4 is a time chart showing signal transmitted through each signal line;
Figure 5 is a chart relating to operations of normal cycle and test cycle;
Figure 6 is a view showing sampling operation of a pulse sent from a sensor;
Figure 7 is a flow chart showing normal cycle operation of sequencer; and
Figures 8a and 8b are flow charts of test cycle operation of sequencer.
With reference to Figures 2 through 8, an embodiment of this invention will be illustrated. This embodiment has functions of both information collection and process equipment control. Figure 2 shows a blockdiagram of the entire system. A sequencer 6 comprises a main unit 7, an operation console unit 8, a display unit 9 and input and output interface unit 10. The main unit 7 comprises a control unit 11, operation unit 12 and memory unit 13. An input and output interface unit 10 is connected with the local units L1, L2, L3, . . . On~1, Ln through six signal lines 14, that are a synchronizing signal line SYN, a selection signal line SEL, and an information signal line INF, an on-control signal line
ON, an off-control signal line OFF and a common line COM.Each local unit of L,- Ln has charge of a pair of sensor and process equipment. The wiring diagram of local unit
L1 is shown in Figure 3. All of the other units also have the same circuits. Address numbers are assigned of the local units L1 Ln. The address number for the local unit L1 is 1 and for Ln is n. For the convenience of explanation, the number of local units will be assumed as 195 hereinafter.
(I) Normal cycle
Firstly, the normal cycle operation for information collection and process equipment control will be explained. When a reset pulse (address number 0) (Figure 4) is transmitted to all the local units from the sequencer 6 through the synchronizing signal line SYN, a counter CTR and flip-flop circuits FF1, FF2, FF3 are reset by this reset pulse (address number 0) at all the local units. Then, a selection signal pulse train (Figure 4) consisting of a series of pulses whose number is the same as the number of local units, that is 195, is transmitted to all the local units through the selection signal lines SEL. The counters CTR in all the local units count the pulses of selection signal pulse train simultaneously.In the local unit L1 whose address number is 1, a decoder
DCD is set so as to produce an output when the counter CTR counts the number of pulse "1" so that the decoder DCD transmits the output signal to a monitoring count up gate A, knowing that the unit itself has been selected by counting a single pulse from the selection signal pulse train.
The monitoring count up gate A opens by the application of another input to the monitoring count up gate A from reset output terminals of the flip-flop circuit FF1-FF3 have been already reset. If the sensor SNS1 is in the on-state at this time, pulse a (Figure 4) is sent back to the sequencer 6 through the information signal line INF. The pulse is not sent back when the sensor SNS1 is in the off-state. The pulse a is sent back within one bit time BT of the pulse (address number 1) of the selection signal pulse train. The sensor SNS1 is a auxiliary contact of a control relay SL.
The output signal of the decoder DCD and the reset output of the flip-flop circuit
FF1 are sent to on-control gates N and C and off-control gates N and C to make them semi-excited state. If an on-control signal x comes from the sequencer 6 through the on-control signal line ON within the assigned one bit time for the unit (An example, wherein the signal x is transmitted to the address of number 2, is shown in
Figure 4), the on-control gates N and C open to set the flip-flop circuit FF4 and the output therefrom excites the control relay
SL through an amplifier circuit AMP to close a main contact M resulting in controlling the process equipment. This onstate causes the pulse b to be sent to the sequencer 6 through the information signal line INF.If the off-control signal y comes from the sequencer 6 through the offcontrol signal line OFF (An example wherein the signal y is sent to the address of number 4 is shown in Figure 4), the offcontrol gates N and C open to reset the flip-flop circuit FF4 resulting in losing excitation from the control relay SL to open the main contact M to make off-control of the process equipment. This off-state causes pulse c to be sent to the sequencer 6 through the information signal line INF and it is treated as an off-information because of short pulse duration. First cycle completes when scanning until the local unit L19 has been achieved, and then second cycle initiated by reset pulse (address number 0) starts and thus normal cycle is repeated hereafter.
A flow chart of normal cycle of the main unit 7 of sequencer is shown in Figure 7.
After completion of sending selection signal pulse train consisting of 195 pulses, information is collected by the program for information collection and then operation based on the information is executed by the program for logical operation, and the oncontrol signal or off-control signal is set to be sent for a local unit according to the results of operation by the program for control output. The other programs are suitably selected and executed.
Referring now to Figure 6, counting up process of the pulses which are sent from sensors SNS1-SNS195 will be explained. In the case of that on-state of the sensors SUNS, for example, is being kept during time t1, one information is sampled every time t2 since 1 cycle time of normal cycle is t2, so that the sampled values at each point of c through g are all 1. In present invention, completion of one pulse from the sensor
SNS1 to be counted up may be recognized by detecting the trailing edge of the pulse.
In other words, changing of sampled values 1 0 of the pulse from the sensor SNS1 between sampling points g and h is detected to be recognized as one count up pulse. The method of operation will be described hereinafter. Let the sampling value of the preceding normal cycle be a and that of the present normal cycle be p,
where, symbol; and . represent logical exclusive OR operation and logical product respectively.
Counting up is executed at S=l.
An example of the operation is shown as follows.
(2) Test cycle
Test cycle is regularly inserted by interrupting normal cycle (every several minutes-several hours).
Address number which is exceeding the last number of the local unit is assigned as the switching command for test cycle If the last address number of the local unit is 195, the number of larger than 196 is used for the switching command. In the illustrated embodiment, one pulse of address number 196, two pulses of address number 196 and 197, three pulses of address numbers 196 through 198, and four pulses of address numbers 196 through 199 are used for the switching command for control test cycle, on-information test cycle, off-information test cycle and command for resetting normal cycle, respectively.
(2a) On-control test cycle
A command signal for switching control test cycle consisting of the pulse of address number 196 which follows the selection signal pulse train of normal cycle (0 through 195), is transmitted to all the local units L1 through L195 from the sequencer 6 through the selection signal line SEL as shown in
Figure 5. The pulse of address 196 is counted by the counter CTR in the local unit, and an output is set as the set input for the flip-flop circuit FF1 from the output terminal 196 of the decoder DCD, then the control operation monitoring gates NI and are subjected in semi-excited state by the set pulse from the circuit FF1 resulting in setting the unit to be control test state.
This is conducted in all the local units at the same time. The on-control gate C and off control gate C are closed at this time, making no change of the control relay SL during the test cycle. Then the reset pulse (address 0) is sent through the synchronized signal line SYN to reset the counters CTR of all the local units. The reset pulse enters to
AND gate T at this time but output from the
AND gate T is not produced because of absence of input from the reset output terminal of the flip-flop circuit FF1, so that the flip-flop circuit FF1 is not reset, being kept in set-state. Subsequently, the selection signal pulse train (addresses 1 through 195) is sent through the selection signal line SEL, and on-control signal is simultaneously sent to all the addresses (addresses 1 through 195) through the on-control signal line ON.
The on-control signal opens the on-control gate N in the local unit, and the control operation monitoring gate NI is opened thereby. Therefore, pulses must be sent back at all addresses, synchronism with the selection signal pulse train from all the local units through the information signal line
INF. If there is no pulse at a certain address, the local unit corresponding to this address is judged to be in trouble of on-control function.
(2b) Off-control test cycle
This test cycle is again commenced with transmitting reset pulse (address 0) through the synchronizing signal line SYN after the completion of on-control test cycle.
Subsequently, the selection signal pulse train (addresses I through 195) is transmitted through the selection signal line
SEL, and off-control signal is simultaneously transmitted to all addresses through the off-control line OFF.
Accordingly, the off-control gate N and the control operation monitoring gate Ni are opened, so that the pulses must be sent back to all addresses from all local units, synchronizing with the selection signal pulse train through the information signal line
INF. If there is no pulse sent back from a certain address, the local unit corresponding to this address is judged to be in trouble of off-control function.
(2c) On-information test cycle
Following the completion of off-control test cycle, the command signal for switching on-information test cycle consisting of two pulses of the address of 196 and 197 is transmitted through the selection signal line
SEL as shown in Figure 5. In the local unit an output signal appears from an output terminal 197 of a decoder DCD to reset the flip-flop circuit FF and set the flip-flop circuit FF2 to be set in on-information test state. This is conducted in all the local units at the same time. At this time, the reset output from the flip-flop circuit FF2 becomes zero to close the monitor count up gate A resulting in that the information relating to the state of the sensor SNS1 is not sent back in any manner.And then the reset pulse (address 0) is transmitted through the synchronizing signal line SYN to reset counters CTR of all the local units, followed by transmission of the selection signal pulse train (addresses 1 through 195) through the selection signal line SEL. When the pulse assigned for the address of local unit itself is received at each local unit, the output signal from the decoder DCD opens the information operation monitoring gate MO to send back a pulse to the sequencer 6 within 1 bit time of its own address through the information signal line SEL.
(2d) Off-information test cycle
Following the end of on-information test cycle, the command signal for switching offinformation test cycle consisting of three pulses of addresses 196 through 198 is transmitted through the selection signal line
SEL. In the local unit, as the result of counting the 198th pulse by the counter
CTR an output signal from the output terminal 198 of the decoder DCD makes the flip-flop circuit FF2 reset and makes the flip-flop circuit FF3 set. This is conducted simultaneously in all the local units.
Subsequently, the reset pulse (address 0)
and the selection signal pulse train (addresses 1--195) are transmitted through the selection signal line SEL, but no
response is obtained from the local units. If
a pulse is sent back, either of the short
circuit trouble in the information signal line
INF and the half closing trouble in the
monitor count up gate A is recognized.
(2e) Resetting to normal cycle from test
cycle
Every flip-flop circuit FF3 in all the local
units is reset by transmission of the reset
command signal consisting of four pulses of
addresses 196 through 199 after the
completion of off-information test cycle through the selection signal line SEL.
Subsequent transmission of reset pulses (address 0) gives back all the local units in
initial state to return to the normal cycle.
A flow chart of the operation in the main
unit 7 of sequencer at test cycle is shown in
Figures 8a and 8b.
In the case of automatic meter reading,
the control of process equipment is not
necessary but only information collection is
required, so that transmissions of on-control
signal and off-control signal are not carried
out, therefore, the on-control signal line ON
and the off-control signal line OFF can be
neglected. Furthermore, the right side of
the on-control gate N and off-control gate m of the local unit in Figure 3 becomes
unnecessary.
The test cycle is carried out regularly by the internal program, but it is also possible to be switched by external signal at suitable time.
WHAT WE CLAIM IS:
1 A sequence control system having a sequencer and a plurality of local units each serving as a sensor; the sequencer and all the local units being connected by four lines including a synchronizing signal line, a selection signal line, an information signal line and a common line; and wherein: a reset pulse is transmitted to all the local units from the sequencer through the synchronizing signal line to reset all the local units to an initial state in a normal cycle for information collection; a selection signal pulse train consisting of a series of pulses whose number is the same as the number of local units is transmitted from the sequencer through the selection signal line; pulses of the selection signal pulse train are simultaneously counted in each local unit; a pulse is sent back or not to the sequencer from the local unit through the information signal line, depending upon the state of on or off of the local unit, within one bit time of the pulse as hereinbefore defined, when the pulse of the same number as the address number of each local unit has been counted; at the time of switching to an information test cycle an information test cycle command signal consisting of a number of pulses is transmitted to all the local units from the sequencer through the selection signal line to simultaneously set all the local units to an information test state following the selection signal pulse train; information concerning whether or not the function of sending back information at each local unit is effective is sequentially sent back to the sequencer from each local unit through the information signal line, in synchronism with the selection signal pulse train in the information test cycle; and a reset command signal for resetting consisting of pulses ;s transmitted to all the local units from the sequencer following the selection signal pulse train through the selection signal line to reset all the local units simultaneously to the information test state.
2. A sequence control system having a sequencer and a plurality of local units each serving as a sensor and as a control for process equipment; the sequencer and all the local units being connected with six lines including a synchronizing signal line, a selection signal line, an information signal line, an on-control signal line, an off-control signal line and a common line; and wherein: a reset pulse is transmitted to all the local units from the sequencer through the synchronizing signal line to reset all the local units to initial state in a normal cycle
**WARNING** end of DESC field may overlap start of CLMS **.
Claims (4)
1 A sequence control system having a sequencer and a plurality of local units each serving as a sensor; the sequencer and all the local units being connected by four lines including a synchronizing signal line, a selection signal line, an information signal line and a common line; and wherein: a reset pulse is transmitted to all the local units from the sequencer through the synchronizing signal line to reset all the local units to an initial state in a normal cycle for information collection; a selection signal pulse train consisting of a series of pulses whose number is the same as the number of local units is transmitted from the sequencer through the selection signal line; pulses of the selection signal pulse train are simultaneously counted in each local unit; a pulse is sent back or not to the sequencer from the local unit through the information signal line, depending upon the state of on or off of the local unit, within one bit time of the pulse as hereinbefore defined, when the pulse of the same number as the address number of each local unit has been counted; at the time of switching to an information test cycle an information test cycle command signal consisting of a number of pulses is transmitted to all the local units from the sequencer through the selection signal line to simultaneously set all the local units to an information test state following the selection signal pulse train; information concerning whether or not the function of sending back information at each local unit is effective is sequentially sent back to the sequencer from each local unit through the information signal line, in synchronism with the selection signal pulse train in the information test cycle; and a reset command signal for resetting consisting of pulses ;s transmitted to all the local units from the sequencer following the selection signal pulse train through the selection signal line to reset all the local units simultaneously to the information test state.
2. A sequence control system having a sequencer and a plurality of local units each serving as a sensor and as a control for process equipment; the sequencer and all the local units being connected with six lines including a synchronizing signal line, a selection signal line, an information signal line, an on-control signal line, an off-control signal line and a common line; and wherein: a reset pulse is transmitted to all the local units from the sequencer through the synchronizing signal line to reset all the local units to initial state in a normal cycle
for information collection and process equipment control; a selection signal pulse train consisting of a series of pulses whose number is the same as the number of local units, is transmitted from the sequencer through the selection signal line; pulses of the selection signal pulse train are simultaneously counted in each local unit; a pulse is sent back or not to the sequencer from the local unit through the information signal line depending upon the state of on or off of the local unit within one bit time of pulse as hereinbefore defined when the pulse of the same number as the address number of each local unit has been connected; at the same time an on-control signal or an off-control signal is transmitted to the local unit from the sequencer within one bit time which is assigned for each local unit through the on-control signal line or the off-control signal line to control process equipment on or off; at the time of switching to an information test cycle an information test cycle command signal consisting of a number of pulses is transmitted to all the local units from the sequencer through the selection signal line to simultaneously set all the local unit to an information test state following the selection signal pulse train; information concerning whether the function of sending back information at each local unit is effective or not is sequentially sent back to he sequencer from each local unit through the information signal line in synchronism with the selection signal pulse train in the information test cycle; at the time of switching to a control test cycle a control test cycle command signal consisting of a number of pulses is transmitted to all the local units from the sequencer through the selection signal line simultaneously to set all the local units to a control test state following the selection signal pulse train; information concerning whether the function of controlling at each local unit is effective or not is sequentially sent back to the sequencer from each local unit through the information signal line in synchronism with the selection signal pulse train in the control test cycle; and at the time of returning to the normal cycle, a reset command signal for resetting consisting of pulses is transmitted to all the local units from the sequencer following the selection signal pulse train through the selection signal line simultaneously to reset all the local units to the test state.
3. The sequence control system according to Claim 1 or Claim 2, wherein a logical exclusive OR operation for a sampling value of a pulse in a preceding normal cycle and that of the pulse in the present normal cycle is carried out at the time of counting up of the pulse sent back to the sequencer from the local unit corresponding to on-state of the sensor through the information signal line, and an AND operation for the value of said logical exclusive OR operation and the sampling value of the pulse in the preceding normal cycle is carried out, whereby one pulse from the sensor is counted up when the result of said AND operation coincides with "1".
4. A sequence control system substantially as described with reference to and as illustrated in Figures 2 to 8 of the accompanying drawings.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB374778A GB1565943A (en) | 1978-01-31 | 1978-01-31 | Sequence control system having functions of automatic prevention and maintenance |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB374778A GB1565943A (en) | 1978-01-31 | 1978-01-31 | Sequence control system having functions of automatic prevention and maintenance |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| GB1565943A true GB1565943A (en) | 1980-04-23 |
Family
ID=9764218
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB374778A Expired GB1565943A (en) | 1978-01-31 | 1978-01-31 | Sequence control system having functions of automatic prevention and maintenance |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB1565943A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0050624A1 (en) * | 1980-04-10 | 1982-05-05 | Fui Keong Yong | Electrical supervisory control and data acquisition system. |
| EP0084526A2 (en) * | 1982-01-19 | 1983-07-27 | Lykke Olesen | Data transmission device |
| GB2136252A (en) * | 1980-05-30 | 1984-09-12 | Pioneer Electronic Corp | Polling Pattern Generator for CATV System |
-
1978
- 1978-01-31 GB GB374778A patent/GB1565943A/en not_active Expired
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0050624A1 (en) * | 1980-04-10 | 1982-05-05 | Fui Keong Yong | Electrical supervisory control and data acquisition system. |
| EP0050624A4 (en) * | 1980-04-10 | 1982-07-30 | Fui Keong Yong | Electrical supervisory control and data acquisition system. |
| GB2136252A (en) * | 1980-05-30 | 1984-09-12 | Pioneer Electronic Corp | Polling Pattern Generator for CATV System |
| EP0084526A2 (en) * | 1982-01-19 | 1983-07-27 | Lykke Olesen | Data transmission device |
| EP0084526A3 (en) * | 1982-01-19 | 1983-09-07 | Lykke Olesen | Data transmission device |
| US4559536A (en) * | 1982-01-19 | 1985-12-17 | Lykke Olesen | Data transmission device |
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| PE20 | Patent expired after termination of 20 years |
Effective date: 19980130 |