JP2551131B2 - Self-routing speech path failure detection circuit - Google Patents

Description

The present invention relates to a switching system using a self-routing speech path that performs self-routing operation based on header information, and particularly detects a failure in the self-routing speech path. For a self-routing speech path failure detection circuit.

[Conventional technology]

Various circuits used in space division exchanges and time division exchanges are known as speech path fault detection circuits for detecting speech line faults of exchanges.

These conventional call path failure detection circuits have a call path configuration in which the call information is transparently carried from the input terminal to the output terminal on the call path set by control information other than the call information such as wiring logic or software control. It was a circuit as a premise.

[Problems to be Solved by the Invention]

On the other hand, the input call information is asynchronously input in the self-routing call path. Then, each time the call information is input, the header information added thereto is used to carry the call information from the input terminal to the output terminal while autonomously setting the call path.

Therefore, the conventionally used speech path failure detection circuit for the space division exchange or the time division exchange cannot be used for the self-routing speech path.

Therefore, an object of the present invention is to provide a self-routing speech path failure detection circuit that can detect a failure in a self-routing speech path.

[Means for solving the problem]

According to the present invention, a self-routing speech path in which a switch performs self-routing operation between a plurality of incoming line transmission lines and a plurality of outgoing line transmission lines according to header information of a fixed length packet,
An empty packet detection circuit that detects the presence of an empty packet in the incoming transmission path of this self-routing communication path, and test drive information and an empty packet detection circuit that are input when diagnosing the communication path and detecting the presence or absence of a fault A first AND circuit which receives the output of the first AND circuit and takes these logics, and a counting circuit which inputs the output of the first AND circuit and counts the number of empty packets and outputs the count information representing this. , A test pattern generation circuit that generates test pattern information, test pattern information as call information for fixed length packets, and count information as header information that specifies the outgoing line of a self-routing call path are input in parallel, and fixed length packet format Parallel-serial conversion circuit for converting to serial data, and two inputs for the input transmission line and the output of the parallel-serial conversion circuit. The logic of the output of the selector circuit and the selector circuit provided for each incoming line that selects one of them and inputs it from the corresponding input terminal of the self-routing speech path is true. When the output of the parallel-serial conversion circuit is selected by the selector circuit corresponding to the input line transmission line specified by the input line designation information that represents one input line transmission line to be tested, otherwise the actual call information on the input line transmission line And a selection signal generation circuit that supplies a selection signal for selecting a fixed-length packet with a selection input terminal of each selector circuit, and the output of the first AND circuit is held true for a predetermined time after the output logic becomes true. And an output of the corresponding output terminal of the self-routing speech path, and a third AND circuit and a test pattern Information and a matcher circuit that determines whether or not the information in the call information area matches, and inputs the output of this matcher circuit and the output of the first AND circuit, and counts the timing by the output of the first AND circuit. The self-routing speech path fault detection circuit is equipped with a timing circuit that starts the start-up and monitors whether the matcher circuit outputs a normal judgment within a predetermined time and outputs the result as fault information of the self-routing speech path. Let

Then, when a failure occurs in the self-routing speech path, an output for displaying failure information is output from the output terminal of the timing determination circuit.

〔Example〕

 Hereinafter, the present invention will be described in detail.

FIG. 1 shows a self-routing speech path failure detection circuit according to an embodiment of the present invention.

An empty packet detection circuit 12 for detecting an empty packet (cell) is connected to the incoming line 11 and outputs 13
Is input to the first AND circuit 15 together with the test drive information 14 to be ORed. The output 16 of the first AND circuit 15 serves as one input to each of the second AND circuit 17 and the third AND circuit 18, and is also input to the counting circuit 19 and the timing determination circuit 21. There is. The input line designation information 22 is input to the other terminal of the second AND circuit 17. The counting circuit 19 counts the number of empty packets, and the counting information 23 representing this counts the test pattern generating circuit 24.
Test pattern information 25 output from
It is input to the serial conversion circuit 26 and converted into serial data 27. This converted serial data 27 is the call information.
It is supplied together with 28 to a selector circuit 29 provided corresponding to the incoming transmission line 11. The selecting operation of the selector circuit 29 is controlled by the logical sum output 31 of the second AND circuit 17. The output 32 of the selector circuit 29 is supplied to one input terminal of the self-routing speech path 33.

Output 34 from one output terminal of self-routing channel 33
Becomes the other input of the third AND circuit 18. The logical sum output 35 of the third AND circuit 18 is the test pattern generation circuit.
It is input to the matcher circuit 36 together with the test pattern information 25 output from 24. The output signal 37 of the matcher circuit 36 is input to the timing determination circuit 21 together with the output 16 of the first AND circuit. A failure information display signal 38 is output from the timing determination circuit 21.

The operation of the self-routing speech path failure detection circuit configured as above will be described below.

Call information of some calls is asynchronous on the incoming line 11
Will be sent. The call information 28 is in the format of a fixed length packet signal and has a header information area and a call information area (not shown). An area is designated on the transmission path in fixed packet length units. Since the call information 28 of some calls is input asynchronously, each fixed-length packet area has a free / closed bit to indicate whether it is an empty packet or a valid packet. The empty packet detection circuit 12 detects the position of the empty packet on the incoming line 11 by this.

When diagnosing the communication path and detecting the presence or absence of a failure, the test drive information 14 is sent from the outside to the self-routing communication path failure detection circuit. The first AND circuit 15 inputs the test drive information 14 and the output 13 of the empty packet detection circuit 12, and outputs the output 16 at H level only when an empty packet is detected.
(High) level. As a result of this, the counting circuit 19
The number of empty packets in the state where the test drive information 14 is sent is counted up. The counting information 23 output from the counting circuit 19 functions as header information that specifies the outgoing line of the self-routing communication path 33. Test pattern generation circuit
The test pattern information 25 output by 24 is used in a call information area of a fixed length packet. A specific configuration of the test pattern generation circuit 24 is a memory circuit that stores a fixed pattern having the same information length as the call information area. A single or a plurality of test patterns are stored here.

The count information 23 output from the counting circuit 19 and the test pattern information 25 described above are input to the input terminal of the parallel-serial conversion circuit 26, and the serial data 27 is output from the output terminal in the fixed-length packet format. . The selector circuit 29 inputs this serial data 27 and the call information 28 transmitted through the incoming line 11. This selector circuit
29 are provided corresponding to the incoming transmission lines 11, that is, corresponding to the input terminals of the self-routing communication line 33, respectively. Therefore, only the selector circuit 29 corresponding to the incoming line 11 to be tested operates and sends the serial data 27 as the output of the parallel-serial conversion circuit 26 as the output 32 to the self-routing speech path 33. .

When there is no empty packet on the incoming line 11, the logical sum output 31 of the first AND circuit 17 is L (low).
It remains at the level. In this case, the selector circuit 29
Selects a fixed-length packet having actual call information on the incoming line 11.

Now, the fixed-length packet information created by the parallel-serial conversion circuit 26 should be output to the output terminal of the self-routing communication path 33 specified by the counting information 23 output from the counting circuit 19. Third AND circuit 18
Is a corresponding output terminal of the self-routing speech path 33 and an output terminal of a holding circuit (not shown) which holds the value for a predetermined time when the value output from the first AND circuit 15 becomes H (high). Is connected to its input side. For this reason,
If the self-routing communication path 33 is normal, the parallel-serial conversion circuit 26 is connected to the output terminal of the third AND circuit 18.
As a result, the same data as the serial data 27 is output. The matcher circuit 36 inputs the logical sum output 35 of the third AND circuit 18 and the test pattern information 25 output from the test pattern generation circuit 24, and determines whether the information in the call information area matches. The timing determination circuit 21 receives the output signal 37 of the matcher circuit 36 and the output 16 of the first AND circuit 15. Therefore, the timing counting is started from the time when the diagnosis of the communication path is started by the output of the first AND circuit 15. In the self-routing speech path, generally speaking, speech information is input asynchronously, and several calls are carried in common on one incoming transmission path. Even at the outgoing line of the self-routing speech path 33, some calls may overlap asynchronously. Therefore, the self-routing speech path 33 has a buffer memory of a predetermined size inside (not shown) so that the speech information is not discarded even if the asynchronous speech information overlaps at the output terminal.

Therefore, even if the call information is input to the incoming line of the self-routing call path 33, the call information may be delayed by the time required for reading the buffer memory at the maximum for the information to be output to the output terminal. is there. The timing judgment circuit 21 starts counting the timing by the output 16 of the first AND circuit 15, and determines whether the matcher circuit 36 outputs the normal judgment as the output signal 37 within the delay of the reading time of the buffer memory. I'm watching. In this way, the fault information display signal 38 output from the timing determination circuit 21 indicates whether or not there is a fault.

By the way, when testing an input line having the self-routing communication path 33, the corresponding input line number is designated as the input line designation information 22 by an external control device (not shown). The counting circuit 19 is a circuit that counts the number of empty packets, and also indicates to which output terminal of the self-routing communication path 33 the fixed length packet created by the parallel-serial conversion circuit 26 is connected. During a given input line designation, the counting circuit 19 designates an incremented output terminal of the self-routing channel 33 each time an empty packet arrives on the input line. Therefore, the connection path between the input line having the self-routing communication path 33 and all the output terminals can be experienced. Next, by specifying another input line from the external control device (not shown) in the input line designation information 22, the connection between that input line of the self-routing speech path 33 and all input lines and all output terminals The route can be tested. In this way it is possible to test the connections between all input lines and all output terminals of the self-routing speech path 33.

〔The invention's effect〕

As described above, in the self-routing speech path failure detection circuit of the present invention, the selector circuit is arranged corresponding to each incoming transmission path in the switching system using the self-routing speech path, but the other circuits are commonly used. It is composed. Therefore, the circuit scale can be reduced by these common circuit portions.

Further, since the test pattern is inserted into the call information area for verification, it is possible to test the normality of the call information area of the packet during transmission in the self-routing call path. Further, the present invention has a merit that the call information is transferred asynchronously, the information is transferred while the call path is autonomously set by the header information added to the call information, and the effective use of the transfer path is possible. To realize a failure detection circuit for a speech path in the speech path. Therefore, the usefulness of this circuit will be extremely high in consideration of future development of communication means.

[Brief description of drawings]

FIG. 1 is a block diagram of a self-routing speech path failure detection circuit according to an embodiment of the present invention. 11 ... Empty packet detection circuit, 14 ... Test drive information, 15 ... First AND circuit, 17 ... Second AND circuit, 18 ... Third AND circuit, 19 ... Counting circuit, 21 ... … Timing judgment circuit, 24 …… Test pattern generation circuit, 33 …… Self-routing communication path, 36 …… Matcher circuit, 38 …… Fault information display signal.

Claims (1)

(57) [Claims] 1. A self-routing speech path in which a switch performs a self-routing operation between a plurality of ingress transmission paths and a plurality of egress transmission paths according to header information of a fixed length packet, and an ingress transmission path of the self-routing speech path. An empty packet detection circuit that detects the existence of an empty packet, test drive information that is input when diagnosing a communication path to detect the presence or absence of a fault, and the output of the empty packet detection circuit are input to these logics. , A counting circuit for inputting the output of the first AND circuit, counting the number of empty packets, and outputting counting information representing this, and a test pattern for generating test pattern information. A generation circuit, and the test pattern information as the call information of the fixed length packet, and the header information for designating the outgoing line of the self-routing call path. A parallel-serial conversion circuit that inputs count information in parallel and converts it into serial data in the fixed-length packet format, and an output of the input line transmission line and the parallel-serial conversion circuit as two inputs. A selector circuit is provided for each input line transmission line which selects one of them and inputs it from the corresponding input terminal of the self-routing speech line, and an attempt is made to test when the output logic of the first AND circuit is true. The selector circuit corresponding to the input line transmission line designated by the input line designation information representing one input line transmission line to select the output of the parallel-serial conversion circuit, and the other has the actual call information on the input line transmission line. A selection signal generation circuit for supplying a selection signal for selecting a fixed-length packet to a selection input terminal of each selector circuit; Thirdly, the logic of the output of the AND circuit of 1 becomes true for a predetermined time after it becomes true and the output of the corresponding output terminal of the self-routing speech path
AND circuit of the third AND circuit, and a matcher circuit which inputs the output of the third AND circuit and the test pattern information and determines whether or not the information in the call information area matches, and the output of the matcher circuit and the first AND circuit. The output of the circuit is input, the timing of counting is started by the output of the first AND circuit, and it is monitored whether the matcher circuit outputs the normal judgment within the predetermined time, and the result is self-routed. And a timing circuit for outputting as fault information of the self-routing speech path fault detection circuit.