GB1521790A - Current mode half and full adders - Google Patents

Current mode half and full adders

Info

Publication number
GB1521790A
GB1521790A GB4077976A GB4077976A GB1521790A GB 1521790 A GB1521790 A GB 1521790A GB 4077976 A GB4077976 A GB 4077976A GB 4077976 A GB4077976 A GB 4077976A GB 1521790 A GB1521790 A GB 1521790A
Authority
GB
United Kingdom
Prior art keywords
gate
transistor
level logic
output
reference voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB4077976A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull HN Information Systems Italia SpA
Bull HN Information Systems Inc
Original Assignee
Honeywell Information Systems Italia SpA
Honeywell Information Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell Information Systems Italia SpA, Honeywell Information Systems Inc filed Critical Honeywell Information Systems Italia SpA
Publication of GB1521790A publication Critical patent/GB1521790A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/501—Half or full adders, i.e. basic adder cells for one denomination
    • G06F7/502—Half adders; Full adders consisting of two cascaded half adders
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/48—Indexing scheme relating to groups G06F7/48 - G06F7/575
    • G06F2207/4802—Special implementations
    • G06F2207/4806—Cascode or current mode logic

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)
  • Analogue/Digital Conversion (AREA)
GB4077976A 1975-10-01 1976-10-01 Current mode half and full adders Expired GB1521790A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US61870975A 1975-10-01 1975-10-01

Publications (1)

Publication Number Publication Date
GB1521790A true GB1521790A (en) 1978-08-16

Family

ID=24478821

Family Applications (1)

Application Number Title Priority Date Filing Date
GB4077976A Expired GB1521790A (en) 1975-10-01 1976-10-01 Current mode half and full adders

Country Status (7)

Country Link
JP (1) JPS5926056B2 (enrdf_load_stackoverflow)
AU (1) AU1821276A (enrdf_load_stackoverflow)
BE (1) BE846854A (enrdf_load_stackoverflow)
CA (1) CA1076706A (enrdf_load_stackoverflow)
DE (1) DE2643609A1 (enrdf_load_stackoverflow)
FR (1) FR2326739A1 (enrdf_load_stackoverflow)
GB (1) GB1521790A (enrdf_load_stackoverflow)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4215418A (en) * 1978-06-30 1980-07-29 Trw Inc. Integrated digital multiplier circuit using current mode logic

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3519810A (en) * 1967-02-14 1970-07-07 Motorola Inc Logic element (full adder) using transistor tree-like configuration
US3978329A (en) * 1975-09-12 1976-08-31 Bell Telephone Laboratories, Incorporated One-bit full adder

Also Published As

Publication number Publication date
DE2643609C2 (enrdf_load_stackoverflow) 1988-09-22
BE846854A (fr) 1977-01-31
AU1821276A (en) 1978-04-06
JPS5244127A (en) 1977-04-06
FR2326739A1 (fr) 1977-04-29
CA1076706A (en) 1980-04-29
DE2643609A1 (de) 1977-04-14
JPS5926056B2 (ja) 1984-06-23

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Legal Events

Date Code Title Description
PS Patent sealed
PCNP Patent ceased through non-payment of renewal fee