GB1496148A - Circuit arrangement employing a memory with random access - Google Patents

Circuit arrangement employing a memory with random access

Info

Publication number
GB1496148A
GB1496148A GB5318274A GB5318274A GB1496148A GB 1496148 A GB1496148 A GB 1496148A GB 5318274 A GB5318274 A GB 5318274A GB 5318274 A GB5318274 A GB 5318274A GB 1496148 A GB1496148 A GB 1496148A
Authority
GB
United Kingdom
Prior art keywords
memory
address
writing
fed
chronologically
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB5318274A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ABB Training Center GmbH and Co KG
Original Assignee
Hartmann and Braun AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hartmann and Braun AG filed Critical Hartmann and Braun AG
Publication of GB1496148A publication Critical patent/GB1496148A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G1/00—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data
    • G09G1/06—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data using single beam tubes, e.g. three-dimensional or perspective representation, rotation or translation of display pattern, hidden lines, shadows
    • G09G1/14—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data using single beam tubes, e.g. three-dimensional or perspective representation, rotation or translation of display pattern, hidden lines, shadows the beam tracing a pattern independent of the information to be displayed, this latter determining the parts of the pattern rendered respectively visible and invisible
    • G09G1/16—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data using single beam tubes, e.g. three-dimensional or perspective representation, rotation or translation of display pattern, hidden lines, shadows the beam tracing a pattern independent of the information to be displayed, this latter determining the parts of the pattern rendered respectively visible and invisible the pattern of rectangular co-ordinates extending over the whole area of the screen, i.e. television type raster
    • G09G1/162—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data using single beam tubes, e.g. three-dimensional or perspective representation, rotation or translation of display pattern, hidden lines, shadows the beam tracing a pattern independent of the information to be displayed, this latter determining the parts of the pattern rendered respectively visible and invisible the pattern of rectangular co-ordinates extending over the whole area of the screen, i.e. television type raster for displaying digital inputs as analog magnitudes, e.g. curves, bar graphs, coordinate axes, singly or in combination with alpha-numeric characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G1/00—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data
    • G09G1/02—Storage circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Remote Sensing (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
  • Radar Systems Or Details Thereof (AREA)
  • Digital Computer Display Output (AREA)
  • Complex Calculations (AREA)

Abstract

1496148 Digital data storage HARTMANN & BRAUN AG 9 Dec 1974 [19 Jan 1974] 53182/74 Heading G4A A randomly accessible memory SP for use as an image repetition memory in a data display device has values MW sequentially stored therein by means of an address counter AZ incremented by clock pulses TJ, writing addresses SA being fed from the address counter AZ to the memory during a writing cycle, one of the (in general) chronologically older values stored in the memory being read out first at the start of a subsequent sequential reading cycle. This is achieved in effect by adding 1 to the last-used writing address SA (to produce the chronologically newest address) and then adding a relative interrogation address AFA to the sum, the actual additions being carried out in a different order by adder stages AS and KA. The resulting reading address LA is then fed to the memory to access the corresponding stored value.
GB5318274A 1974-01-19 1974-12-09 Circuit arrangement employing a memory with random access Expired GB1496148A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19742402549 DE2402549C3 (en) 1974-01-19 1974-01-19 Circuit arrangement for data storage with random access

Publications (1)

Publication Number Publication Date
GB1496148A true GB1496148A (en) 1977-12-30

Family

ID=5905181

Family Applications (1)

Application Number Title Priority Date Filing Date
GB5318274A Expired GB1496148A (en) 1974-01-19 1974-12-09 Circuit arrangement employing a memory with random access

Country Status (5)

Country Link
BE (1) BE824440A (en)
DE (1) DE2402549C3 (en)
FR (1) FR2258688B3 (en)
GB (1) GB1496148A (en)
NL (1) NL7415411A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4218757A (en) * 1978-06-29 1980-08-19 Burroughs Corporation Device for automatic modification of ROM contents by a system selected variable

Also Published As

Publication number Publication date
BE824440A (en) 1975-05-15
FR2258688A1 (en) 1975-08-18
DE2402549A1 (en) 1975-07-24
NL7415411A (en) 1975-07-22
DE2402549C3 (en) 1978-06-29
DE2402549B2 (en) 1976-03-18
FR2258688B3 (en) 1977-10-14

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Legal Events

Date Code Title Description
PS Patent sealed
PCNP Patent ceased through non-payment of renewal fee