GB1495419A - Carrier frequency systems with main and stand-by phase-controlled oscillators - Google Patents

Abstract

1495419 Data transmission SIEMENS AG 27 March 1975 [9 April 1974 (2)] 13106/75 Heading H4P A carrier frequency system having main and at least one stand-by phase controlled oscillators each being connected to a local synchronization detector which also receives a common control frequency has oscillator disconnection switches with, on poles remote from the oscillator, an amplitude level detector with an output controlling its local sync. detector, each oscillator having an identical alarm and switch over unit controlled by the level detector comprising a first gate having an output to a first interconnection terminal and to a (NAND) second gate with commoned outputs to a first alarm effective when all oscillators are defective, a second NAND gate input being common to a third gate controlling the disconnecting switches, a second alarm being rendered effective to switch over to stand-by oscillator(s) on failure of any oscillator. Main oscillator OB of frequency harmonically related to a control frequency fst has its output monitored by synchronism detector SD, also receiving inputs from one or more stand-by oscillators OE of the same or harmonically related frequency also the control frequency fst, the output being passed through disconnecting switch UB to an amplitude level detection circuit G and common output terminal (unreferenced) to which other oscillators, provided with similar monitoring circuits are connected. A common alarm A operates if both units become defective, or B on failure of the main oscillator which causes switch over. The alarm circuits comprise NAND gates 1,2,3, 6 with output terminals U-Z bridged in dependence whether an oscillator is main or stand-by, and manual reset key LT. In one modification, NAND gates 4, 5 are added as shown which avoid a switch over if any stand-by oscillator is disturbed. A second modification (Fig. 2, not shown) provides automatic reset by eliminating gates 6 and the B alarm circuit is connected through diodes to a common input to gates 1. Each sychronism detector may comprise an exclusive OR gate 10, Fig. 3, formed by NAND gates 16-19 having an output E fed via low pass filter 20 to a transistor switching stage 21, 22. The circuit is fed with the control frequency fst together with outputs from the phase discriminators of the oscillators through a plural input NAND gate 12 feeding a flip-flop 11 which may be synchronized by a pulse generator 24 formed by NAND gates 13-15. An alarm signal is generated in the event of non synchronism of any phase lock loop from any cause or a break in any connection line. Provision (not shown) is made to switch the band width of the low pass filter in phase control loops. Interference pulses may be suppressed by the insertion of a delay element in line A if the phase discriminators by themselves do not provide sufficient lag. The arrangement is particularly suited to I.C. phase controlled oscillators; certain NAND gates may be replaced by inverters.