GB1468342A - Adder or priority-determining circuits for computers - Google Patents

Adder or priority-determining circuits for computers

Info

Publication number
GB1468342A
GB1468342A GB4476372A GB4476372A GB1468342A GB 1468342 A GB1468342 A GB 1468342A GB 4476372 A GB4476372 A GB 4476372A GB 4476372 A GB4476372 A GB 4476372A GB 1468342 A GB1468342 A GB 1468342A
Authority
GB
United Kingdom
Prior art keywords
stage
carry
cmos
logic
adder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB4476372A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hawker Siddeley Dynamics Ltd
Original Assignee
Hawker Siddeley Dynamics Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hawker Siddeley Dynamics Ltd filed Critical Hawker Siddeley Dynamics Ltd
Priority to GB4476372A priority Critical patent/GB1468342A/en
Priority to FR7402479A priority patent/FR2215654B3/fr
Priority to NL7401039A priority patent/NL7401039A/xx
Priority to DE19742404145 priority patent/DE2404145A1/de
Publication of GB1468342A publication Critical patent/GB1468342A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/501—Half or full adders, i.e. basic adder cells for one denomination
    • G06F7/503—Half or full adders, i.e. basic adder cells for one denomination using carry switching, i.e. the incoming carry being connected directly, or only via an inverter, to the carry output under control of a carry propagate signal

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)
GB4476372A 1973-01-28 1973-01-28 Adder or priority-determining circuits for computers Expired GB1468342A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
GB4476372A GB1468342A (en) 1973-01-28 1973-01-28 Adder or priority-determining circuits for computers
FR7402479A FR2215654B3 (enrdf_load_stackoverflow) 1973-01-28 1974-01-25
NL7401039A NL7401039A (enrdf_load_stackoverflow) 1973-01-28 1974-01-25
DE19742404145 DE2404145A1 (de) 1973-01-28 1974-01-26 Binaere paralleladdierschaltung

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB4476372A GB1468342A (en) 1973-01-28 1973-01-28 Adder or priority-determining circuits for computers

Publications (1)

Publication Number Publication Date
GB1468342A true GB1468342A (en) 1977-03-23

Family

ID=10434644

Family Applications (1)

Application Number Title Priority Date Filing Date
GB4476372A Expired GB1468342A (en) 1973-01-28 1973-01-28 Adder or priority-determining circuits for computers

Country Status (4)

Country Link
DE (1) DE2404145A1 (enrdf_load_stackoverflow)
FR (1) FR2215654B3 (enrdf_load_stackoverflow)
GB (1) GB1468342A (enrdf_load_stackoverflow)
NL (1) NL7401039A (enrdf_load_stackoverflow)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2647982A1 (de) * 1976-10-22 1978-04-27 Siemens Ag Logische schaltungsanordnung in integrierter mos-schaltkreistechnik
US4254471A (en) * 1978-04-25 1981-03-03 International Computers Limited Binary adder circuit
DE3035631A1 (de) * 1980-09-20 1982-05-06 Deutsche Itt Industries Gmbh, 7800 Freiburg Binaerer mos-paralleladdierer

Also Published As

Publication number Publication date
FR2215654B3 (enrdf_load_stackoverflow) 1976-11-19
NL7401039A (enrdf_load_stackoverflow) 1974-07-30
DE2404145A1 (de) 1974-09-05
FR2215654A1 (enrdf_load_stackoverflow) 1974-08-23

Similar Documents

Publication Publication Date Title
US4601007A (en) Full adder
US3932734A (en) Binary parallel adder employing high speed gating circuitry
US4682303A (en) Parallel binary adder
US3465133A (en) Carry or borrow system for arithmetic computations
US4831578A (en) Binary adder
GB1052400A (enrdf_load_stackoverflow)
JPS6159014B2 (enrdf_load_stackoverflow)
US5343418A (en) Three-to-two carry save adder cell
GB1468342A (en) Adder or priority-determining circuits for computers
GB963429A (en) Electronic binary parallel adder
US4860242A (en) Precharge-type carry chained adder circuit
US4873660A (en) Arithmetic processor using redundant signed digit arithmetic
US3454751A (en) Binary adder circuit using denial logic
GB1333645A (en) Divider circuits
McCluskey Logical design theory of NOR gate networks with no complemented inputs
GB1280392A (en) High-speed parallel binary adder
GB914014A (en) Parallel digital adder system
GB1171266A (en) Arithmetic and Logic Circuits, e.g. for use in Computing
JPS6010910A (ja) ラツチ回路アレイ
GB1135108A (en) Binary digital circuits
GB1037802A (en) Arithmetic circuit
US3249747A (en) Carry assimilating system
US2933252A (en) Binary adder-subtracter with command carry control
US4449197A (en) One-bit full adder circuit
GB1131958A (en) Binary adder

Legal Events

Date Code Title Description
PS Patent sealed
435 Patent endorsed 'licences of right' on the date specified (sect. 35/1949)
732 Registration of transactions, instruments or events in the register (sect. 32/1977)
PCNP Patent ceased through non-payment of renewal fee