GB1388629A - Bipolar to mos interface circuit - Google Patents

Bipolar to mos interface circuit

Info

Publication number
GB1388629A
GB1388629A GB2131972A GB2131972A GB1388629A GB 1388629 A GB1388629 A GB 1388629A GB 2131972 A GB2131972 A GB 2131972A GB 2131972 A GB2131972 A GB 2131972A GB 1388629 A GB1388629 A GB 1388629A
Authority
GB
United Kingdom
Prior art keywords
turn
gate
drain
source
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB2131972A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Microsystems International Ltd
Original Assignee
Microsystems International Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from CA116959A external-priority patent/CA918757A/en
Application filed by Microsystems International Ltd filed Critical Microsystems International Ltd
Priority claimed from CA218,493A external-priority patent/CA1057331A/en
Publication of GB1388629A publication Critical patent/GB1388629A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/01855—Interface arrangements synchronous, i.e. using clock signals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Logic Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
GB2131972A 1971-06-29 1972-05-08 Bipolar to mos interface circuit Expired GB1388629A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
CA116959A CA918757A (en) 1972-01-17 1971-06-29 Bipolar to mos interface circuit
US21849472A 1972-01-17 1972-01-17
CA218,493A CA1057331A (en) 1974-02-07 1975-01-23 Aspirated vehicle occupant restraint system

Publications (1)

Publication Number Publication Date
GB1388629A true GB1388629A (en) 1975-03-26

Family

ID=27161283

Family Applications (2)

Application Number Title Priority Date Filing Date
GB2131872A Expired GB1341334A (en) 1971-06-29 1972-05-08 Static bipolar to mos interface circuit
GB2131972A Expired GB1388629A (en) 1971-06-29 1972-05-08 Bipolar to mos interface circuit

Family Applications Before (1)

Application Number Title Priority Date Filing Date
GB2131872A Expired GB1341334A (en) 1971-06-29 1972-05-08 Static bipolar to mos interface circuit

Country Status (3)

Country Link
DE (1) DE2231203A1 (enExample)
FR (1) FR2144361A5 (enExample)
GB (2) GB1341334A (enExample)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5759689B2 (enExample) * 1974-09-30 1982-12-16 Citizen Watch Co Ltd
DE3026040C2 (de) * 1980-07-09 1982-05-27 Siemens AG, 1000 Berlin und 8000 München Schalter mit in Serie geschalteten MOS-FET

Also Published As

Publication number Publication date
FR2144361A5 (enExample) 1973-02-09
GB1341334A (en) 1973-12-19
DE2231203A1 (de) 1973-01-25

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Legal Events

Date Code Title Description
PS Patent sealed [section 19, patents act 1949]
PLNP Patent lapsed through nonpayment of renewal fees