GB1326129A - Method for forming an interconnection through an insulating layer - Google Patents

Method for forming an interconnection through an insulating layer

Info

Publication number
GB1326129A
GB1326129A GB2932271A GB2932271A GB1326129A GB 1326129 A GB1326129 A GB 1326129A GB 2932271 A GB2932271 A GB 2932271A GB 2932271 A GB2932271 A GB 2932271A GB 1326129 A GB1326129 A GB 1326129A
Authority
GB
United Kingdom
Prior art keywords
photo
opening
region
layer
irradiation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB2932271A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of GB1326129A publication Critical patent/GB1326129A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
    • H05K3/427—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in metal-clad substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0023—Etching of the substrate by chemical or physical means by exposure and development of a photosensitive insulating layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0355—Metal foils
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0388—Other aspects of conductors
    • H05K2201/0394—Conductor crossing over a hole in the substrate or a gap between two separate substrate parts
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09563—Metal filled via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05—Patterning and lithography; Masks; Details of resist
    • H05K2203/0548—Masks
    • H05K2203/0554—Metal used as mask for etching vias, e.g. by laser ablation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
    • H05K3/4069—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in organic insulating substrates
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49156—Manufacturing circuit on or in base with selective destruction of conductive paths
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)
GB2932271A 1970-09-04 1971-06-22 Method for forming an interconnection through an insulating layer Expired GB1326129A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US6964670A 1970-09-04 1970-09-04

Publications (1)

Publication Number Publication Date
GB1326129A true GB1326129A (en) 1973-08-08

Family

ID=22090315

Family Applications (1)

Application Number Title Priority Date Filing Date
GB2932271A Expired GB1326129A (en) 1970-09-04 1971-06-22 Method for forming an interconnection through an insulating layer

Country Status (4)

Country Link
US (1) US3778900A (enExample)
DE (1) DE2144137A1 (enExample)
FR (1) FR2101773A5 (enExample)
GB (1) GB1326129A (enExample)

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4008300A (en) * 1974-10-15 1977-02-15 A & P Products Incorporated Multi-conductor element and method of making same
US4054479A (en) * 1976-12-22 1977-10-18 E. I. Du Pont De Nemours And Company Additive process for producing printed circuit elements using a self-supported photosensitive sheet
US4054483A (en) * 1976-12-22 1977-10-18 E. I. Du Pont De Nemours And Company Additives process for producing plated holes in printed circuit elements
US4157407A (en) * 1978-02-13 1979-06-05 E. I. Du Pont De Nemours And Company Toning and solvent washout process for making conductive interconnections
US4341591A (en) * 1981-04-08 1982-07-27 Rca Corporation Method of fabricating a color-selection structure for a CRT
US4413051A (en) * 1981-05-04 1983-11-01 Dynamics Research Corporation Method for providing high resolution, highly defined, thick film patterns
US4487828A (en) * 1983-06-03 1984-12-11 At&T Technologies, Inc. Method of manufacturing printed circuit boards
DE3477455D1 (en) * 1984-07-16 1989-04-27 Ibm Deutschland Manufacture of connection holes in plastic plates and application of the method
CA1276972C (en) * 1986-10-22 1990-11-27 David S. Strong Multi-cell metal/air battery
JP2702507B2 (ja) * 1988-05-31 1998-01-21 キヤノン株式会社 電気的接続部材及びその製造方法
US5216807A (en) * 1988-05-31 1993-06-08 Canon Kabushiki Kaisha Method of producing electrical connection members
US5807453A (en) * 1995-05-04 1998-09-15 Tessera, Inc. Fabrication of leads on semiconductor connection components
EP0976307A1 (en) * 1997-04-16 2000-02-02 AlliedSignal Inc. Positive working photodefinable resin coated metal for mass production of microvias in multilayer printed wiring boards
US6255039B1 (en) 1997-04-16 2001-07-03 Isola Laminate Systems Corp. Fabrication of high density multilayer interconnect printed circuit boards
US6120693A (en) * 1998-11-06 2000-09-19 Alliedsignal Inc. Method of manufacturing an interlayer via and a laminate precursor useful for same
US6103134A (en) * 1998-12-31 2000-08-15 Motorola, Inc. Circuit board features with reduced parasitic capacitance and method therefor
GB2369453B (en) * 2000-11-24 2002-07-31 Bookham Technology Plc Fabrication of integrated circuit
US6930256B1 (en) * 2002-05-01 2005-08-16 Amkor Technology, Inc. Integrated circuit substrate having laser-embedded conductive patterns and method therefor
JP2003022850A (ja) * 2001-07-09 2003-01-24 Tokyo Electron Ltd フィードスルーの製造方法およびフィードスルー
US7670962B2 (en) 2002-05-01 2010-03-02 Amkor Technology, Inc. Substrate having stiffener fabrication method
US9691635B1 (en) 2002-05-01 2017-06-27 Amkor Technology, Inc. Buildup dielectric layer having metallization pattern semiconductor package fabrication method
US7548430B1 (en) 2002-05-01 2009-06-16 Amkor Technology, Inc. Buildup dielectric and metallization process and semiconductor package
US10811277B2 (en) 2004-03-23 2020-10-20 Amkor Technology, Inc. Encapsulated semiconductor package
US11081370B2 (en) 2004-03-23 2021-08-03 Amkor Technology Singapore Holding Pte. Ltd. Methods of manufacturing an encapsulated semiconductor device
US7145238B1 (en) 2004-05-05 2006-12-05 Amkor Technology, Inc. Semiconductor package and substrate having multi-level vias
US8826531B1 (en) 2005-04-05 2014-09-09 Amkor Technology, Inc. Method for making an integrated circuit substrate having laminated laser-embedded circuit layers
US7589398B1 (en) 2006-10-04 2009-09-15 Amkor Technology, Inc. Embedded metal features structure
US7752752B1 (en) 2007-01-09 2010-07-13 Amkor Technology, Inc. Method of fabricating an embedded circuit pattern
US8872329B1 (en) 2009-01-09 2014-10-28 Amkor Technology, Inc. Extended landing pad substrate package structure and method

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3060076A (en) * 1957-09-30 1962-10-23 Automated Circuits Inc Method of making bases for printed electric circuits
US3271180A (en) * 1962-06-19 1966-09-06 Ibm Photolytic processes for fabricating thin film patterns
US3264402A (en) * 1962-09-24 1966-08-02 North American Aviation Inc Multilayer printed-wiring boards
US3311966A (en) * 1962-09-24 1967-04-04 North American Aviation Inc Method of fabricating multilayer printed-wiring boards
US3369293A (en) * 1963-10-29 1968-02-20 Mc Donnell Douglas Corp Method of manufacturing etched circuitry
US3319317A (en) * 1963-12-23 1967-05-16 Ibm Method of making a multilayered laminated circuit board
US3476561A (en) * 1965-08-30 1969-11-04 Ibm Photoetch method

Also Published As

Publication number Publication date
FR2101773A5 (enExample) 1972-03-31
US3778900A (en) 1973-12-18
DE2144137A1 (de) 1972-03-09

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Legal Events

Date Code Title Description
PS Patent sealed [section 19, patents act 1949]
PLNP Patent lapsed through nonpayment of renewal fees