GB1325082A - Semiconductor devices - Google Patents
Semiconductor devicesInfo
- Publication number
- GB1325082A GB1325082A GB125971A GB125971A GB1325082A GB 1325082 A GB1325082 A GB 1325082A GB 125971 A GB125971 A GB 125971A GB 125971 A GB125971 A GB 125971A GB 1325082 A GB1325082 A GB 1325082A
- Authority
- GB
- United Kingdom
- Prior art keywords
- polycrystalline
- oxide
- region
- monocrystalline
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D99/00—Subject matter not provided for in other groups of this subclass
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/085—Isolated-integrated
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/115—Orientation
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/122—Polycrystalline
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/145—Shaped junctions
Landscapes
- Bipolar Transistors (AREA)
- Element Separation (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US649370A | 1970-01-28 | 1970-01-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| GB1325082A true GB1325082A (en) | 1973-08-01 |
Family
ID=21721155
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB125971A Expired GB1325082A (en) | 1970-01-28 | 1971-01-11 | Semiconductor devices |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US3621346A (https=) |
| JP (1) | JPS4936790B1 (https=) |
| CA (1) | CA925223A (https=) |
| DE (1) | DE2059506C2 (https=) |
| FR (1) | FR2077371B1 (https=) |
| GB (1) | GB1325082A (https=) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| NL166156C (nl) * | 1971-05-22 | 1981-06-15 | Philips Nv | Halfgeleiderinrichting bevattende ten minste een op een halfgeleidersubstraatlichaam aangebrachte halfge- leiderlaag met ten minste een isolatiezone, welke een in de halfgeleiderlaag verzonken isolatielaag uit door plaatselijke thermische oxydatie van het half- geleidermateriaal van de halfgeleiderlaag gevormd isolerend materiaal bevat en een werkwijze voor het vervaardigen daarvan. |
| JPS4936797U (https=) * | 1972-06-28 | 1974-04-01 | ||
| DE2429957B2 (de) * | 1974-06-21 | 1980-08-28 | Siemens Ag, 1000 Berlin Und 8000 Muenchen | Verfahren zur Herstellung einer dotierten Zone eines bestimmten Leitungstyps in einem Halbleiterkörper |
| US4178197A (en) * | 1979-03-05 | 1979-12-11 | International Business Machines Corporation | Formation of epitaxial tunnels utilizing oriented growth techniques |
| US4210470A (en) * | 1979-03-05 | 1980-07-01 | International Business Machines Corporation | Epitaxial tunnels from intersecting growth planes |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3316130A (en) * | 1963-05-07 | 1967-04-25 | Gen Electric | Epitaxial growth of semiconductor devices |
| US3475661A (en) * | 1966-02-09 | 1969-10-28 | Sony Corp | Semiconductor device including polycrystalline areas among monocrystalline areas |
| US3433684A (en) * | 1966-09-13 | 1969-03-18 | North American Rockwell | Multilayer semiconductor heteroepitaxial structure |
| NL163372C (nl) * | 1967-11-14 | 1980-08-15 | Sony Corp | Halfgeleiderinrichting, omvattende een monokristallijn halfgeleiderlichaam met een door aangroeien vanuit de dampfase verkregen halfgeleidende laag, die een gebied van monokristallijn materiaal en een gebied van polykristallijn materiaal omvat. |
| US3648128A (en) * | 1968-05-25 | 1972-03-07 | Sony Corp | An integrated complementary transistor circuit chip with polycrystalline contact to buried collector regions |
-
1970
- 1970-01-28 US US6493A patent/US3621346A/en not_active Expired - Lifetime
- 1970-12-03 DE DE2059506A patent/DE2059506C2/de not_active Expired
- 1970-12-11 JP JP45109644A patent/JPS4936790B1/ja active Pending
-
1971
- 1971-01-07 FR FR7100861A patent/FR2077371B1/fr not_active Expired
- 1971-01-11 GB GB125971A patent/GB1325082A/en not_active Expired
- 1971-01-25 CA CA103626A patent/CA925223A/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| FR2077371A1 (https=) | 1971-10-22 |
| DE2059506C2 (de) | 1983-02-24 |
| DE2059506A1 (de) | 1971-08-05 |
| CA925223A (en) | 1973-04-24 |
| FR2077371B1 (https=) | 1974-03-22 |
| US3621346A (en) | 1971-11-16 |
| JPS4936790B1 (https=) | 1974-10-03 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PS | Patent sealed [section 19, patents act 1949] | ||
| PCNP | Patent ceased through non-payment of renewal fee |