GB1314267A - Semiconductor wafers and pllets - Google Patents

Semiconductor wafers and pllets

Info

Publication number
GB1314267A
GB1314267A GB2137370A GB2137370A GB1314267A GB 1314267 A GB1314267 A GB 1314267A GB 2137370 A GB2137370 A GB 2137370A GB 2137370 A GB2137370 A GB 2137370A GB 1314267 A GB1314267 A GB 1314267A
Authority
GB
United Kingdom
Prior art keywords
zone
layer
major surface
central
type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB2137370A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
General Electric Co
Original Assignee
General Electric Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by General Electric Co filed Critical General Electric Co
Publication of GB1314267A publication Critical patent/GB1314267A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/104—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices having particular shapes of the bodies at or near reverse-biased junctions, e.g. having bevels or moats
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D18/00—Thyristors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D18/00—Thyristors
    • H10D18/80—Bidirectional devices, e.g. triacs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/80—PNPN diodes, e.g. Shockley diodes or break-over diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P54/00—Cutting or separating of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/461—Leadframes specially adapted for cooling
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/134—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations being in grooves in the semiconductor body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/59—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/926—Multiple bond pads having different sizes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/028—Dicing

Landscapes

  • Thyristors (AREA)
GB2137370A 1969-05-05 1970-05-04 Semiconductor wafers and pllets Expired GB1314267A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US82168869A 1969-05-05 1969-05-05

Publications (1)

Publication Number Publication Date
GB1314267A true GB1314267A (en) 1973-04-18

Family

ID=25234052

Family Applications (1)

Application Number Title Priority Date Filing Date
GB2137370A Expired GB1314267A (en) 1969-05-05 1970-05-04 Semiconductor wafers and pllets

Country Status (7)

Country Link
US (1) US3628106A (https=)
BE (1) BE749971A (https=)
DE (2) DE2021691A1 (https=)
FR (1) FR2044768B1 (https=)
GB (1) GB1314267A (https=)
IE (1) IE34131B1 (https=)
SE (1) SE369646B (https=)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2610828A1 (de) * 1975-03-26 1976-10-07 Philips Nv Thyristor mit passivierter oberflaeche
DE2611363A1 (de) * 1975-03-26 1976-10-07 Philips Nv Verfahren zur herstellung einer halbleiteranordnung
US4375125A (en) 1980-03-07 1983-03-01 U.S. Philips Corporation Method of passivating pn-junction in a semiconductor device
CN109307981A (zh) * 2017-07-26 2019-02-05 天津环鑫科技发展有限公司 一种gpp生产的光刻版工艺

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3908187A (en) * 1973-01-02 1975-09-23 Gen Electric High voltage power transistor and method for making
US3943013A (en) * 1973-10-11 1976-03-09 General Electric Company Triac with gold diffused boundary
JPS5318380B2 (https=) * 1974-06-05 1978-06-14
US4063272A (en) * 1975-11-26 1977-12-13 General Electric Company Semiconductor device and method of manufacture thereof
GB1563421A (en) * 1975-12-18 1980-03-26 Gen Electric Polyimide-siloxane copolymer protective coating for semiconductor devices
JPS5346285A (en) * 1976-10-08 1978-04-25 Hitachi Ltd Mesa type high breakdown voltage semiconductor device
JPS56103447A (en) * 1980-01-22 1981-08-18 Toshiba Corp Dicing method of semiconductor wafer
US4814296A (en) * 1987-08-28 1989-03-21 Xerox Corporation Method of fabricating image sensor dies for use in assembling arrays
FR2666174B1 (fr) * 1990-08-21 1997-03-21 Sgs Thomson Microelectronics Composant semiconducteur haute tension a faible courant de fuite.
US5313094A (en) * 1992-01-28 1994-05-17 International Business Machines Corportion Thermal dissipation of integrated circuits using diamond paths
US5590460A (en) 1994-07-19 1997-01-07 Tessera, Inc. Method of making multilayer circuit
US5789302A (en) * 1997-03-24 1998-08-04 Siemens Aktiengesellschaft Crack stops
US6492201B1 (en) 1998-07-10 2002-12-10 Tessera, Inc. Forming microelectronic connection components by electrophoretic deposition
WO2013156891A1 (en) * 2012-04-16 2013-10-24 Koninklijke Philips N.V. Method and apparatus for creating a w-mesa street
CN108475665B (zh) 2015-11-05 2022-05-27 日立能源瑞士股份公司 功率半导体器件
DE102016124670B4 (de) * 2016-12-16 2020-01-23 Semikron Elektronik Gmbh & Co. Kg Thyristor mit einem Halbleiterkörper
DE102016124669B3 (de) * 2016-12-16 2018-05-17 Semikron Elektronik Gmbh & Co. Kg Thyristoren mit einem jeweiligen Halbleiterkörper

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1182353C2 (de) * 1961-03-29 1973-01-11 Siemens Ag Verfahren zum Herstellen eines Halbleiter-bauelements, wie Halbleiterstromtor oder Flaechentransistor, mit einer hochohmigen n-Zone zwischen zwei p-Zonen im Halbleiter-koerper
BE623187A (https=) * 1961-10-06
US3241010A (en) * 1962-03-23 1966-03-15 Texas Instruments Inc Semiconductor junction passivation
BE639633A (https=) * 1962-11-07
GB1030669A (en) * 1964-12-02 1966-05-25 Standard Telephones Cables Ltd Semiconductor devices
US3442722A (en) * 1964-12-16 1969-05-06 Siemens Ag Method of making a pnpn thyristor
NL6603372A (https=) * 1965-03-25 1966-09-26
US3283224A (en) * 1965-08-18 1966-11-01 Trw Semiconductors Inc Mold capping semiconductor device
US3492174A (en) * 1966-03-19 1970-01-27 Sony Corp Method of making a semiconductor device
GB1110993A (en) * 1967-01-09 1968-04-24 Standard Telephones Cables Ltd Semiconductors

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2610828A1 (de) * 1975-03-26 1976-10-07 Philips Nv Thyristor mit passivierter oberflaeche
DE2611363A1 (de) * 1975-03-26 1976-10-07 Philips Nv Verfahren zur herstellung einer halbleiteranordnung
US4375125A (en) 1980-03-07 1983-03-01 U.S. Philips Corporation Method of passivating pn-junction in a semiconductor device
CN109307981A (zh) * 2017-07-26 2019-02-05 天津环鑫科技发展有限公司 一种gpp生产的光刻版工艺
CN109307981B (zh) * 2017-07-26 2022-03-22 天津环鑫科技发展有限公司 一种gpp生产的光刻版工艺

Also Published As

Publication number Publication date
US3628106A (en) 1971-12-14
FR2044768A1 (https=) 1971-02-26
DE7016645U (de) 1973-11-08
IE34131B1 (en) 1975-02-19
FR2044768B1 (https=) 1974-02-01
DE2021691A1 (de) 1970-11-12
SE369646B (https=) 1974-09-09
IE34131L (en) 1970-11-05
BE749971A (fr) 1970-10-16

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Legal Events

Date Code Title Description
PS Patent sealed [section 19, patents act 1949]
PLNP Patent lapsed through nonpayment of renewal fees