GB1305029A - - Google Patents

Info

Publication number
GB1305029A
GB1305029A GB5559969A GB1305029DA GB1305029A GB 1305029 A GB1305029 A GB 1305029A GB 5559969 A GB5559969 A GB 5559969A GB 1305029D A GB1305029D A GB 1305029DA GB 1305029 A GB1305029 A GB 1305029A
Authority
GB
United Kingdom
Prior art keywords
synchronism
lines
nov
joined
outputs
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB5559969A
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of GB1305029A publication Critical patent/GB1305029A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/04—Distributors combined with modulators or demodulators
    • H04J3/047—Distributors with transistors or integrated circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/22—Means for limiting or controlling the pin/gate ratio
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G06F13/423—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with synchronous protocol
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/017545—Coupling arrangements; Impedance matching circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/156—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

1305029 Digital calculators SUMLOCK ANITA ELECTRONICS Ltd 5 Nov 1970 [13 Nov 1969 15 May 1970] 55599/69 and 23612/70 Heading G4A A digital electronic calculating machine includes two integrated circuits (IC's) 2, 4 joined by a line, the circuits being controlled by clock pulses and each having means for synchronizing their operation. A transmit I.C. portion 6 and a receive I.C. portion 8 on the separate chips are joined by lines 16, 18, 20, each I.C. having 18 outputs 10, 12, 14 inside the I.C. which are reduced to the lines 16, 18, 20 for external connection. A master oscillator 26 feeds respective multiplexers 22, 28 having output lines 27, 27<SP>1</SP> and sync. outputs 27a, 27a<SP>1</SP>, the former passing to M.O.S. switches (Figs. 2 and 3, not shown). Each chip includes a ring counter formed of MOS transistors whereby, if the I.C.'s are being operated in synchronism, signals are transmitted between the two I.C.'s and, if they are not in synchronism, the counters are stepped by clock pulses until they are in synchronism again. Another embodiment is described (Figs. 4 to 9, not shown).
GB5559969A 1969-11-13 1969-11-13 Expired GB1305029A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB5559969 1969-11-13
GB2361270 1970-05-15

Publications (1)

Publication Number Publication Date
GB1305029A true GB1305029A (en) 1973-01-31

Family

ID=26256622

Family Applications (1)

Application Number Title Priority Date Filing Date
GB5559969A Expired GB1305029A (en) 1969-11-13 1969-11-13

Country Status (4)

Country Link
US (1) US3683415A (en)
DE (1) DE2055999B2 (en)
GB (1) GB1305029A (en)
NL (1) NL7016689A (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3943488A (en) * 1974-07-16 1976-03-09 Fischer & Porter Co. Multiplex telemetering system
US3975712A (en) * 1975-02-18 1976-08-17 Motorola, Inc. Asynchronous communication interface adaptor
DE3177305T2 (en) * 1980-05-29 1994-06-16 Texas Instruments Inc Modular I / O system.
US4882505A (en) * 1986-03-24 1989-11-21 International Business Machines Corporation Fully synchronous half-frequency clock generator
US5117443A (en) * 1989-11-13 1992-05-26 Lucid, Inc. (Formerly Portable Computer) Method and apparatus for operating at fractional speeds in synchronous systems
FI113113B (en) * 2001-11-20 2004-02-27 Nokia Corp Method and device for time synchronization of integrated circuits

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1292698B (en) * 1961-10-23 1969-04-17 Kokusai Denshin Denwa Co Ltd Circuit arrangement for equalizing teletype characters when transmitting the time division multiplex signals of several synchronous time division multiplex group lines over a single time division multiplex main line
US3308434A (en) * 1963-01-09 1967-03-07 Teletype Corp Synchronization circuit for signal generators using comparison of a specific data message
US3402404A (en) * 1963-12-26 1968-09-17 Johnson Service Co Selective signal transmitting and indicating system
US3384873A (en) * 1965-01-22 1968-05-21 Collins Radio Co Selective calling system
US3461245A (en) * 1965-11-09 1969-08-12 Bell Telephone Labor Inc System for time division multiplexed signals from asynchronous pulse sources by inserting control pulses
US3516089A (en) * 1967-05-10 1970-06-02 Ind Instrumentations Inc Shift register controlled scanning function monitor

Also Published As

Publication number Publication date
DE2055999B2 (en) 1972-09-07
DE2055999A1 (en) 1971-05-19
US3683415A (en) 1972-08-08
NL7016689A (en) 1971-05-17

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Legal Events

Date Code Title Description
PS Patent sealed [section 19, patents act 1949]
PLNP Patent lapsed through nonpayment of renewal fees