GB1224436A - Data transmission arrangements - Google Patents

Abstract

1,224,436. Transfer between data stores. SIEMENS A.G. 27 Feb., 1969 [28 Feb., 1968], No. 10658/69. Heading G4C. In a data transmission arrangement, a logic feed-in circuit passes to the input of a receiving shift register either the output of a transmitting shift register or the output of the receiving shift register depending upon the output of a mask shift register, as the three registers are shifted in synchronism, whereby the data at locations of the transmitting register determined by the content of the mask register will be transmitted to corresponding locations of the receiving register. The output of the logic feed-in circuit may also be inserted into the input end of the mask register, and the output of the receiving register also inserted into the input end of the transmitting register. The transmitting and mask registers and the logic feed-in circuit are at a transmitting station and the receiving register is at a receiving station. Each 1 from the logic feed-in circuit reverses a first parity trigger at the transmitting station and a second parity trigger at the receiving station, the states of the two triggers being continuously compared at the receiving station to produce an error signal (e.g. to produce repetition of transfer) if unequal. As a modification, the inputs to the mask and transmitting registers above could be interchanged. A second embodiment differs from the first in having a plurality of receiving stations, addressable from the transmitting station. The logic feed-in circuits are in the receiving stations, and the triggers used in the error checks are fed from the output of the transmitting shift register instead of the logic feed-in circuit. A third embodiment permits any selected one of a plurality of extra registers at a receiving station to exchange data with the transmitting shift register via the receiving shift register, data transfer between the extra registers and the receiving shift register being parallel by bit.