DE1909418B2 - ARRANGEMENT FOR TRANSFERRING THE CONTENT OF THE DATA CONTAINED IN INDIVIDUAL POSITIONS OF A SLIDING REGISTER TO ANOTHER SLIDING REGISTER - Google Patents

Description

The invention relates to an arrangement for transmitting data to selected, in a Mask register set positions of a first sending register are stored in corresponding Setting a receiving register. It is known to serialize the entire contents of a shift register into a to transfer another shift register. For this purpose, the output of the send register is connected to the input of the receiving register connected via a single line and both registers with common Shift clock pulses applied. This is done before the transmission in the receiving

^derRe -

between shift registers »loaded.

through, Sihr

ha.ten «* * ~ _{gm of the control unit χ}

housed clock generator T delivered to the

Are Empf.ngsreg.ster with a jbgedeck ^ g ^ be, with only ^{non-mas, k} ^ ^rte _n £ ^e *, _askieruni loaded with new data .to M is djerung in so-called pardWen Dagnubetrag g between two registers / * ^k ? ^nnt : ™ ^r _T "" _chahun .

5 ⁸ pp

_one
U.N

NAND gate

NT

Catte, Λ.

₃ *

Tt

-

aiiL

in the case of parallel transmission so ^ such as the Raster Meil 16 or 24. There are also lines for the door output signals and receiving pulses

The object of the invention "t ej the λ at connecting lines, ^ ^ ktronischen ^{cna '1} connector points, etc., of the U» ^ f ^ äJlL · transmission of data between registers is ^e. to reduce. Furthermore, the new arrangement should enable the occurrence of errors in the transmission with a high seven "" Λ "en ^ nnd according to this Au ^ d -bycn that the send register, the Empiangsregisier u, mask register as a shift register; ^ a-gjüde nd and« In response to one of the position indicators 1 ^ _{7 the} same number of clock pulses -

that the ^^^ the receiving register g

circuit are connected.

from the mask register J

either the output signal of the

de <; F. Reception register for the receipt of the

registers through. Amfiihrunc-

Using the drawing m ^ r Ajisfuh ™ n ^ b | games are shown
finduna as well as other advantages and described and explained in more detail

Fig. 1 shows the Pnnzipschaltbdd emer ^ processing arrangement for masked data exchange between two shift registers; in ^^^^^^^^

F i e. 2 is the function of ^ "^ i ^ ™ according to Fig. 1 in the transmission of data m

Direction and in. Directives

F. g. 3 when transmitting in both directions

clarifies:.

Fig. 4 shows the Pnnzipscfaaltold a circuit arrangement, m of the data in a shift register and storage before other shift registers are connected. ausLc to be exchanged; in

Fig. 5 is the schematic diagram of a arrangement shown. in. ^^, J Mix data exchange emeni «« «g ^^ register and several receiving shift registers

1, s, with 1 a central control unit loading

5 »

. η

e. ^ ^ _{dcr director} " _{tell h} ,

4: 1 reducing frequency divider FT ^ _β? . _{En start signal}

_{ß7 so} for the output pulses of the

-eremh eit ^

Also receives pushing impulses from the Tak ^ L _or T and its positions can be freely selected with fc ^ ^^ _{or> lf gcseUt} ^ _erde ".

_{Places in the register that are occupied, in the exemplary} embodiment with a "1" digit, are also transferred to corresponding places in the., ER . The output signals of the i » _{eT * _{SR and E} R and of the maskΓ? Sden one in the control unit 1 ^ _logical input circuit LE, the

^ g ^ £ _{£ / jv hold t and}

u Dependency on what is fed

J ¹¹ S ¹¹ ", h ^ iHf- whether that arrives from register ER-

^ S Saf oSerias via a 'Feedback Sg r pending output signal of the register ER

Reeister ΕΛ is entered. Fie ~> the expiration of a mas-J _n ^ D ^ nSbertragunf is between four-digit reform as an example - represented _svm bolisch. The three registers SR. ξ .; _{Α and} > - _Ä have the content shown in'zeTl.TO \ before the start of the transfer. _{The data} before the transfer are “signed” by sign

^ indicates. With each clock pulse the Incn ^ p, ^ i _sle r is shifted to the right, so that with ^, ", T clock pulse of the logical input switch ^ - - ^ _other ^ _{ster S} R a logic> 0-

tunj ll ^^ _masks rcgister MR and the Emr-L ER each supplies a logical "1"

* Effect of the mask register that _{5αιάαφαα} ^ SR is in the receiving inputted so that the register ^^ '^ s in _the dargestellhaben line I. With the second clock pulse _input vnrd sc _h a] tung turn zuseführt from the eme "1". so as to turn _the £ ^ e ^ psters SR in the Emp ^ _{ER κτ e,} ngegeben, and there is s.cr dm second clock pulse in the line II dargc- _1; "and tying next Taktimpi:. '> -s . DA »ESL al of Maskenreg.sters, 0 .. - Jass dades receiving register ER .π d.esen y ^ ^ ^ ^ _{n Ejngan |, desse} iben gegeber

will. After the fourth and last clock pulse, see chap

5 6

accordingly a »0« is read into the receive register ER or MR or both. On the other hand,

enrolled. The end result is in line IV if there is one in all stages of the mask register MR

posed. Since "1" is entered in the first two digits of the mask, the contents of the ER register at

registers MR was always a "0" at the beginning, read was destroyed. Finally, individual bodies can

ben must be set in the first two positions of the receive 5 of the mask register, so that when reading

registers ER keep the original data. The in the corresponding places of the register ER of the

original data of the last two digits, in original content is destroyed. The content of the

where a »1« in each of the other positions in the trademark register MR is retained and becomes at the same time

was saved, were written into the mask register by the last two digits, so that

len of the send register SR replaced. io is a masked reading.

With the device according to Fig. 1, the described data circulation can be used for control

can be exploited with the masked transmission of the content of the purpose. After the

Send register SR in the receive register ER DES data transfer, the contents of the register ER

sen original content entered into the register SR by checking the content of the register MR or SR

will read. To this end, according to a further development, 15 is checked without the content of the register

the invention of additionally querying the output of the register ER via ER,

a read line / with the input of the SR register When transferring particularly important data,

tied together. e.g. of control commands is a data backup

The arrangement according to the invention can be extended for checking necessary to recognize disturbed values and for trolling purposes so that the transmission can be repeated at the same time as the masked transmission of the masked ones. With the new circuit arrangement, with the content of the output of the logic input circuit, a highly effective data LE can be achieved during the transfer via a line m in the mask register backup with very little effort. If the logic input circuit is in the data backup it is known to accommodate the number of devices 2, then the control also extends to the transmission path 2 contained in a series of information "1" elements. Count and determine whether the number just has the in F i g. 1 embodiment shown, when is numbered or odd. If the logic input circuit in the control unit is even, a "1" unit is placed in an additional position, the advantage that the number is ben, so that the number becomes odd. Am of the transmission lines is very low. 30 recipients are checked for odd numbers

In such an arrangement there is an information and. if the number of "1" elements is an even number circulation instead of, as illustrated in FIG. 3. an error signal triggered. With this procedure is light. In line 0, as in FIG. 2, there can be double errors, for example the deletion of an even-numbered content of the register SR. of the mask register MR numerous number of pulses that are not recognized, and the register ER is entered. To improve the control, a further development of the invention is therefore proposed after being stored in the registers SR and MR. Data are to be provided by "single" and the data stored in the register ER on the sending side and the receiving side is to be provided by double underlining the counting stage and thus the number of counting stages is indicated. With the first clock pulse, "1" elements are counted, the status of this Since a "1" 40 lers is constantly available in the last position of the mask register via a control line k , a "0" is to be transferred from the register SR to the register and transferred there by means of a control ER. This>; 0 "is at the same time written into the circuit with the status of the corresponding highest digit of the mask register AiR. The counters can, for example, also be the bistable flip-flops Kl and Kl in the last digit of the register ER , the "1" in the first digit of the register SR is written to the negative or positive pulse edges n execution clock pulse of the memory example shown in line I is designed as a so-called half adder, the state of the registers. With the second clock pulse can consist of NAND gates, Vl to .V4, the register SR becomes a "1" in the register, which is transferred as modules in integrated technology to the ER and the mask register AiR as well as 50 access. The control circuit has written a "0" in the register SR from the register ER so that it only emits an output signal. With the third clock pulse, the output of the register ER will be "1" when its two inputs are different and with four zucefiihii. Therefore, the first clock pulse triggers a "0" in the event of a malfunction, a malfunction message. so all registers entered. After completion 55 that double faults are reliably recognized. With one of the transfers, ER and MR are in the registers Of course, the original content of all transmitted data transmitted in a masked manner can be saved in such a test circuit; for the verification of register SR and in the register SR of the original reduction of the effort, however, one will refer to the content of the register ER. It is of course also possible to save the loan entered in the register ER , restrict the masked content in the data and the data output by this in the register SR and the original content of the register.

Write ER in the mask register MR . Here- Often data from the control unit is not

to is only the line g to the input of only a single device 3, but to several

Register SR and transmit the line / to the input of the parallel-connected devices.

To lead mask register MR. 65 len the possibilities of exchanging information

Are the registers SR and MR remain in place before the start of a. Fig. 4 shows schematically a

If the transmission is deleted, the content of the re- such arrangement is deleted. The control unit 1 also contains

register ER non-destructive in one of the registers SR in turn a shift register SR and a mask

register MR and a control counting stage Kl. The data transmission between the memories Sp 1 bis

Output lines of the control unit 1, the corresponding Sp η and the register ER can be run in parallel

according to the in F i g. 1 chosen because they are immediately adjacent

are connected to busbars, and hence the line expense in this case

namely with a (Sk) for the information about 5 does not play a major role. An additional data backup

Data backup, an (SD) for the output signal is generally used for this parallel transmission

of the register SR, one (SO not necessary for the output signal.

the registers F i g contained in the individual devices. 6 shows the circuit diagram ER1 to ERn for clarification, one (St) for the clock pulses and such a device, with finally one (Sm) for the output signal, for the sake of clarity, only one memory being shown. The Mask Register Register. The ER again consists of four stages on the busbars, e.g. B. flip-flops, devices 31, 32 to 3 π via the one inputs of each of which two gates 0 are connected upstream. The coincidence gates connected in the execution flip-flops are therefore either from the respective vorrungsbeispiel NAND gates NA and prepared on their switched flip-flop or from a signal lying on the second inputs of addressing lines A1 to A η communicated B signal. Their introductions are via which the devices can be switched from an address control Ad invention contained in the course of a further addition to the control unit 1, coincidence gates with an input for to the busbars. a switching pulse. After arrival of a In the embodiment, each device contains clock pulse via the line t or by addition to the registers ER and Kontrollzählstufen 20 switch pulse, the pre-K is taken 2, a control circuit H and a logical inputs preparation signal in the register ER at the terminal DS, gear shift LE. However, it is possible to con- The first stage of the register ER is preceded by a logical troll circuits and the logic input circuits input circuit LE to unite said Ausgen each in a single circuit output signals of the send register SR, the mask and those in the control unit to attach. 25 registers and the receiving register ER supplied to F i g. 5 shows a device that can be several additional. This logic input circuit is identical to memories 5p 1, Sp2 to Spn , the content of which corresponds to that shown in FIG. The outputs of the register SR ( not shown) of a control multivibrator of the shift register feed the collecting unit to be exchanged. This exchange seemed to which the storage stages are appropriately connected only with the aid of the single receipt that they are carried out by the output chip start register ER . For this purpose, output circuits D 1 or D 2... Or D η des are prepared at a voltage corresponding stages of the shift register ER. After supplying a takeover selected memory 5p 1 or .... 5p "a transit pulse to the transfer circuit Un is the set-connect signal, after which the memory contents to contents of shift register ER to the memory 5p η a bus bar B is switched and transmitted from there 35 . At the output of each storage stage, after a switching pulse has been applied to the terminal, coincidence gates D n, for example NAND gates DS, are transferred to register ER . It is then provided which busbars B feed, and the above-described information exchange between the inputs of the flip-flops of the shift register and the control unit can take place. After you are connected. If a signal is applied to the coincidence of the same, the content of the register ER, 40 denzgattern Dn , the memory content from which is given to a busbar A is switched through to the busbars B by means of the NAND gates and a takeover pulse is sent to one of the memories can from there by means of an in-5p 1 to Spn upstream takeover circuits pulses to terminal DS in the shift register L ^R L, L'2 are stored again to Un. Which are taken over.

For this purpose 2 sheets of drawings

Claims (13)

Patent claims: 1. Arrangement for transmitting data that are stored in selected places of a transmit register set in a mask register, in corresponding places of a receive register, characterized in that the transmit register (SR), the receive register (ER) and the mask register (MR) are designed as shift registers and are synchronous with one of the number of lines of registers equal number are vveitergeschaltet of clock pulses, that the outputs of these registers reproducing circuit with a receiving register (ER) upstream logic input (LE) are connected, which in dependence of the of the Ma ^c kenregister (MR) signal supplied to either the Ausgangssigna! of the send (SR) or that of the receive register (ER) to the input of the receive register (ER) ao. 2. Arrangement according to claim 1, characterized in that a read line (/) is led from the output of the receiving register (ER) to the input of the transmitting register (SR) . as 3. Arrangement according to claim 1 or 2, characterized in that a line (g) is led from the output of the logic input circuit (LE) to the input of the mask register (MR). via which the data written in the receive register (ER) can be fed to the mask register (MR). 4. Arrangement according to claim 1, characterized in that the output of the receiving register (ER) with the input of the mask register (MR) via a read line and or the output of the logic input circuit (LE) with the input of the sending register (SR) via a Line is connected. via which the data written in the receive register (ER) can be fed to the mask register (MR). 5. Arrangement according to one of claims 2 to 4, characterized in that the transmission register (SR). the mask register (MR) and the logic input circuit are arranged in a control unit (1) and the receiving register (ER) is arranged in a device (3) that is spatially separated therefrom. 6. Arrangement according to one of claims 1 to 5, characterized in that a counter (Kl or Kl) is connected to both ends of at least one transmission line (g) , which counts the number of the transmitted or transmitted. Counts pulses and the state of which can be checked with that of the other counter (K 2 or Kl) in a comparison circuit (H) which emits an error signal at different counter readings. 7. Arrangement according to claim 6, characterized in that the counters (Kl, K2) are bistable multivibrators (Kl, K 2) to which the comparison circuit (H) is connected. 8. Arrangement according to claim 6 or 7, characterized in that the comparison circuit (H) consists of four NAND gates each with two inputs, one of which (ΛΊ) is connected to both flip-flops (Kl, Kl) , two more (N 2, N 3), with the outputs of which the inputs of the fourth (A'4) are connected, with their one input to the first NAND gate (Nl) and with their other input to a trigger stage (Kl or K 2). are connected. 9. Arrangement according to one of claims 1 to 8, characterized in that the receiving register (ER) memories (5p 1 to Sp n) are assigned, the contents of which are interchangeable with that of the receiving register. 10. The arrangement according to claim 9, characterized in that the inputs of the memory (Sp 1 to Spn) via bus lines (A) and each via a transfer circuit (Ul to Un) to the receiving register (ER) and the outputs of the memory via one each Output circuit (Dl to Dn) are connected to a busbar (B) to which the input of the receiving register (ER) is connected, so that the transfer circuits (U 1 to Un) each have an input for a pulse which causes the receiving register content to be transferred to the memory and the output circuits (D 1 to Dn) each have an input for a switch-through pulse which causes the output of the memory contents to the bus (5). 11. The arrangement according to claim 10 or 11, characterized in that the stages of the receiving register (ER) and the stages of the memory (5p 1 to Sp n) are connected in parallel with one another. 12. Arrangement according to one of claims 9 to 11, characterized in that the inputs of the reception register stages coincidence gate with an input for a switching pulse included, which causes the takeover of the signal on the bus (ß). 13. Arrangement according to one of claims 1 to 12, characterized in that a plurality of receiving registers (ERl. ERl to ERn) and possibly associated logical input sounds (LEI to LEn), flip-flops (K 21 to K2n) and control circuits (Hl to Hn) are provided which are connected to the control unit via bus lines (Sk. Sd. Sl, St, Sm) , and that, by means of an address control (Ad), the receiving registers (ERl to ERn) and the respective circuits assigned to them via addressing lines designed as stub lines (al to on) can be switched on.