GB1208029A - Method for manufacturing a semiconductor device - Google Patents
Method for manufacturing a semiconductor deviceInfo
- Publication number
- GB1208029A GB1208029A GB3001268A GB3001268A GB1208029A GB 1208029 A GB1208029 A GB 1208029A GB 3001268 A GB3001268 A GB 3001268A GB 3001268 A GB3001268 A GB 3001268A GB 1208029 A GB1208029 A GB 1208029A
- Authority
- GB
- United Kingdom
- Prior art keywords
- window
- region
- base contact
- layer
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 title abstract 2
- 238000004519 manufacturing process Methods 0.000 title 1
- 238000000034 method Methods 0.000 title 1
- 239000011521 glass Substances 0.000 abstract 5
- 239000012535 impurity Substances 0.000 abstract 5
- 238000000151 deposition Methods 0.000 abstract 4
- 229910052581 Si3N4 Inorganic materials 0.000 abstract 2
- 238000010438 heat treatment Methods 0.000 abstract 2
- 239000000463 material Substances 0.000 abstract 2
- 229910052759 nickel Inorganic materials 0.000 abstract 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 abstract 1
- 229910052787 antimony Inorganic materials 0.000 abstract 1
- 229910052785 arsenic Inorganic materials 0.000 abstract 1
- 229910052796 boron Inorganic materials 0.000 abstract 1
- 229910052804 chromium Inorganic materials 0.000 abstract 1
- 229910052802 copper Inorganic materials 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 abstract 1
- 238000005530 etching Methods 0.000 abstract 1
- 238000010574 gas phase reaction Methods 0.000 abstract 1
- 229910052737 gold Inorganic materials 0.000 abstract 1
- 229910052749 magnesium Inorganic materials 0.000 abstract 1
- 239000002184 metal Substances 0.000 abstract 1
- 229910052751 metal Inorganic materials 0.000 abstract 1
- 229910052750 molybdenum Inorganic materials 0.000 abstract 1
- 229910052757 nitrogen Inorganic materials 0.000 abstract 1
- 229910052698 phosphorus Inorganic materials 0.000 abstract 1
- 229910052697 platinum Inorganic materials 0.000 abstract 1
- 229910052710 silicon Inorganic materials 0.000 abstract 1
- 229910052814 silicon oxide Inorganic materials 0.000 abstract 1
- 229910052709 silver Inorganic materials 0.000 abstract 1
- 229910000679 solder Inorganic materials 0.000 abstract 1
- 238000004544 sputter deposition Methods 0.000 abstract 1
- 229910052715 tantalum Inorganic materials 0.000 abstract 1
- 229910052719 titanium Inorganic materials 0.000 abstract 1
- 229910052721 tungsten Inorganic materials 0.000 abstract 1
- 229910052720 vanadium Inorganic materials 0.000 abstract 1
- 229910052726 zirconium Inorganic materials 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/291—Oxides or nitrides or carbides, e.g. ceramics, glass
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
1,208,029. Semi-conductor devices. HITACHI Ltd. 24 June, 1968 [28 June, 1967], No. 30012/68. Heading H1K. Regions of opposite conductivity type are formed in a wafer by depositing a first impurity material of one conductivity type through a window in a first insulating layer, covering with a second insulating layer, forming a new window laterally spaced from the first window and diffusing-in a second impurity of the opposite conductivity type to that of the first impurity from the gas phase. The deposited first impurity material may be diffused-in prior to or simultaneously with the diffusion of the second impurity. A planar transistor is produced by forming a P-type base region (2) in one face of an N-type body (1), forming a window (4) in an overlying oxide layer (3a), depositing P to form a glass layer (5) over the whole surface, heating to diffuse in the P to form on N type emitter region (6), covering the glass layer with a silicon oxide, silicon nitride or alumina layer (7), e.g. by gas phase reaction, etching a further window (8) to expose part of the base region, and diffusing-in B from the gas phase to form a P+type base contact region (9), Figs. 1(a) to (f) (not shown). The emitter region (6) and base contact region (9) are exposed and ohmic contacts (21, 22) are provided by depositing a metal such as Cr, Ti, Ta, Mo, W, Ni, Mg, V, Zr, Figs. 1(g) and (h) (not shown). The contacts are provided with overlying layers 23, 24 of Au, Ag or Pt to which a Au lead may be secured, or of Cu or Ni to which a solder electrode may be secured. In a second embodiment, Fig. 2 (not shown), the base contact and emitter regions are formed by depositing B, to form a boron glass layer, which may be removed except where the base contact region is to be formed, covering the glass with a layer of silicon nitride by sputtering Si and N, forming a window and heating in a P containing atmosphere to simultaneously drive in the B from the glass layer to form the base contact region and to diffuse-in P to form the emitter region. PNP transistors may also be formed using P, As or Sb to form the N + type base contact regions.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4098067 | 1967-06-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| GB1208029A true GB1208029A (en) | 1970-10-07 |
Family
ID=12595565
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB3001268A Expired GB1208029A (en) | 1967-06-28 | 1968-06-24 | Method for manufacturing a semiconductor device |
| GB4882069A Expired GB1208030A (en) | 1967-06-28 | 1968-06-24 | A semiconductor device |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB4882069A Expired GB1208030A (en) | 1967-06-28 | 1968-06-24 | A semiconductor device |
Country Status (2)
| Country | Link |
|---|---|
| FR (1) | FR1571170A (en) |
| GB (2) | GB1208029A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE1764824A1 (en) * | 1968-08-13 | 1971-11-04 | Siemens Ag | Field effect transistor |
| GB8907898D0 (en) * | 1989-04-07 | 1989-05-24 | Inmos Ltd | Semiconductor devices and fabrication thereof |
-
1968
- 1968-06-24 GB GB3001268A patent/GB1208029A/en not_active Expired
- 1968-06-24 GB GB4882069A patent/GB1208030A/en not_active Expired
- 1968-06-27 FR FR1571170D patent/FR1571170A/fr not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| GB1208030A (en) | 1970-10-07 |
| FR1571170A (en) | 1969-06-13 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PS | Patent sealed | ||
| PCNP | Patent ceased through non-payment of renewal fee |