GB1039257A - Semiconductor devices - Google Patents

Semiconductor devices

Info

Publication number
GB1039257A
GB1039257A GB21600/65A GB2160065A GB1039257A GB 1039257 A GB1039257 A GB 1039257A GB 21600/65 A GB21600/65 A GB 21600/65A GB 2160065 A GB2160065 A GB 2160065A GB 1039257 A GB1039257 A GB 1039257A
Authority
GB
United Kingdom
Prior art keywords
layer
grown
semi
wafer
conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB21600/65A
Inventor
Roger Cullis
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STC PLC
Original Assignee
Standard Telephone and Cables PLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Standard Telephone and Cables PLC filed Critical Standard Telephone and Cables PLC
Priority to GB21600/65A priority Critical patent/GB1039257A/en
Priority to DE19661564147 priority patent/DE1564147A1/en
Priority to NL6606800A priority patent/NL6606800A/xx
Priority to FR62316A priority patent/FR1500841A/en
Publication of GB1039257A publication Critical patent/GB1039257A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
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    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
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    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
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    • H01L2924/01024—Chromium [Cr]
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    • H01L2924/01057—Lanthanum [La]
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    • H01L2924/01—Chemical elements
    • H01L2924/01067—Holmium [Ho]
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    • H01L2924/01074—Tungsten [W]
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    • H01L2924/013—Alloys
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    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
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    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19042—Component type being an inductor
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    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30105—Capacitance

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Recrystallisation Techniques (AREA)
  • Die Bonding (AREA)

Abstract

1,039,257. Semi-conductor devices. STANDARD TELEPHONES & CABLES Ltd. May 21, 1965, No. 21600/65. Heading H1K. In the manufacture of a semi-conductor device a layer of semi-conductor material is grown on one face of a semi-conductor wafer on the other side of which is grown or deposited an insulating layer which, after the formation of the semiconductor device in or on the grown semiconductor layer, is bonded directly or indirectly to a metallic member which may form part of the device encapsulation. In one embodiment a medium resistivity layer of N-type silicon is grown on one side of a low resistivity wafer of the same material. The other side of the wafer is lapped to reduce its thickness. The body is then heated in oxygen saturated with steam to produce silica coatings on both faces. A very high resistivity layer of polycrystalline silicon is then deposited on to the silica coating on the lapped surface. On the other side of the body transistors are fabricated in the grown semiconductor layer by use of the planar process. The wafer is diced after evaporated and alloyed aluminium contacts have been provided for emitter, base, and collector of each transistor. Each die is bonded to a metallic header with gold or solder glass. In a second embodiment the starting wafer is of high resistivity and is of the opposite conductivity type to a low resistivity semi-conductor layer grown on one of its faces. A medium resistivity layer is grown in ohmic contact on the first grown layer and semi-conductor devices made in this second layer. An insulating layer is deposited or grown on the other wafer face. The structure may be bonded to a metallic header either by a metallic layer graded from chromium at the insulating layer to gold at the header, or by solder glass. Semi-conductors other than silicon may be used and silicon nitride or silicon monoxide may be used as the insulating material. Methods other than diffusion may be used to make the devices, for example localized epitaxial deposition or alloying.
GB21600/65A 1965-05-21 1965-05-21 Semiconductor devices Expired GB1039257A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
GB21600/65A GB1039257A (en) 1965-05-21 1965-05-21 Semiconductor devices
DE19661564147 DE1564147A1 (en) 1965-05-21 1966-05-07 Semiconductor device and manufacturing process
NL6606800A NL6606800A (en) 1965-05-21 1966-05-17
FR62316A FR1500841A (en) 1965-05-21 1966-05-20 Manufacturing process of a silicon planar transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB21600/65A GB1039257A (en) 1965-05-21 1965-05-21 Semiconductor devices

Publications (1)

Publication Number Publication Date
GB1039257A true GB1039257A (en) 1966-08-17

Family

ID=10165646

Family Applications (1)

Application Number Title Priority Date Filing Date
GB21600/65A Expired GB1039257A (en) 1965-05-21 1965-05-21 Semiconductor devices

Country Status (4)

Country Link
DE (1) DE1564147A1 (en)
FR (1) FR1500841A (en)
GB (1) GB1039257A (en)
NL (1) NL6606800A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL8004139A (en) * 1980-07-18 1982-02-16 Philips Nv SEMICONDUCTOR DEVICE.
DE10149774A1 (en) * 2001-10-09 2003-04-24 Bosch Gmbh Robert Process for packing electronic modules comprises applying a power semiconductor chip on a base plate, applying a logic chip on the base plate, connecting the logic chip with the semiconductor chip, and packing the module

Also Published As

Publication number Publication date
FR1500841A (en) 1967-11-10
DE1564147A1 (en) 1969-10-02
NL6606800A (en) 1966-11-22

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