FR1500841A - Manufacturing process of a silicon planar transistor - Google Patents

Manufacturing process of a silicon planar transistor

Info

Publication number
FR1500841A
FR1500841A FR62316A FR62316A FR1500841A FR 1500841 A FR1500841 A FR 1500841A FR 62316 A FR62316 A FR 62316A FR 62316 A FR62316 A FR 62316A FR 1500841 A FR1500841 A FR 1500841A
Authority
FR
France
Prior art keywords
manufacturing process
planar transistor
silicon planar
silicon
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
FR62316A
Other languages
French (fr)
Inventor
Roger Cullis
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
I T T IND
ITT Inc
Original Assignee
I T T IND
ITT Industries Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by I T T IND, ITT Industries Inc filed Critical I T T IND
Application granted granted Critical
Publication of FR1500841A publication Critical patent/FR1500841A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
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    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
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    • H01L2224/838—Bonding techniques
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    • H01L2924/1904—Component type
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    • H01L2924/30105—Capacitance

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Die Bonding (AREA)
  • Recrystallisation Techniques (AREA)
FR62316A 1965-05-21 1966-05-20 Manufacturing process of a silicon planar transistor Expired FR1500841A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB21600/65A GB1039257A (en) 1965-05-21 1965-05-21 Semiconductor devices

Publications (1)

Publication Number Publication Date
FR1500841A true FR1500841A (en) 1967-11-10

Family

ID=10165646

Family Applications (1)

Application Number Title Priority Date Filing Date
FR62316A Expired FR1500841A (en) 1965-05-21 1966-05-20 Manufacturing process of a silicon planar transistor

Country Status (4)

Country Link
DE (1) DE1564147A1 (en)
FR (1) FR1500841A (en)
GB (1) GB1039257A (en)
NL (1) NL6606800A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL8004139A (en) * 1980-07-18 1982-02-16 Philips Nv SEMICONDUCTOR DEVICE.
DE10149774A1 (en) 2001-10-09 2003-04-24 Bosch Gmbh Robert Process for packing electronic modules comprises applying a power semiconductor chip on a base plate, applying a logic chip on the base plate, connecting the logic chip with the semiconductor chip, and packing the module

Also Published As

Publication number Publication date
DE1564147A1 (en) 1969-10-02
NL6606800A (en) 1966-11-22
GB1039257A (en) 1966-08-17

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