GB1068199A - High voltage semiconductor device - Google Patents

High voltage semiconductor device

Info

Publication number
GB1068199A
GB1068199A GB4761864A GB4761864A GB1068199A GB 1068199 A GB1068199 A GB 1068199A GB 4761864 A GB4761864 A GB 4761864A GB 4761864 A GB4761864 A GB 4761864A GB 1068199 A GB1068199 A GB 1068199A
Authority
GB
United Kingdom
Prior art keywords
junction
groove
wafer
etch
plate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB4761864A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies Americas Corp
Original Assignee
International Rectifier Corp USA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US325873A external-priority patent/US3278347A/en
Priority claimed from US325872A external-priority patent/US3320496A/en
Application filed by International Rectifier Corp USA filed Critical International Rectifier Corp USA
Publication of GB1068199A publication Critical patent/GB1068199A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0661—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3085—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Thyristors (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

1,068,199. Semi-conductor devices. INTERNATIONAL RECTIFIER CORPORATION. Nov. 23, 1964 [Nov. 26, 1963], No. 47618/64. Heading H1K. A semi-conductor, e.g. silicon, wafer containing a plane PN junction extending completely across the wafer is provided with an annular groove 24 extending from one face of the wafer and breaking through the junction. The groove is formed by a two-stage etching process. In the first stage (Fig. 3, not shown) the base, edge and outer part of the top surface of the wafer are covered by an etch-resistant, e.g. PTFE, jig 20 and the inner part of the top surface by an etch-resistant plate 21. An acid etch then produces an annular groove of U- section just breaking through the junction. The plate 21 is then replaced by the smaller plate 23 of Fig. 4 and a second etching gives the groove the shape shown, in which the tangent to the inner surface of the groove at the plane of the junction makes an acute angle with the junction, e.g. between 10 and 60 degrees and preferable about 45 degrees. The groove is then filled (Fig. 5, not shown) and the entire surface of the device covered, with varnish. The completed device may be encapsulated, and if the encapsulation provides an inert environment the varnishing step may be omitted.
GB4761864A 1963-11-26 1964-11-23 High voltage semiconductor device Expired GB1068199A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US325873A US3278347A (en) 1963-11-26 1963-11-26 High voltage semiconductor device
US325872A US3320496A (en) 1963-11-26 1963-11-26 High voltage semiconductor device

Publications (1)

Publication Number Publication Date
GB1068199A true GB1068199A (en) 1967-05-10

Family

ID=26985151

Family Applications (2)

Application Number Title Priority Date Filing Date
GB4761964A Expired GB1068200A (en) 1963-11-26 1964-11-23 High voltage semiconductor device
GB4761864A Expired GB1068199A (en) 1963-11-26 1964-11-23 High voltage semiconductor device

Family Applications Before (1)

Application Number Title Priority Date Filing Date
GB4761964A Expired GB1068200A (en) 1963-11-26 1964-11-23 High voltage semiconductor device

Country Status (1)

Country Link
GB (2) GB1068200A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2359415A (en) * 2000-02-21 2001-08-22 Westcode Semiconductors Ltd Profiling of semiconductor wafer to prevent edge breakdown
CN109950308A (en) * 2019-03-20 2019-06-28 江苏东晨电子科技有限公司 Hyperbolicity table top thyristor and preparation method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2359415A (en) * 2000-02-21 2001-08-22 Westcode Semiconductors Ltd Profiling of semiconductor wafer to prevent edge breakdown
CN109950308A (en) * 2019-03-20 2019-06-28 江苏东晨电子科技有限公司 Hyperbolicity table top thyristor and preparation method thereof

Also Published As

Publication number Publication date
GB1068200A (en) 1967-05-10

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