GB0807101D0 - A method of dicing wafers to give high die strength - Google Patents

A method of dicing wafers to give high die strength

Info

Publication number
GB0807101D0
GB0807101D0 GBGB0807101.1A GB0807101A GB0807101D0 GB 0807101 D0 GB0807101 D0 GB 0807101D0 GB 0807101 A GB0807101 A GB 0807101A GB 0807101 D0 GB0807101 D0 GB 0807101D0
Authority
GB
United Kingdom
Prior art keywords
give high
high die
die strength
dicing wafers
dicing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GBGB0807101.1A
Other versions
GB2459302A (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Electro Scientific Industries Inc
Original Assignee
XSIL Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by XSIL Ltd filed Critical XSIL Ltd
Priority to GB0807101A priority Critical patent/GB2459302A/en
Publication of GB0807101D0 publication Critical patent/GB0807101D0/en
Priority to TW098113117A priority patent/TW201013766A/en
Priority to PCT/EP2009/054678 priority patent/WO2009127740A1/en
Publication of GB2459302A publication Critical patent/GB2459302A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/673—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere using specially adapted carriers or holders; Fixing the workpieces on such carriers or holders
    • H01L21/67346—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere using specially adapted carriers or holders; Fixing the workpieces on such carriers or holders characterized by being specially adapted for supporting a single substrate or by comprising a stack of such individual supports

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Dicing (AREA)
  • Laser Beam Processing (AREA)
GB0807101A 2008-04-18 2008-04-18 A method of dicing wafers to give high die strength Withdrawn GB2459302A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
GB0807101A GB2459302A (en) 2008-04-18 2008-04-18 A method of dicing wafers to give high die strength
TW098113117A TW201013766A (en) 2008-04-18 2009-04-20 A method of dicing wafers to give high die strength
PCT/EP2009/054678 WO2009127740A1 (en) 2008-04-18 2009-04-20 A method of dicing wafers to give high die strength

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB0807101A GB2459302A (en) 2008-04-18 2008-04-18 A method of dicing wafers to give high die strength

Publications (2)

Publication Number Publication Date
GB0807101D0 true GB0807101D0 (en) 2008-05-21
GB2459302A GB2459302A (en) 2009-10-21

Family

ID=39472344

Family Applications (1)

Application Number Title Priority Date Filing Date
GB0807101A Withdrawn GB2459302A (en) 2008-04-18 2008-04-18 A method of dicing wafers to give high die strength

Country Status (3)

Country Link
GB (1) GB2459302A (en)
TW (1) TW201013766A (en)
WO (1) WO2009127740A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7066263B2 (en) * 2018-01-23 2022-05-13 株式会社ディスコ Machining method, etching equipment, and laser processing equipment

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63164336A (en) * 1986-12-26 1988-07-07 Oki Electric Ind Co Ltd Manufacture of semiconductor device
US6498074B2 (en) * 1996-10-29 2002-12-24 Tru-Si Technologies, Inc. Thinning and dicing of semiconductor wafers using dry etch, and obtaining semiconductor chips with rounded bottom edges and corners
JP2002016021A (en) * 2000-06-28 2002-01-18 Toshiba Corp Production method of semiconductor chip and the semiconductor chip
JP3910843B2 (en) * 2001-12-13 2007-04-25 東京エレクトロン株式会社 Semiconductor element separation method and semiconductor element separation apparatus
AU2003233604A1 (en) * 2002-05-20 2003-12-12 Imagerlabs Forming a multi segment integrated circuit with isolated substrates
US7507638B2 (en) * 2004-06-30 2009-03-24 Freescale Semiconductor, Inc. Ultra-thin die and method of fabricating same
GB2420443B (en) * 2004-11-01 2009-09-16 Xsil Technology Ltd Increasing die strength by etching during or after dicing
JP4544143B2 (en) * 2005-06-17 2010-09-15 セイコーエプソン株式会社 Semiconductor device manufacturing method, semiconductor device, circuit board, and electronic apparatus

Also Published As

Publication number Publication date
WO2009127740A1 (en) 2009-10-22
TW201013766A (en) 2010-04-01
GB2459302A (en) 2009-10-21

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Legal Events

Date Code Title Description
COOA Change in applicant's name or ownership of the application

Owner name: ELECTRO SCIENTIFIC INDUSTRIES, INC.

Free format text: FORMER OWNER: XSIL TECHNOLOGY LIMITED

WAP Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1)